1be944d42SStephen WarrenNVIDIA Tegra30 AHUB (Audio Hub) 2be944d42SStephen Warren 3be944d42SStephen WarrenRequired properties: 495d36075SStephen Warren- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc. 5be944d42SStephen Warren- reg : Should contain the register physical address and length for each of 695d36075SStephen Warren the AHUB's register blocks. 795d36075SStephen Warren - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. 895d36075SStephen Warren - Tegra114 requires an additional entry, for the APBIF2 register block. 9be944d42SStephen Warren- interrupts : Should contain AHUB interrupt 1095d36075SStephen Warren- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each 1195d36075SStephen Warren entry contains the Tegra DMA controller's phandle and request selector. 1295d36075SStephen Warren If a single entry is present, the request selectors for the channels are 1395d36075SStephen Warren assumed to be contiguous, and increment from this value. 1495d36075SStephen Warren If multiple values are given, one value must be given per channel. 15*d8f64797SStephen Warren- clocks : Must contain an entry for each entry in clock-names. 16*d8f64797SStephen Warren See ../clocks/clock-bindings.txt for details. 1795d36075SStephen Warren- clock-names : Must include the following entries: 18*d8f64797SStephen Warren Tegra30 and later: 19*d8f64797SStephen Warren - d_audio 20*d8f64797SStephen Warren - apbif 21*d8f64797SStephen Warren - i2s0 22*d8f64797SStephen Warren - i2s1 23*d8f64797SStephen Warren - i2s2 24*d8f64797SStephen Warren - i2s3 25*d8f64797SStephen Warren - i2s4 26*d8f64797SStephen Warren - dam0 27*d8f64797SStephen Warren - dam1 28*d8f64797SStephen Warren - dam2 29*d8f64797SStephen Warren - spdif_in 30*d8f64797SStephen Warren Tegra114 and later additionally require: 31*d8f64797SStephen Warren - amx 32*d8f64797SStephen Warren - adx 33be944d42SStephen Warren- ranges : The bus address mapping for the configlink register bus. 34be944d42SStephen Warren Can be empty since the mapping is 1:1. 35be944d42SStephen Warren- #address-cells : For the configlink bus. Should be <1>; 36be944d42SStephen Warren- #size-cells : For the configlink bus. Should be <1>. 37be944d42SStephen Warren 38be944d42SStephen WarrenAHUB client modules need to specify the IDs of their CIFs (Client InterFaces). 39be944d42SStephen WarrenFor RX CIFs, the numbers indicate the register number within AHUB routing 40be944d42SStephen Warrenregister space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). 41be944d42SStephen WarrenFor TX CIFs, the numbers indicate the bit position within the AHUB routing 42be944d42SStephen Warrenregisters (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1). 43be944d42SStephen Warren 44be944d42SStephen WarrenExample: 45be944d42SStephen Warren 46be944d42SStephen Warrenahub@70080000 { 47be944d42SStephen Warren compatible = "nvidia,tegra30-ahub"; 48be944d42SStephen Warren reg = <0x70080000 0x200 0x70080200 0x100>; 49be944d42SStephen Warren interrupts = < 0 103 0x04 >; 50be944d42SStephen Warren nvidia,dma-request-selector = <&apbdma 1>; 5195d36075SStephen Warren clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, 5295d36075SStephen Warren <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, 5395d36075SStephen Warren <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, 5495d36075SStephen Warren <&tegra_car 110>, <&tegra_car 162>; 5595d36075SStephen Warren clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 5695d36075SStephen Warren "i2s3", "i2s4", "dam0", "dam1", "dam2", 5795d36075SStephen Warren "spdif_in"; 58be944d42SStephen Warren ranges; 59be944d42SStephen Warren #address-cells = <1>; 60be944d42SStephen Warren #size-cells = <1>; 61be944d42SStephen Warren}; 62