1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pwm/renesas,tpu-pwm.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car Timer Pulse Unit PWM Controller 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - renesas,tpu-r8a73a4 # R-Mobile APE6 17 - renesas,tpu-r8a7740 # R-Mobile A1 18 - renesas,tpu-r8a7742 # RZ/G1H 19 - renesas,tpu-r8a7743 # RZ/G1M 20 - renesas,tpu-r8a7744 # RZ/G1N 21 - renesas,tpu-r8a7745 # RZ/G1E 22 - renesas,tpu-r8a7790 # R-Car H2 23 - renesas,tpu-r8a7791 # R-Car M2-W 24 - renesas,tpu-r8a7792 # R-Car V2H 25 - renesas,tpu-r8a7793 # R-Car M2-N 26 - renesas,tpu-r8a7794 # R-Car E2 27 - renesas,tpu-r8a7795 # R-Car H3 28 - renesas,tpu-r8a7796 # R-Car M3-W 29 - renesas,tpu-r8a77961 # R-Car M3-W+ 30 - renesas,tpu-r8a77965 # R-Car M3-N 31 - renesas,tpu-r8a77970 # R-Car V3M 32 - renesas,tpu-r8a77980 # R-Car V3H 33 - renesas,tpu-r8a779a0 # R-Car V3U 34 - renesas,tpu-r8a779g0 # R-Car V4H 35 - renesas,tpu-r8a779h0 # R-Car V4M 36 - const: renesas,tpu 37 38 reg: 39 # Base address and length of each memory resource used by the PWM 40 # controller hardware module. 41 maxItems: 1 42 43 interrupts: 44 maxItems: 1 45 46 '#pwm-cells': 47 # should be 3. See pwm.yaml in this directory for a description of 48 # the cells format. The only third cell flag supported by this binding is 49 # PWM_POLARITY_INVERTED. 50 const: 3 51 52 clocks: 53 maxItems: 1 54 55 power-domains: 56 maxItems: 1 57 58 resets: 59 maxItems: 1 60 61required: 62 - compatible 63 - reg 64 - clocks 65 - power-domains 66 67allOf: 68 - $ref: pwm.yaml# 69 70 - if: 71 not: 72 properties: 73 compatible: 74 contains: 75 enum: 76 - renesas,tpu-r8a73a4 77 - renesas,tpu-r8a7740 78 then: 79 required: 80 - resets 81 82additionalProperties: false 83 84examples: 85 - | 86 #include <dt-bindings/clock/r8a7740-clock.h> 87 88 tpu: pwm@e6600000 { 89 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 90 reg = <0xe6600000 0x148>; 91 clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 92 power-domains = <&pd_a3sp>; 93 #pwm-cells = <3>; 94 }; 95