1*df77f773SConor Dooley# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*df77f773SConor Dooley 3*df77f773SConor Dooley%YAML 1.2 4*df77f773SConor Dooley--- 5*df77f773SConor Dooley$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml# 6*df77f773SConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 7*df77f773SConor Dooley 8*df77f773SConor Dooleytitle: Microchip IP corePWM controller bindings 9*df77f773SConor Dooley 10*df77f773SConor Dooleymaintainers: 11*df77f773SConor Dooley - Conor Dooley <conor.dooley@microchip.com> 12*df77f773SConor Dooley 13*df77f773SConor Dooleydescription: | 14*df77f773SConor Dooley corePWM is an 16 channel pulse width modulator FPGA IP 15*df77f773SConor Dooley 16*df77f773SConor Dooley https://www.microsemi.com/existing-parts/parts/152118 17*df77f773SConor Dooley 18*df77f773SConor DooleyallOf: 19*df77f773SConor Dooley - $ref: pwm.yaml# 20*df77f773SConor Dooley 21*df77f773SConor Dooleyproperties: 22*df77f773SConor Dooley compatible: 23*df77f773SConor Dooley items: 24*df77f773SConor Dooley - const: microchip,corepwm-rtl-v4 25*df77f773SConor Dooley 26*df77f773SConor Dooley reg: 27*df77f773SConor Dooley maxItems: 1 28*df77f773SConor Dooley 29*df77f773SConor Dooley clocks: 30*df77f773SConor Dooley maxItems: 1 31*df77f773SConor Dooley 32*df77f773SConor Dooley "#pwm-cells": 33*df77f773SConor Dooley const: 2 34*df77f773SConor Dooley 35*df77f773SConor Dooley microchip,sync-update-mask: 36*df77f773SConor Dooley description: | 37*df77f773SConor Dooley Depending on how the IP is instantiated, there are two modes of operation. 38*df77f773SConor Dooley In synchronous mode, all channels are updated at the beginning of the PWM period, 39*df77f773SConor Dooley and in asynchronous mode updates happen as the control registers are written. 40*df77f773SConor Dooley A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous 41*df77f773SConor Dooley mode is possible for each channel, and is set by the bitstream programmed to the 42*df77f773SConor Dooley FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that 43*df77f773SConor Dooley control the duty cycle for channel x have a second "shadow"/buffer reg synthesised. 44*df77f773SConor Dooley At runtime a bit wide register exposed to APB can be used to toggle on/off 45*df77f773SConor Dooley synchronised mode for all channels it has been synthesised for. 46*df77f773SConor Dooley Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents 47*df77f773SConor Dooley whether synchronous mode is possible for the PWM channel. 48*df77f773SConor Dooley 49*df77f773SConor Dooley $ref: /schemas/types.yaml#/definitions/uint32 50*df77f773SConor Dooley default: 0 51*df77f773SConor Dooley 52*df77f773SConor Dooley microchip,dac-mode-mask: 53*df77f773SConor Dooley description: | 54*df77f773SConor Dooley Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates 55*df77f773SConor Dooley a minimum period pulse train whose High/Low average is that of the chosen duty 56*df77f773SConor Dooley cycle. This "DAC" will have far better bandwidth and ripple performance than the 57*df77f773SConor Dooley standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP 58*df77f773SConor Dooley core, set at instantiation and by the bitstream programmed to the FPGA, determines 59*df77f773SConor Dooley whether a given channel operates in regular PWM or DAC mode. 60*df77f773SConor Dooley Each bit corresponds to a PWM channel & represents whether DAC mode is enabled 61*df77f773SConor Dooley for that channel. 62*df77f773SConor Dooley 63*df77f773SConor Dooley $ref: /schemas/types.yaml#/definitions/uint32 64*df77f773SConor Dooley default: 0 65*df77f773SConor Dooley 66*df77f773SConor Dooleyrequired: 67*df77f773SConor Dooley - compatible 68*df77f773SConor Dooley - reg 69*df77f773SConor Dooley - clocks 70*df77f773SConor Dooley 71*df77f773SConor DooleyadditionalProperties: false 72*df77f773SConor Dooley 73*df77f773SConor Dooleyexamples: 74*df77f773SConor Dooley - | 75*df77f773SConor Dooley pwm@41000000 { 76*df77f773SConor Dooley compatible = "microchip,corepwm-rtl-v4"; 77*df77f773SConor Dooley microchip,sync-update-mask = /bits/ 32 <0>; 78*df77f773SConor Dooley clocks = <&clkcfg 30>; 79*df77f773SConor Dooley reg = <0x41000000 0xF0>; 80*df77f773SConor Dooley #pwm-cells = <2>; 81*df77f773SConor Dooley }; 82