1*90cd430fSBinbin Zhou# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*90cd430fSBinbin Zhou%YAML 1.2 3*90cd430fSBinbin Zhou--- 4*90cd430fSBinbin Zhou$id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# 5*90cd430fSBinbin Zhou$schema: http://devicetree.org/meta-schemas/core.yaml# 6*90cd430fSBinbin Zhou 7*90cd430fSBinbin Zhoutitle: Loongson PWM Controller 8*90cd430fSBinbin Zhou 9*90cd430fSBinbin Zhoumaintainers: 10*90cd430fSBinbin Zhou - Binbin Zhou <zhoubinbin@loongson.cn> 11*90cd430fSBinbin Zhou 12*90cd430fSBinbin Zhoudescription: 13*90cd430fSBinbin Zhou The Loongson PWM has one pulse width output signal and one pulse input 14*90cd430fSBinbin Zhou signal to be measured. 15*90cd430fSBinbin Zhou It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. 16*90cd430fSBinbin Zhou 17*90cd430fSBinbin ZhouallOf: 18*90cd430fSBinbin Zhou - $ref: pwm.yaml# 19*90cd430fSBinbin Zhou 20*90cd430fSBinbin Zhouproperties: 21*90cd430fSBinbin Zhou compatible: 22*90cd430fSBinbin Zhou oneOf: 23*90cd430fSBinbin Zhou - const: loongson,ls7a-pwm 24*90cd430fSBinbin Zhou - items: 25*90cd430fSBinbin Zhou - enum: 26*90cd430fSBinbin Zhou - loongson,ls2k0500-pwm 27*90cd430fSBinbin Zhou - loongson,ls2k1000-pwm 28*90cd430fSBinbin Zhou - loongson,ls2k2000-pwm 29*90cd430fSBinbin Zhou - const: loongson,ls7a-pwm 30*90cd430fSBinbin Zhou 31*90cd430fSBinbin Zhou reg: 32*90cd430fSBinbin Zhou maxItems: 1 33*90cd430fSBinbin Zhou 34*90cd430fSBinbin Zhou interrupts: 35*90cd430fSBinbin Zhou maxItems: 1 36*90cd430fSBinbin Zhou 37*90cd430fSBinbin Zhou clocks: 38*90cd430fSBinbin Zhou maxItems: 1 39*90cd430fSBinbin Zhou 40*90cd430fSBinbin Zhou '#pwm-cells': 41*90cd430fSBinbin Zhou description: 42*90cd430fSBinbin Zhou The first cell must have a value of 0, which specifies the PWM output signal; 43*90cd430fSBinbin Zhou The second cell is the period in nanoseconds; 44*90cd430fSBinbin Zhou The third cell flag supported by this binding is PWM_POLARITY_INVERTED. 45*90cd430fSBinbin Zhou const: 3 46*90cd430fSBinbin Zhou 47*90cd430fSBinbin Zhourequired: 48*90cd430fSBinbin Zhou - compatible 49*90cd430fSBinbin Zhou - reg 50*90cd430fSBinbin Zhou - interrupts 51*90cd430fSBinbin Zhou - clocks 52*90cd430fSBinbin Zhou 53*90cd430fSBinbin ZhouadditionalProperties: false 54*90cd430fSBinbin Zhou 55*90cd430fSBinbin Zhouexamples: 56*90cd430fSBinbin Zhou - | 57*90cd430fSBinbin Zhou #include <dt-bindings/interrupt-controller/irq.h> 58*90cd430fSBinbin Zhou #include <dt-bindings/clock/loongson,ls2k-clk.h> 59*90cd430fSBinbin Zhou 60*90cd430fSBinbin Zhou pwm@1fe22000 { 61*90cd430fSBinbin Zhou compatible = "loongson,ls2k1000-pwm", "loongson,ls7a-pwm"; 62*90cd430fSBinbin Zhou reg = <0x1fe22000 0x10>; 63*90cd430fSBinbin Zhou interrupt-parent = <&liointc0>; 64*90cd430fSBinbin Zhou interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 65*90cd430fSBinbin Zhou clocks = <&clk LOONGSON2_APB_CLK>; 66*90cd430fSBinbin Zhou #pwm-cells = <3>; 67*90cd430fSBinbin Zhou }; 68