134df9f69SGrant LikelyMPC5200 Device Tree Bindings 234df9f69SGrant Likely---------------------------- 334df9f69SGrant Likely 434df9f69SGrant Likely(c) 2006-2009 Secret Lab Technologies Ltd 534df9f69SGrant LikelyGrant Likely <grant.likely@secretlab.ca> 634df9f69SGrant Likely 734df9f69SGrant LikelyNaming conventions 834df9f69SGrant Likely------------------ 934df9f69SGrant LikelyFor mpc5200 on-chip devices, the format for each compatible value is 1034df9f69SGrant Likely<chip>-<device>[-<mode>]. The OS should be able to match a device driver 1134df9f69SGrant Likelyto the device based solely on the compatible value. If two drivers 1234df9f69SGrant Likelymatch on the compatible list; the 'most compatible' driver should be 1334df9f69SGrant Likelyselected. 1434df9f69SGrant Likely 1534df9f69SGrant LikelyThe split between the MPC5200 and the MPC5200B leaves a bit of a 1634df9f69SGrant Likelyconundrum. How should the compatible property be set up to provide 1734df9f69SGrant Likelymaximum compatibility information; but still accurately describe the 1834df9f69SGrant Likelychip? For the MPC5200; the answer is easy. Most of the SoC devices 1934df9f69SGrant Likelyoriginally appeared on the MPC5200. Since they didn't exist anywhere 2034df9f69SGrant Likelyelse; the 5200 compatible properties will contain only one item; 2134df9f69SGrant Likely"fsl,mpc5200-<device>". 2234df9f69SGrant Likely 2334df9f69SGrant LikelyThe 5200B is almost the same as the 5200, but not quite. It fixes 2434df9f69SGrant Likelysilicon bugs and it adds a small number of enhancements. Most of the 2534df9f69SGrant Likelydevices either provide exactly the same interface as on the 5200. A few 2634df9f69SGrant Likelydevices have extra functions but still have a backwards compatible mode. 2734df9f69SGrant LikelyTo express this information as completely as possible, 5200B device trees 2834df9f69SGrant Likelyshould have two items in the compatible list: 2934df9f69SGrant Likely compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>"; 3034df9f69SGrant Likely 3134df9f69SGrant LikelyIt is *strongly* recommended that 5200B device trees follow this convention 3234df9f69SGrant Likely(instead of only listing the base mpc5200 item). 3334df9f69SGrant Likely 3434df9f69SGrant Likelyie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec"; 3534df9f69SGrant Likely ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec"; 3634df9f69SGrant Likely 3734df9f69SGrant LikelyModal devices, like PSCs, also append the configured function to the 3834df9f69SGrant Likelyend of the compatible field. ie. A PSC in i2s mode would specify 3934df9f69SGrant Likely"fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to 4034df9f69SGrant Likelyavoid naming conflicts with non-psc devices providing the same 4134df9f69SGrant Likelyfunction. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe 4234df9f69SGrant Likelythe mpc5200 simple spi device and a PSC spi mode respectively. 4334df9f69SGrant Likely 4434df9f69SGrant LikelyAt the time of writing, exact chip may be either 'fsl,mpc5200' or 4534df9f69SGrant Likely'fsl,mpc5200b'. 4634df9f69SGrant Likely 4734df9f69SGrant LikelyThe soc node 4834df9f69SGrant Likely------------ 4934df9f69SGrant LikelyThis node describes the on chip SOC peripherals. Every mpc5200 based 5034df9f69SGrant Likelyboard will have this node, and as such there is a common naming 5134df9f69SGrant Likelyconvention for SOC devices. 5234df9f69SGrant Likely 5334df9f69SGrant LikelyRequired properties: 5434df9f69SGrant Likelyname description 5534df9f69SGrant Likely---- ----------- 5634df9f69SGrant Likelyranges Memory range of the internal memory mapped registers. 5734df9f69SGrant Likely Should be <0 [baseaddr] 0xc000> 5834df9f69SGrant Likelyreg Should be <[baseaddr] 0x100> 5934df9f69SGrant Likelycompatible mpc5200: "fsl,mpc5200-immr" 6034df9f69SGrant Likely mpc5200b: "fsl,mpc5200b-immr" 6134df9f69SGrant Likelysystem-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI 6234df9f69SGrant Likely clocks are derived from the fsystem clock. 6334df9f69SGrant Likelybus-frequency IPB bus frequency in Hz. Clock rate 6434df9f69SGrant Likely used by most of the soc devices. 6534df9f69SGrant Likely 6634df9f69SGrant Likelysoc child nodes 6734df9f69SGrant Likely--------------- 6834df9f69SGrant LikelyAny on chip SOC devices available to Linux must appear as soc5200 child nodes. 6934df9f69SGrant Likely 7034df9f69SGrant LikelyNote: The tables below show the value for the mpc5200. A mpc5200b device 7134df9f69SGrant Likelytree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form. 7234df9f69SGrant Likely 7334df9f69SGrant LikelyRequired soc5200 child nodes: 7434df9f69SGrant Likelyname compatible Description 7534df9f69SGrant Likely---- ---------- ----------- 7634df9f69SGrant Likelycdm@<addr> fsl,mpc5200-cdm Clock Distribution 7734df9f69SGrant Likelyinterrupt-controller@<addr> fsl,mpc5200-pic need an interrupt 7834df9f69SGrant Likely controller to boot 7934df9f69SGrant Likelybestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller 8034df9f69SGrant Likely 8134df9f69SGrant LikelyRecommended soc5200 child nodes; populate as needed for your board 8234df9f69SGrant Likelyname compatible Description 8334df9f69SGrant Likely---- ---------- ----------- 8434df9f69SGrant Likelytimer@<addr> fsl,mpc5200-gpt General purpose timers 8534df9f69SGrant Likelygpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller 8634df9f69SGrant Likelygpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller 8734df9f69SGrant Likelyrtc@<addr> fsl,mpc5200-rtc Real time clock 8834df9f69SGrant Likelymscan@<addr> fsl,mpc5200-mscan CAN bus controller 8934df9f69SGrant Likelypci@<addr> fsl,mpc5200-pci PCI bridge 9034df9f69SGrant Likelyserial@<addr> fsl,mpc5200-psc-uart PSC in serial mode 9134df9f69SGrant Likelyi2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode 9234df9f69SGrant Likelyac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode 9334df9f69SGrant Likelyspi@<addr> fsl,mpc5200-psc-spi PSC in spi mode 9434df9f69SGrant Likelyirda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode 9534df9f69SGrant Likelyspi@<addr> fsl,mpc5200-spi MPC5200 spi device 9634df9f69SGrant Likelyethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device 9734df9f69SGrant Likelyata@<addr> fsl,mpc5200-ata IDE ATA interface 9834df9f69SGrant Likelyi2c@<addr> fsl,mpc5200-i2c I2C controller 9934df9f69SGrant Likelyusb@<addr> fsl,mpc5200-ohci,ohci-be USB controller 10034df9f69SGrant Likelyxlb@<addr> fsl,mpc5200-xlb XLB arbitrator 10134df9f69SGrant Likely 10234df9f69SGrant Likelyfsl,mpc5200-gpt nodes 10334df9f69SGrant Likely--------------------- 10434df9f69SGrant LikelyOn the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board 10534df9f69SGrant Likelydesign supports the internal wdt, then the device node for GPT0 should 10613b600b5SAlbrecht Dreßinclude the empty property 'fsl,has-wdt'. Note that this does not activate 10713b600b5SAlbrecht Dreßthe watchdog. The timer will function as a GPT if the timer api is used, and 10813b600b5SAlbrecht Dreßit will function as watchdog if the watchdog device is used. The watchdog 10913b600b5SAlbrecht Dreßmode has priority over the gpt mode, i.e. if the watchdog is activated, any 11013b600b5SAlbrecht Dreßgpt api call to this timer will fail with -EBUSY. 11113b600b5SAlbrecht Dreß 11213b600b5SAlbrecht DreßIf you add the property 11313b600b5SAlbrecht Dreß fsl,wdt-on-boot = <n>; 11413b600b5SAlbrecht DreßGPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it. 11513b600b5SAlbrecht DreßIf n>0, the watchdog is started with a timeout of n seconds. If n=0, the 11613b600b5SAlbrecht Dreßconfiguration of the watchdog is not touched. This is useful in two cases: 11713b600b5SAlbrecht Dreß- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later; 11813b600b5SAlbrecht Dreß- do not touch a configuration assigned by the boot loader which supervises 11913b600b5SAlbrecht Dreß the boot process itself. 12013b600b5SAlbrecht Dreß 12113b600b5SAlbrecht DreßThe watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option. 12234df9f69SGrant Likely 12334df9f69SGrant LikelyAn mpc5200-gpt can be used as a single line GPIO controller. To do so, 12434df9f69SGrant Likelyadd the following properties to the gpt node: 12534df9f69SGrant Likely gpio-controller; 12634df9f69SGrant Likely #gpio-cells = <2>; 12734df9f69SGrant LikelyWhen referencing the GPIO line from another node, the first cell must always 12834df9f69SGrant Likelybe zero and the second cell represents the gpio flags and described in the 12934df9f69SGrant Likelygpio device tree binding. 13034df9f69SGrant Likely 13134df9f69SGrant LikelyAn mpc5200-gpt can be used as a single line edge sensitive interrupt 13234df9f69SGrant Likelycontroller. To do so, add the following properties to the gpt node: 13334df9f69SGrant Likely interrupt-controller; 13434df9f69SGrant Likely #interrupt-cells = <1>; 13534df9f69SGrant LikelyWhen referencing the IRQ line from another node, the cell represents the 13634df9f69SGrant Likelysense mode; 1 for edge rising, 2 for edge falling. 13734df9f69SGrant Likely 13834df9f69SGrant Likelyfsl,mpc5200-psc nodes 13934df9f69SGrant Likely--------------------- 14034df9f69SGrant LikelyThe PSCs should include a cell-index which is the index of the PSC in 14134df9f69SGrant Likelyhardware. cell-index is used to determine which shared SoC registers to 14234df9f69SGrant Likelyuse when setting up PSC clocking. cell-index number starts at '0'. ie: 14334df9f69SGrant Likely PSC1 has 'cell-index = <0>' 14434df9f69SGrant Likely PSC4 has 'cell-index = <3>' 14534df9f69SGrant Likely 14634df9f69SGrant LikelyPSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in 14734df9f69SGrant Likelyi2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the 14834df9f69SGrant Likelycompatible field. 14934df9f69SGrant Likely 15034df9f69SGrant Likely 15134df9f69SGrant Likelyfsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes 15234df9f69SGrant Likely------------------------------------------------ 15334df9f69SGrant LikelyEach GPIO controller node should have the empty property gpio-controller and 15434df9f69SGrant Likely#gpio-cells set to 2. First cell is the GPIO number which is interpreted 15534df9f69SGrant Likelyaccording to the bit numbers in the GPIO control registers. The second cell 15634df9f69SGrant Likelyis for flags which is currently unused. 15734df9f69SGrant Likely 15834df9f69SGrant Likelyfsl,mpc5200-fec nodes 15934df9f69SGrant Likely--------------------- 16034df9f69SGrant LikelyThe FEC node can specify one of the following properties to configure 16134df9f69SGrant Likelythe MII link: 16234df9f69SGrant Likely- fsl,7-wire-mode - An empty property that specifies the link uses 7-wire 16334df9f69SGrant Likely mode instead of MII 16434df9f69SGrant Likely- current-speed - Specifies that the MII should be configured for a fixed 16534df9f69SGrant Likely speed. This property should contain two cells. The 16634df9f69SGrant Likely first cell specifies the speed in Mbps and the second 16734df9f69SGrant Likely should be '0' for half duplex and '1' for full duplex 16834df9f69SGrant Likely- phy-handle - Contains a phandle to an Ethernet PHY. 16934df9f69SGrant Likely 17034df9f69SGrant LikelyInterrupt controller (fsl,mpc5200-pic) node 17134df9f69SGrant Likely------------------------------------------- 17234df9f69SGrant LikelyThe mpc5200 pic binding splits hardware IRQ numbers into two levels. The 17334df9f69SGrant Likelysplit reflects the layout of the PIC hardware itself, which groups 17434df9f69SGrant Likelyinterrupts into one of three groups; CRIT, MAIN or PERP. Also, the 175*be55492eSRandy DunlapBestcomm dma engine has its own set of interrupt sources which are 17634df9f69SGrant Likelycascaded off of peripheral interrupt 0, which the driver interprets as a 17734df9f69SGrant Likelyfourth group, SDMA. 17834df9f69SGrant Likely 17934df9f69SGrant LikelyThe interrupts property for device nodes using the mpc5200 pic consists 18034df9f69SGrant Likelyof three cells; <L1 L2 level> 18134df9f69SGrant Likely 18234df9f69SGrant Likely L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3] 18334df9f69SGrant Likely L2 := interrupt number; directly mapped from the value in the 18434df9f69SGrant Likely "ICTL PerStat, MainStat, CritStat Encoded Register" 18534df9f69SGrant Likely level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3] 18634df9f69SGrant Likely 18734df9f69SGrant LikelyFor external IRQs, use the following interrupt property values (how to 18834df9f69SGrant Likelyspecify external interrupts is a frequently asked question): 18934df9f69SGrant LikelyExternal interrupts: 19034df9f69SGrant Likely external irq0: interrupts = <0 0 n>; 19134df9f69SGrant Likely external irq1: interrupts = <1 1 n>; 19234df9f69SGrant Likely external irq2: interrupts = <1 2 n>; 19334df9f69SGrant Likely external irq3: interrupts = <1 3 n>; 19434df9f69SGrant Likely'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low) 19534df9f69SGrant Likely 196afa17a50SWolfram Sangfsl,mpc5200-mscan nodes 197afa17a50SWolfram Sang----------------------- 198cea47072SMarc Kleine-BuddeSee file Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt 199