xref: /linux/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml (revision a23e1966932464e1c5226cb9ac4ce1d5fc10ba22)
1ae07a9a8SChanghuang Liang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2ae07a9a8SChanghuang Liang%YAML 1.2
3ae07a9a8SChanghuang Liang---
4ae07a9a8SChanghuang Liang$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5ae07a9a8SChanghuang Liang$schema: http://devicetree.org/meta-schemas/core.yaml#
6ae07a9a8SChanghuang Liang
7ae07a9a8SChanghuang Liangtitle: StarFive SoC JH7110 MIPI D-PHY Rx Controller
8ae07a9a8SChanghuang Liang
9ae07a9a8SChanghuang Liangmaintainers:
10ae07a9a8SChanghuang Liang  - Jack Zhu <jack.zhu@starfivetech.com>
11ae07a9a8SChanghuang Liang  - Changhuang Liang <changhuang.liang@starfivetech.com>
12ae07a9a8SChanghuang Liang
13ae07a9a8SChanghuang Liangdescription:
14ae07a9a8SChanghuang Liang  StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
15ae07a9a8SChanghuang Liang  transfer CSI camera data.
16ae07a9a8SChanghuang Liang
17ae07a9a8SChanghuang Liangproperties:
18ae07a9a8SChanghuang Liang  compatible:
19ae07a9a8SChanghuang Liang    const: starfive,jh7110-dphy-rx
20ae07a9a8SChanghuang Liang
21ae07a9a8SChanghuang Liang  reg:
22ae07a9a8SChanghuang Liang    maxItems: 1
23ae07a9a8SChanghuang Liang
24ae07a9a8SChanghuang Liang  clocks:
25ae07a9a8SChanghuang Liang    items:
26ae07a9a8SChanghuang Liang      - description: config clock
27ae07a9a8SChanghuang Liang      - description: reference clock
28ae07a9a8SChanghuang Liang      - description: escape mode transmit clock
29ae07a9a8SChanghuang Liang
30ae07a9a8SChanghuang Liang  clock-names:
31ae07a9a8SChanghuang Liang    items:
32ae07a9a8SChanghuang Liang      - const: cfg
33ae07a9a8SChanghuang Liang      - const: ref
34ae07a9a8SChanghuang Liang      - const: tx
35ae07a9a8SChanghuang Liang
36ae07a9a8SChanghuang Liang  resets:
37ae07a9a8SChanghuang Liang    items:
38ae07a9a8SChanghuang Liang      - description: DPHY_HW reset
39ae07a9a8SChanghuang Liang      - description: DPHY_B09_ALWAYS_ON reset
40ae07a9a8SChanghuang Liang
41ae07a9a8SChanghuang Liang  power-domains:
42ae07a9a8SChanghuang Liang    maxItems: 1
43ae07a9a8SChanghuang Liang
44ae07a9a8SChanghuang Liang  "#phy-cells":
45ae07a9a8SChanghuang Liang    const: 0
46ae07a9a8SChanghuang Liang
47ae07a9a8SChanghuang Liangrequired:
48ae07a9a8SChanghuang Liang  - compatible
49ae07a9a8SChanghuang Liang  - reg
50ae07a9a8SChanghuang Liang  - clocks
51ae07a9a8SChanghuang Liang  - clock-names
52ae07a9a8SChanghuang Liang  - resets
53ae07a9a8SChanghuang Liang  - power-domains
54ae07a9a8SChanghuang Liang  - "#phy-cells"
55ae07a9a8SChanghuang Liang
56ae07a9a8SChanghuang LiangadditionalProperties: false
57ae07a9a8SChanghuang Liang
58ae07a9a8SChanghuang Liangexamples:
59ae07a9a8SChanghuang Liang  - |
60ae07a9a8SChanghuang Liang    phy@19820000 {
61ae07a9a8SChanghuang Liang      compatible = "starfive,jh7110-dphy-rx";
62ae07a9a8SChanghuang Liang      reg = <0x19820000 0x10000>;
63ae07a9a8SChanghuang Liang      clocks = <&ispcrg 3>,
64ae07a9a8SChanghuang Liang               <&ispcrg 4>,
65ae07a9a8SChanghuang Liang               <&ispcrg 5>;
66ae07a9a8SChanghuang Liang      clock-names = "cfg", "ref", "tx";
67ae07a9a8SChanghuang Liang      resets = <&ispcrg 2>,
68ae07a9a8SChanghuang Liang               <&ispcrg 3>;
69ae07a9a8SChanghuang Liang      power-domains = <&aon_syscon 1>;
70ae07a9a8SChanghuang Liang      #phy-cells = <0>;
71ae07a9a8SChanghuang Liang    };
72