xref: /linux/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml (revision 6315d93541f8a5f77c5ef5c4f25233e66d189603) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung SoC series UFS PHY
8
9maintainers:
10  - Alim Akhtar <alim.akhtar@samsung.com>
11
12properties:
13  "#phy-cells":
14    const: 0
15
16  compatible:
17    enum:
18      - google,gs101-ufs-phy
19      - samsung,exynos7-ufs-phy
20      - samsung,exynosautov9-ufs-phy
21      - samsung,exynosautov920-ufs-phy
22      - tesla,fsd-ufs-phy
23
24  reg:
25    maxItems: 1
26
27  reg-names:
28    items:
29      - const: phy-pma
30
31  clocks:
32    minItems: 1
33    maxItems: 4
34
35  clock-names:
36    minItems: 1
37    maxItems: 4
38
39  samsung,pmu-syscon:
40    $ref: /schemas/types.yaml#/definitions/phandle-array
41    maxItems: 1
42    items:
43      minItems: 1
44      items:
45        - description: phandle for PMU system controller interface, used to
46                       control pmu registers bits for ufs m-phy
47        - description: offset of the pmu control register
48    description:
49      It can be phandle/offset pair. The second cell which can represent an
50      offset is optional.
51
52required:
53  - "#phy-cells"
54  - compatible
55  - reg
56  - reg-names
57  - clocks
58  - clock-names
59  - samsung,pmu-syscon
60
61allOf:
62  - if:
63      properties:
64        compatible:
65          contains:
66            const: samsung,exynos7-ufs-phy
67
68    then:
69      properties:
70        clocks:
71          items:
72            - description: PLL reference clock
73            - description: symbol clock for input symbol (rx0-ch0 symbol clock)
74            - description: symbol clock for input symbol (rx1-ch1 symbol clock)
75            - description: symbol clock for output symbol (tx0 symbol clock)
76
77        clock-names:
78          items:
79            - const: ref_clk
80            - const: rx1_symbol_clk
81            - const: rx0_symbol_clk
82            - const: tx0_symbol_clk
83
84    else:
85      properties:
86        clocks:
87          items:
88            - description: PLL reference clock
89
90        clock-names:
91          items:
92            - const: ref_clk
93
94additionalProperties: false
95
96examples:
97  - |
98    #include <dt-bindings/clock/exynos7-clk.h>
99
100    ufs_phy: ufs-phy@15571800 {
101        compatible = "samsung,exynos7-ufs-phy";
102        reg = <0x15571800 0x240>;
103        reg-names = "phy-pma";
104        samsung,pmu-syscon = <&pmu_system_controller>;
105        #phy-cells = <0>;
106        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
107                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
108                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
109                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
110        clock-names = "ref_clk", "rx1_symbol_clk",
111                      "rx0_symbol_clk", "tx0_symbol_clk";
112
113    };
114...
115