1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PHY controller (UFS, SC8280XP) 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 The QMP PHY controller supports physical layer functionality for a number of 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - enum: 21 - qcom,qcs615-qmp-ufs-phy 22 - const: qcom,sm6115-qmp-ufs-phy 23 - items: 24 - enum: 25 - qcom,qcs8300-qmp-ufs-phy 26 - const: qcom,sa8775p-qmp-ufs-phy 27 - enum: 28 - qcom,msm8996-qmp-ufs-phy 29 - qcom,msm8998-qmp-ufs-phy 30 - qcom,sa8775p-qmp-ufs-phy 31 - qcom,sc7180-qmp-ufs-phy 32 - qcom,sc7280-qmp-ufs-phy 33 - qcom,sc8180x-qmp-ufs-phy 34 - qcom,sc8280xp-qmp-ufs-phy 35 - qcom,sdm845-qmp-ufs-phy 36 - qcom,sm6115-qmp-ufs-phy 37 - qcom,sm6125-qmp-ufs-phy 38 - qcom,sm6350-qmp-ufs-phy 39 - qcom,sm7150-qmp-ufs-phy 40 - qcom,sm8150-qmp-ufs-phy 41 - qcom,sm8250-qmp-ufs-phy 42 - qcom,sm8350-qmp-ufs-phy 43 - qcom,sm8450-qmp-ufs-phy 44 - qcom,sm8475-qmp-ufs-phy 45 - qcom,sm8550-qmp-ufs-phy 46 - qcom,sm8650-qmp-ufs-phy 47 - qcom,sm8750-qmp-ufs-phy 48 49 reg: 50 maxItems: 1 51 52 clocks: 53 minItems: 2 54 maxItems: 3 55 56 clock-names: 57 minItems: 2 58 maxItems: 3 59 60 power-domains: 61 maxItems: 1 62 63 resets: 64 maxItems: 1 65 66 reset-names: 67 items: 68 - const: ufsphy 69 70 vdda-phy-supply: true 71 72 vdda-pll-supply: true 73 74 "#clock-cells": 75 const: 1 76 77 "#phy-cells": 78 const: 0 79 80required: 81 - compatible 82 - reg 83 - clocks 84 - clock-names 85 - resets 86 - reset-names 87 - vdda-phy-supply 88 - vdda-pll-supply 89 - "#phy-cells" 90 91allOf: 92 - if: 93 properties: 94 compatible: 95 contains: 96 enum: 97 - qcom,msm8998-qmp-ufs-phy 98 - qcom,sa8775p-qmp-ufs-phy 99 - qcom,sc7180-qmp-ufs-phy 100 - qcom,sc7280-qmp-ufs-phy 101 - qcom,sc8180x-qmp-ufs-phy 102 - qcom,sc8280xp-qmp-ufs-phy 103 - qcom,sdm845-qmp-ufs-phy 104 - qcom,sm6115-qmp-ufs-phy 105 - qcom,sm6125-qmp-ufs-phy 106 - qcom,sm6350-qmp-ufs-phy 107 - qcom,sm7150-qmp-ufs-phy 108 - qcom,sm8150-qmp-ufs-phy 109 - qcom,sm8250-qmp-ufs-phy 110 - qcom,sm8350-qmp-ufs-phy 111 - qcom,sm8450-qmp-ufs-phy 112 - qcom,sm8475-qmp-ufs-phy 113 - qcom,sm8550-qmp-ufs-phy 114 - qcom,sm8650-qmp-ufs-phy 115 - qcom,sm8750-qmp-ufs-phy 116 then: 117 properties: 118 clocks: 119 minItems: 3 120 maxItems: 3 121 clock-names: 122 items: 123 - const: ref 124 - const: ref_aux 125 - const: qref 126 127 - if: 128 properties: 129 compatible: 130 contains: 131 enum: 132 - qcom,msm8996-qmp-ufs-phy 133 then: 134 properties: 135 clocks: 136 minItems: 2 137 maxItems: 2 138 clock-names: 139 items: 140 - const: ref 141 - const: qref 142 143 - if: 144 properties: 145 compatible: 146 contains: 147 enum: 148 - qcom,msm8996-qmp-ufs-phy 149 - qcom,msm8998-qmp-ufs-phy 150 then: 151 properties: 152 power-domains: 153 false 154 else: 155 required: 156 - power-domains 157 158additionalProperties: false 159 160examples: 161 - | 162 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 163 #include <dt-bindings/clock/qcom,rpmh.h> 164 165 ufs_mem_phy: phy@1d87000 { 166 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 167 reg = <0x01d87000 0x1000>; 168 169 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 170 <&gcc GCC_UFS_REF_CLKREF_CLK>; 171 172 clock-names = "ref", "ref_aux", "qref"; 173 174 power-domains = <&gcc UFS_PHY_GDSC>; 175 176 resets = <&ufs_mem_hc 0>; 177 reset-names = "ufsphy"; 178 179 vdda-phy-supply = <&vreg_l6b>; 180 vdda-pll-supply = <&vreg_l3b>; 181 182 #phy-cells = <0>; 183 }; 184