xref: /linux/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml (revision e4dffb674cfd489a37314b606f6f1a0a6dc3e610)
142694f9fSMauro Carvalho Chehab# SPDX-License-Identifier: GPL-2.0
242694f9fSMauro Carvalho Chehab%YAML 1.2
342694f9fSMauro Carvalho Chehab---
442694f9fSMauro Carvalho Chehab$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
542694f9fSMauro Carvalho Chehab$schema: http://devicetree.org/meta-schemas/core.yaml#
642694f9fSMauro Carvalho Chehab
742694f9fSMauro Carvalho Chehabtitle: Synopsys DesignWare PCIe interface
842694f9fSMauro Carvalho Chehab
942694f9fSMauro Carvalho Chehabmaintainers:
1042694f9fSMauro Carvalho Chehab  - Jingoo Han <jingoohan1@gmail.com>
1142694f9fSMauro Carvalho Chehab  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
1242694f9fSMauro Carvalho Chehab
1342694f9fSMauro Carvalho Chehabdescription: |
1442694f9fSMauro Carvalho Chehab  Synopsys DesignWare PCIe host controller
1542694f9fSMauro Carvalho Chehab
1642694f9fSMauro Carvalho ChehaballOf:
1742694f9fSMauro Carvalho Chehab  - $ref: /schemas/pci/pci-bus.yaml#
1842694f9fSMauro Carvalho Chehab
1942694f9fSMauro Carvalho Chehabproperties:
2042694f9fSMauro Carvalho Chehab  compatible:
2142694f9fSMauro Carvalho Chehab    anyOf:
2242694f9fSMauro Carvalho Chehab      - {}
2342694f9fSMauro Carvalho Chehab      - const: snps,dw-pcie
2442694f9fSMauro Carvalho Chehab
2542694f9fSMauro Carvalho Chehab  reg:
2642694f9fSMauro Carvalho Chehab    description: |
2742694f9fSMauro Carvalho Chehab      It should contain Data Bus Interface (dbi) and config registers for all
2842694f9fSMauro Carvalho Chehab      versions.
2942694f9fSMauro Carvalho Chehab      For designware core version >= 4.80, it may contain ATU address space.
3042694f9fSMauro Carvalho Chehab    minItems: 2
3142694f9fSMauro Carvalho Chehab    maxItems: 5
3242694f9fSMauro Carvalho Chehab
3342694f9fSMauro Carvalho Chehab  reg-names:
3442694f9fSMauro Carvalho Chehab    minItems: 2
3542694f9fSMauro Carvalho Chehab    maxItems: 5
3642694f9fSMauro Carvalho Chehab    items:
37*e4dffb67SVidya Sagar      enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
38*e4dffb67SVidya Sagar              parf, cfg, link, ulreg, smu, mpu, apb, phy ]
3942694f9fSMauro Carvalho Chehab
4042694f9fSMauro Carvalho Chehab  num-lanes:
4142694f9fSMauro Carvalho Chehab    description: |
4242694f9fSMauro Carvalho Chehab      number of lanes to use (this property should be specified unless
4342694f9fSMauro Carvalho Chehab      the link is brought already up in firmware)
4442694f9fSMauro Carvalho Chehab    maximum: 16
4542694f9fSMauro Carvalho Chehab
4642694f9fSMauro Carvalho Chehab  reset-gpio:
4742694f9fSMauro Carvalho Chehab    description: GPIO pin number of PERST# signal
4842694f9fSMauro Carvalho Chehab    maxItems: 1
4942694f9fSMauro Carvalho Chehab    deprecated: true
5042694f9fSMauro Carvalho Chehab
5142694f9fSMauro Carvalho Chehab  reset-gpios:
5242694f9fSMauro Carvalho Chehab    description: GPIO controlled connection to PERST# signal
5342694f9fSMauro Carvalho Chehab    maxItems: 1
5442694f9fSMauro Carvalho Chehab
5542694f9fSMauro Carvalho Chehab  interrupts: true
5642694f9fSMauro Carvalho Chehab
5742694f9fSMauro Carvalho Chehab  interrupt-names: true
5842694f9fSMauro Carvalho Chehab
5942694f9fSMauro Carvalho Chehab  clocks: true
6042694f9fSMauro Carvalho Chehab
6142694f9fSMauro Carvalho Chehab  snps,enable-cdm-check:
6242694f9fSMauro Carvalho Chehab    type: boolean
6342694f9fSMauro Carvalho Chehab    description: |
6442694f9fSMauro Carvalho Chehab      This is a boolean property and if present enables
6542694f9fSMauro Carvalho Chehab      automatic checking of CDM (Configuration Dependent Module) registers
6642694f9fSMauro Carvalho Chehab      for data corruption. CDM registers include standard PCIe configuration
6742694f9fSMauro Carvalho Chehab      space registers, Port Logic registers, DMA and iATU (internal Address
6842694f9fSMauro Carvalho Chehab      Translation Unit) registers.
6942694f9fSMauro Carvalho Chehab
7042694f9fSMauro Carvalho Chehab  num-viewport:
714e71ed98SRob Herring    $ref: /schemas/types.yaml#/definitions/uint32
724e71ed98SRob Herring    maximum: 256
7342694f9fSMauro Carvalho Chehab    description: |
7442694f9fSMauro Carvalho Chehab      number of view ports configured in hardware. If a platform
7542694f9fSMauro Carvalho Chehab      does not specify it, the driver autodetects it.
7642694f9fSMauro Carvalho Chehab    deprecated: true
7742694f9fSMauro Carvalho Chehab
78b92225b0SRob HerringadditionalProperties: true
7942694f9fSMauro Carvalho Chehab
8042694f9fSMauro Carvalho Chehabrequired:
8142694f9fSMauro Carvalho Chehab  - reg
8242694f9fSMauro Carvalho Chehab  - reg-names
8342694f9fSMauro Carvalho Chehab  - compatible
8442694f9fSMauro Carvalho Chehab
8542694f9fSMauro Carvalho Chehabexamples:
8642694f9fSMauro Carvalho Chehab  - |
8742694f9fSMauro Carvalho Chehab    bus {
8842694f9fSMauro Carvalho Chehab      #address-cells = <1>;
8942694f9fSMauro Carvalho Chehab      #size-cells = <1>;
9042694f9fSMauro Carvalho Chehab      pcie@dfc00000 {
9142694f9fSMauro Carvalho Chehab        device_type = "pci";
9242694f9fSMauro Carvalho Chehab        compatible = "snps,dw-pcie";
9342694f9fSMauro Carvalho Chehab        reg = <0xdfc00000 0x0001000>, /* IP registers */
9442694f9fSMauro Carvalho Chehab              <0xd0000000 0x0002000>; /* Configuration space */
9542694f9fSMauro Carvalho Chehab        reg-names = "dbi", "config";
9642694f9fSMauro Carvalho Chehab        #address-cells = <3>;
9742694f9fSMauro Carvalho Chehab        #size-cells = <2>;
9842694f9fSMauro Carvalho Chehab        ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
9942694f9fSMauro Carvalho Chehab                 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
10042694f9fSMauro Carvalho Chehab        interrupts = <25>, <24>;
10142694f9fSMauro Carvalho Chehab        #interrupt-cells = <1>;
10242694f9fSMauro Carvalho Chehab        num-lanes = <1>;
10342694f9fSMauro Carvalho Chehab      };
10442694f9fSMauro Carvalho Chehab    };
105