1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie-sc7280.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SC7280 PCI Express Root Complex 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 12 13description: 14 Qualcomm SC7280 SoC PCIe root complex controller is based on the Synopsys 15 DesignWare PCIe IP. 16 17properties: 18 compatible: 19 const: qcom,pcie-sc7280 20 21 reg: 22 minItems: 5 23 maxItems: 6 24 25 reg-names: 26 minItems: 5 27 items: 28 - const: parf # Qualcomm specific registers 29 - const: dbi # DesignWare PCIe registers 30 - const: elbi # External local bus interface registers 31 - const: atu # ATU address space 32 - const: config # PCIe configuration space 33 - const: mhi # MHI registers 34 35 clocks: 36 minItems: 13 37 maxItems: 13 38 39 clock-names: 40 items: 41 - const: pipe # PIPE clock 42 - const: pipe_mux # PIPE MUX 43 - const: phy_pipe # PIPE output clock 44 - const: ref # REFERENCE clock 45 - const: aux # Auxiliary clock 46 - const: cfg # Configuration clock 47 - const: bus_master # Master AXI clock 48 - const: bus_slave # Slave AXI clock 49 - const: slave_q2a # Slave Q2A clock 50 - const: tbu # PCIe TBU clock 51 - const: ddrss_sf_tbu # PCIe SF TBU clock 52 - const: aggre0 # Aggre NoC PCIe CENTER SF AXI clock 53 - const: aggre1 # Aggre NoC PCIe1 AXI clock 54 55 interrupts: 56 minItems: 8 57 maxItems: 9 58 59 interrupt-names: 60 minItems: 8 61 items: 62 - const: msi0 63 - const: msi1 64 - const: msi2 65 - const: msi3 66 - const: msi4 67 - const: msi5 68 - const: msi6 69 - const: msi7 70 - const: global 71 72 resets: 73 maxItems: 1 74 75 reset-names: 76 items: 77 - const: pci 78 79allOf: 80 - $ref: qcom,pcie-common.yaml# 81 82unevaluatedProperties: false 83 84examples: 85 - | 86 #include <dt-bindings/clock/qcom,gcc-sc7280.h> 87 #include <dt-bindings/clock/qcom,rpmh.h> 88 #include <dt-bindings/gpio/gpio.h> 89 #include <dt-bindings/interrupt-controller/arm-gic.h> 90 91 soc { 92 #address-cells = <2>; 93 #size-cells = <2>; 94 95 pcie@1c08000 { 96 compatible = "qcom,pcie-sc7280"; 97 reg = <0 0x01c08000 0 0x3000>, 98 <0 0x40000000 0 0xf1d>, 99 <0 0x40000f20 0 0xa8>, 100 <0 0x40001000 0 0x1000>, 101 <0 0x40100000 0 0x100000>; 102 reg-names = "parf", "dbi", "elbi", "atu", "config"; 103 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 104 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 105 106 bus-range = <0x00 0xff>; 107 device_type = "pci"; 108 linux,pci-domain = <1>; 109 num-lanes = <2>; 110 111 #address-cells = <3>; 112 #size-cells = <2>; 113 114 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 115 assigned-clock-rates = <19200000>; 116 117 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 118 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 119 <&pcie1_phy>, 120 <&rpmhcc RPMH_CXO_CLK>, 121 <&gcc GCC_PCIE_1_AUX_CLK>, 122 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 123 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 124 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 125 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 126 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 127 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 128 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 129 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 130 131 clock-names = "pipe", 132 "pipe_mux", 133 "phy_pipe", 134 "ref", 135 "aux", 136 "cfg", 137 "bus_master", 138 "bus_slave", 139 "slave_q2a", 140 "tbu", 141 "ddrss_sf_tbu", 142 "aggre0", 143 "aggre1"; 144 145 dma-coherent; 146 147 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "msi0", "msi1", "msi2", "msi3", 157 "msi4", "msi5", "msi6", "msi7", "global"; 158 #interrupt-cells = <1>; 159 interrupt-map-mask = <0 0 0 0x7>; 160 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 161 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 162 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 163 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 164 165 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 166 <0x100 &apps_smmu 0x1c81 0x1>; 167 168 phys = <&pcie1_phy>; 169 phy-names = "pciephy"; 170 171 pinctrl-names = "default"; 172 pinctrl-0 = <&pcie1_clkreq_n>; 173 174 power-domains = <&gcc GCC_PCIE_1_GDSC>; 175 176 resets = <&gcc GCC_PCIE_1_BCR>; 177 reset-names = "pci"; 178 179 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; 180 vddpe-3v3-supply = <&pp3300_ssd>; 181 }; 182 }; 183