1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/opp/opp-v2-qcom-adreno.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Adreno compatible OPP supply 8 9description: 10 Adreno GPUs present in Qualcomm's Snapdragon chipsets uses an OPP specific 11 ACD related information tailored for the specific chipset. This binding 12 provides the information needed to describe such a hardware value. 13 14maintainers: 15 - Rob Clark <robdclark@gmail.com> 16 17allOf: 18 - $ref: opp-v2-base.yaml# 19 20properties: 21 compatible: 22 contains: 23 const: operating-points-v2-adreno 24 25patternProperties: 26 '^opp-[0-9]+$': 27 type: object 28 additionalProperties: false 29 30 properties: 31 opp-hz: true 32 33 opp-level: true 34 35 opp-peak-kBps: true 36 37 opp-supported-hw: true 38 39 qcom,opp-acd-level: 40 description: | 41 A positive value representing the ACD (Adaptive Clock Distribution, 42 a fancy name for clk throttling during voltage droop) level associated 43 with this OPP node. This value is shared to a co-processor inside GPU 44 (called Graphics Management Unit a.k.a GMU) during wake up. It may not 45 be present for some OPPs and GMU will disable ACD while transitioning 46 to that OPP. This value encodes a voltage threshold, delay cycles & 47 calibration margins which are identified by characterization of the 48 SoC. So, it doesn't have any unit. This data is passed to GMU firmware 49 via 'HFI_H2F_MSG_ACD' packet. 50 $ref: /schemas/types.yaml#/definitions/uint32 51 52 required: 53 - opp-hz 54 - opp-level 55 56required: 57 - compatible 58 59additionalProperties: false 60 61examples: 62 - | 63 #include <dt-bindings/power/qcom-rpmpd.h> 64 65 gpu_opp_table: opp-table { 66 compatible = "operating-points-v2-adreno", "operating-points-v2"; 67 68 opp-687000000 { 69 opp-hz = /bits/ 64 <687000000>; 70 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 71 opp-peak-kBps = <8171875>; 72 qcom,opp-acd-level = <0x882e5ffd>; 73 }; 74 75 opp-550000000 { 76 opp-hz = /bits/ 64 <550000000>; 77 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 78 opp-peak-kBps = <6074219>; 79 qcom,opp-acd-level = <0xc0285ffd>; 80 }; 81 82 opp-390000000 { 83 opp-hz = /bits/ 64 <390000000>; 84 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 85 opp-peak-kBps = <3000000>; 86 qcom,opp-acd-level = <0xc0285ffd>; 87 }; 88 89 opp-300000000 { 90 opp-hz = /bits/ 64 <300000000>; 91 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 92 opp-peak-kBps = <2136719>; 93 /* Intentionally left out qcom,opp-acd-level property here */ 94 }; 95 96 }; 97