1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MTK MSDC Storage Host Controller 8 9maintainers: 10 - Chaotian Jing <chaotian.jing@mediatek.com> 11 - Wenbin Mei <wenbin.mei@mediatek.com> 12 13properties: 14 compatible: 15 oneOf: 16 - enum: 17 - mediatek,mt2701-mmc 18 - mediatek,mt2712-mmc 19 - mediatek,mt6779-mmc 20 - mediatek,mt6795-mmc 21 - mediatek,mt7620-mmc 22 - mediatek,mt7622-mmc 23 - mediatek,mt7986-mmc 24 - mediatek,mt7988-mmc 25 - mediatek,mt8135-mmc 26 - mediatek,mt8173-mmc 27 - mediatek,mt8183-mmc 28 - mediatek,mt8196-mmc 29 - mediatek,mt8516-mmc 30 - items: 31 - const: mediatek,mt7623-mmc 32 - const: mediatek,mt2701-mmc 33 - items: 34 - enum: 35 - mediatek,mt6893-mmc 36 - mediatek,mt8186-mmc 37 - mediatek,mt8188-mmc 38 - mediatek,mt8192-mmc 39 - mediatek,mt8195-mmc 40 - mediatek,mt8365-mmc 41 - const: mediatek,mt8183-mmc 42 43 reg: 44 minItems: 1 45 items: 46 - description: base register (required). 47 - description: top base register (required for MT8183). 48 49 clocks: 50 description: 51 Should contain phandle for the clock feeding the MMC controller. 52 minItems: 2 53 maxItems: 7 54 55 clock-names: 56 minItems: 2 57 maxItems: 7 58 59 interrupts: 60 description: 61 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended 62 interrupt is required and be configured as wakeup source irq. 63 minItems: 1 64 maxItems: 2 65 66 interrupt-names: 67 items: 68 - const: msdc 69 - const: sdio_wakeup 70 71 pinctrl-names: 72 description: 73 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin 74 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this 75 scenario. 76 minItems: 2 77 items: 78 - const: default 79 - const: state_uhs 80 - const: state_eint 81 82 pinctrl-0: 83 description: 84 should contain default/high speed pin ctrl. 85 maxItems: 1 86 87 pinctrl-1: 88 description: 89 should contain uhs mode pin ctrl. 90 maxItems: 1 91 92 pinctrl-2: 93 description: 94 should switch dat1 pin to GPIO mode. 95 maxItems: 1 96 97 hs400-ds-delay: 98 $ref: /schemas/types.yaml#/definitions/uint32 99 description: 100 HS400 DS delay setting. 101 minimum: 0 102 maximum: 0xffffffff 103 104 mediatek,hs200-cmd-int-delay: 105 $ref: /schemas/types.yaml#/definitions/uint32 106 description: 107 HS200 command internal delay setting. 108 This field has total 32 stages. 109 The value is an integer from 0 to 31. 110 minimum: 0 111 maximum: 31 112 113 mediatek,hs400-cmd-int-delay: 114 $ref: /schemas/types.yaml#/definitions/uint32 115 description: 116 HS400 command internal delay setting. 117 This field has total 32 stages. 118 The value is an integer from 0 to 31. 119 minimum: 0 120 maximum: 31 121 122 mediatek,hs400-cmd-resp-sel-rising: 123 $ref: /schemas/types.yaml#/definitions/flag 124 description: 125 HS400 command response sample selection. 126 If present, HS400 command responses are sampled on rising edges. 127 If not present, HS400 command responses are sampled on falling edges. 128 129 mediatek,hs400-ds-dly3: 130 $ref: /schemas/types.yaml#/definitions/uint32 131 description: 132 Gear of the third delay line for DS for input data latch in data 133 pad macro, there are 32 stages from 0 to 31. 134 For different corner IC, the time is different about one step, it is 135 about 100ps. 136 The value is confirmed by doing scan and calibration to find a best 137 value with corner IC and it is valid only for HS400 mode. 138 minimum: 0 139 maximum: 31 140 141 mediatek,latch-ck: 142 $ref: /schemas/types.yaml#/definitions/uint32 143 description: 144 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid 145 data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. 146 if not present, default value is 0. 147 applied to compatible "mediatek,mt2701-mmc". 148 minimum: 0 149 maximum: 7 150 151 mediatek,tuning-step: 152 $ref: /schemas/types.yaml#/definitions/uint32 153 description: 154 Some SoCs need extend tuning step for better delay value to avoid CRC issue. 155 If not present, default tuning step is 32. For eMMC and SD, this can yield 156 satisfactory calibration results in most cases. 157 enum: [32, 64] 158 default: 32 159 160 resets: 161 maxItems: 1 162 163 reset-names: 164 const: hrst 165 166required: 167 - compatible 168 - reg 169 - interrupts 170 - clocks 171 - clock-names 172 - pinctrl-names 173 - pinctrl-0 174 - pinctrl-1 175 - vmmc-supply 176 - vqmmc-supply 177 178allOf: 179 - $ref: mmc-controller.yaml# 180 - if: 181 properties: 182 compatible: 183 enum: 184 - mediatek,mt2701-mmc 185 - mediatek,mt6779-mmc 186 - mediatek,mt6795-mmc 187 - mediatek,mt7620-mmc 188 - mediatek,mt7622-mmc 189 - mediatek,mt7623-mmc 190 - mediatek,mt8135-mmc 191 - mediatek,mt8173-mmc 192 - mediatek,mt8183-mmc 193 - mediatek,mt8186-mmc 194 - mediatek,mt8188-mmc 195 - mediatek,mt8195-mmc 196 - mediatek,mt8196-mmc 197 - mediatek,mt8516-mmc 198 then: 199 properties: 200 clocks: 201 minItems: 2 202 items: 203 - description: source clock 204 - description: HCLK which used for host 205 - description: independent source clock gate 206 clock-names: 207 minItems: 2 208 items: 209 - const: source 210 - const: hclk 211 - const: source_cg 212 213 - if: 214 properties: 215 compatible: 216 contains: 217 const: mediatek,mt2712-mmc 218 then: 219 properties: 220 clocks: 221 minItems: 3 222 items: 223 - description: source clock 224 - description: HCLK which used for host 225 - description: independent source clock gate 226 - description: bus clock used for internal register access (required for MSDC0/3). 227 clock-names: 228 minItems: 3 229 items: 230 - const: source 231 - const: hclk 232 - const: source_cg 233 - const: bus_clk 234 235 - if: 236 properties: 237 compatible: 238 contains: 239 enum: 240 - mediatek,mt7986-mmc 241 - mediatek,mt7988-mmc 242 - mediatek,mt8183-mmc 243 - mediatek,mt8196-mmc 244 then: 245 properties: 246 reg: 247 minItems: 2 248 else: 249 properties: 250 reg: 251 maxItems: 1 252 253 - if: 254 properties: 255 compatible: 256 contains: 257 enum: 258 - mediatek,mt7986-mmc 259 then: 260 properties: 261 clocks: 262 minItems: 3 263 items: 264 - description: source clock 265 - description: HCLK which used for host 266 - description: independent source clock gate 267 - description: bus clock used for internal register access (required for MSDC0/3). 268 - description: msdc subsys clock gate 269 clock-names: 270 minItems: 3 271 items: 272 - const: source 273 - const: hclk 274 - const: source_cg 275 - const: bus_clk 276 - const: sys_cg 277 278 - if: 279 properties: 280 compatible: 281 contains: 282 enum: 283 - mediatek,mt7988-mmc 284 then: 285 properties: 286 clocks: 287 items: 288 - description: source clock 289 - description: HCLK which used for host 290 - description: Advanced eXtensible Interface 291 - description: Advanced High-performance Bus clock 292 clock-names: 293 items: 294 - const: source 295 - const: hclk 296 - const: axi_cg 297 - const: ahb_cg 298 299 - if: 300 properties: 301 compatible: 302 enum: 303 - mediatek,mt6893-mmc 304 - mediatek,mt8186-mmc 305 - mediatek,mt8188-mmc 306 - mediatek,mt8195-mmc 307 then: 308 properties: 309 clocks: 310 items: 311 - description: source clock 312 - description: HCLK which used for host 313 - description: independent source clock gate 314 - description: crypto clock used for data encrypt/decrypt (optional) 315 clock-names: 316 items: 317 - const: source 318 - const: hclk 319 - const: source_cg 320 - const: crypto 321 322 - if: 323 properties: 324 compatible: 325 contains: 326 const: mediatek,mt8192-mmc 327 then: 328 properties: 329 clocks: 330 items: 331 - description: source clock 332 - description: HCLK which used for host 333 - description: independent source clock gate 334 - description: msdc subsys clock gate 335 - description: peripheral bus clock gate 336 - description: AXI bus clock gate 337 - description: AHB bus clock gate 338 clock-names: 339 items: 340 - const: source 341 - const: hclk 342 - const: source_cg 343 - const: sys_cg 344 - const: pclk_cg 345 - const: axi_cg 346 - const: ahb_cg 347 348unevaluatedProperties: false 349 350examples: 351 - | 352 #include <dt-bindings/interrupt-controller/irq.h> 353 #include <dt-bindings/interrupt-controller/arm-gic.h> 354 #include <dt-bindings/clock/mt8173-clk.h> 355 mmc0: mmc@11230000 { 356 compatible = "mediatek,mt8173-mmc"; 357 reg = <0x11230000 0x1000>; 358 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; 359 vmmc-supply = <&mt6397_vemc_3v3_reg>; 360 vqmmc-supply = <&mt6397_vio18_reg>; 361 clocks = <&pericfg CLK_PERI_MSDC30_0>, 362 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 363 clock-names = "source", "hclk"; 364 pinctrl-names = "default", "state_uhs"; 365 pinctrl-0 = <&mmc0_pins_default>; 366 pinctrl-1 = <&mmc0_pins_uhs>; 367 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; 368 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 369 hs400-ds-delay = <0x14015>; 370 mediatek,hs200-cmd-int-delay = <26>; 371 mediatek,hs400-cmd-int-delay = <14>; 372 mediatek,hs400-cmd-resp-sel-rising; 373 }; 374 375 mmc3: mmc@11260000 { 376 compatible = "mediatek,mt8173-mmc"; 377 reg = <0x11260000 0x1000>; 378 clock-names = "source", "hclk"; 379 clocks = <&pericfg CLK_PERI_MSDC30_3>, 380 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 381 interrupt-names = "msdc", "sdio_wakeup"; 382 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>, 383 <&pio 23 IRQ_TYPE_LEVEL_LOW>; 384 pinctrl-names = "default", "state_uhs", "state_eint"; 385 pinctrl-0 = <&mmc2_pins_default>; 386 pinctrl-1 = <&mmc2_pins_uhs>; 387 pinctrl-2 = <&mmc2_pins_eint>; 388 bus-width = <4>; 389 max-frequency = <200000000>; 390 cap-sd-highspeed; 391 sd-uhs-sdr104; 392 keep-power-in-suspend; 393 wakeup-source; 394 cap-sdio-irq; 395 no-mmc; 396 no-sd; 397 non-removable; 398 vmmc-supply = <&sdio_fixed_3v3>; 399 vqmmc-supply = <&mt6397_vgp3_reg>; 400 mmc-pwrseq = <&wifi_pwrseq>; 401 }; 402 403... 404