1c49a5d09SLeonard Crestez# SPDX-License-Identifier: GPL-2.0 2c49a5d09SLeonard Crestez%YAML 1.2 3c49a5d09SLeonard Crestez--- 4c49a5d09SLeonard Crestez$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# 5c49a5d09SLeonard Crestez$schema: http://devicetree.org/meta-schemas/core.yaml# 6c49a5d09SLeonard Crestez 7c49a5d09SLeonard Cresteztitle: i.MX8M DDR Controller 8c49a5d09SLeonard Crestez 9c49a5d09SLeonard Crestezmaintainers: 10*96c9b511SKrzysztof Kozlowski - Peng Fan <peng.fan@nxp.com> 11c49a5d09SLeonard Crestez 12c49a5d09SLeonard Crestezdescription: 13c49a5d09SLeonard Crestez The DDRC block is integrated in i.MX8M for interfacing with DDR based 14c49a5d09SLeonard Crestez memories. 15c49a5d09SLeonard Crestez 16c49a5d09SLeonard Crestez It supports switching between different frequencies at runtime but during 17c49a5d09SLeonard Crestez this process RAM itself becomes briefly inaccessible so actual frequency 18c49a5d09SLeonard Crestez switching is implemented by TF-A code which runs from a SRAM area. 19c49a5d09SLeonard Crestez 20c49a5d09SLeonard Crestez The Linux driver for the DDRC doesn't even map registers (they're included 21c49a5d09SLeonard Crestez for the sake of "describing hardware"), it mostly just exposes firmware 22c49a5d09SLeonard Crestez capabilities through standard Linux mechanism like devfreq and OPP tables. 23c49a5d09SLeonard Crestez 24c49a5d09SLeonard Crestezproperties: 25c49a5d09SLeonard Crestez compatible: 26c49a5d09SLeonard Crestez items: 27c49a5d09SLeonard Crestez - enum: 28c49a5d09SLeonard Crestez - fsl,imx8mn-ddrc 29c49a5d09SLeonard Crestez - fsl,imx8mm-ddrc 30c49a5d09SLeonard Crestez - fsl,imx8mq-ddrc 31c49a5d09SLeonard Crestez - const: fsl,imx8m-ddrc 32c49a5d09SLeonard Crestez 33c49a5d09SLeonard Crestez reg: 34c49a5d09SLeonard Crestez maxItems: 1 35c49a5d09SLeonard Crestez description: 36c49a5d09SLeonard Crestez Base address and size of DDRC CTL area. 37c49a5d09SLeonard Crestez This is not currently mapped by the imx8m-ddrc driver. 38c49a5d09SLeonard Crestez 39c49a5d09SLeonard Crestez clocks: 40c49a5d09SLeonard Crestez maxItems: 4 41c49a5d09SLeonard Crestez 42c49a5d09SLeonard Crestez clock-names: 43c49a5d09SLeonard Crestez items: 44c49a5d09SLeonard Crestez - const: core 45c49a5d09SLeonard Crestez - const: pll 46c49a5d09SLeonard Crestez - const: alt 47c49a5d09SLeonard Crestez - const: apb 48c49a5d09SLeonard Crestez 49c49a5d09SLeonard Crestez operating-points-v2: true 5066320b26SKrzysztof Kozlowski opp-table: 5166320b26SKrzysztof Kozlowski type: object 52c49a5d09SLeonard Crestez 53c49a5d09SLeonard Crestezrequired: 54c49a5d09SLeonard Crestez - reg 55c49a5d09SLeonard Crestez - compatible 56c49a5d09SLeonard Crestez - clocks 57c49a5d09SLeonard Crestez - clock-names 58c49a5d09SLeonard Crestez 59c49a5d09SLeonard CrestezadditionalProperties: false 60c49a5d09SLeonard Crestez 61c49a5d09SLeonard Crestezexamples: 62c49a5d09SLeonard Crestez - | 63c49a5d09SLeonard Crestez #include <dt-bindings/clock/imx8mm-clock.h> 64c49a5d09SLeonard Crestez ddrc: memory-controller@3d400000 { 65c49a5d09SLeonard Crestez compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 66c49a5d09SLeonard Crestez reg = <0x3d400000 0x400000>; 67c49a5d09SLeonard Crestez clock-names = "core", "pll", "alt", "apb"; 68c49a5d09SLeonard Crestez clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 69c49a5d09SLeonard Crestez <&clk IMX8MM_DRAM_PLL>, 70c49a5d09SLeonard Crestez <&clk IMX8MM_CLK_DRAM_ALT>, 71c49a5d09SLeonard Crestez <&clk IMX8MM_CLK_DRAM_APB>; 72c49a5d09SLeonard Crestez operating-points-v2 = <&ddrc_opp_table>; 73c49a5d09SLeonard Crestez }; 74