xref: /linux/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml (revision 6315d93541f8a5f77c5ef5c4f25233e66d189603) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm iris video encode and decode accelerators
8
9maintainers:
10  - Vikash Garodia <quic_vgarodia@quicinc.com>
11  - Dikshita Agarwal <quic_dikshita@quicinc.com>
12
13description:
14  The iris video processing unit is a video encode and decode accelerator
15  present on Qualcomm platforms.
16
17allOf:
18  - $ref: qcom,venus-common.yaml#
19
20properties:
21  compatible:
22    const: qcom,sm8550-iris
23
24  power-domains:
25    maxItems: 4
26
27  power-domain-names:
28    items:
29      - const: venus
30      - const: vcodec0
31      - const: mxc
32      - const: mmcx
33
34  clocks:
35    maxItems: 3
36
37  clock-names:
38    items:
39      - const: iface
40      - const: core
41      - const: vcodec0_core
42
43  interconnects:
44    maxItems: 2
45
46  interconnect-names:
47    items:
48      - const: cpu-cfg
49      - const: video-mem
50
51  resets:
52    maxItems: 1
53
54  reset-names:
55    items:
56      - const: bus
57
58  iommus:
59    maxItems: 2
60
61  dma-coherent: true
62
63  operating-points-v2: true
64
65  opp-table:
66    type: object
67
68required:
69  - compatible
70  - power-domain-names
71  - interconnects
72  - interconnect-names
73  - resets
74  - reset-names
75  - iommus
76  - dma-coherent
77
78unevaluatedProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
84    #include <dt-bindings/clock/qcom,sm8450-videocc.h>
85    #include <dt-bindings/interrupt-controller/arm-gic.h>
86    #include <dt-bindings/interconnect/qcom,icc.h>
87    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
88    #include <dt-bindings/power/qcom-rpmpd.h>
89    #include <dt-bindings/power/qcom,rpmhpd.h>
90
91    video-codec@aa00000 {
92        compatible = "qcom,sm8550-iris";
93        reg = <0x0aa00000 0xf0000>;
94        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
95
96        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
97                        <&videocc VIDEO_CC_MVS0_GDSC>,
98                        <&rpmhpd RPMHPD_MXC>,
99                        <&rpmhpd RPMHPD_MMCX>;
100        power-domain-names = "venus", "vcodec0", "mxc", "mmcx";
101
102        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
103                 <&videocc VIDEO_CC_MVS0C_CLK>,
104                 <&videocc VIDEO_CC_MVS0_CLK>;
105        clock-names = "iface", "core", "vcodec0_core";
106
107        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
108                         &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>,
109                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
110                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
111        interconnect-names = "cpu-cfg", "video-mem";
112
113        memory-region = <&video_mem>;
114
115        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
116        reset-names = "bus";
117
118        iommus = <&apps_smmu 0x1940 0x0000>,
119                 <&apps_smmu 0x1947 0x0000>;
120        dma-coherent;
121
122        operating-points-v2 = <&iris_opp_table>;
123
124        iris_opp_table: opp-table {
125            compatible = "operating-points-v2";
126
127            opp-240000000 {
128                opp-hz = /bits/ 64 <240000000>;
129                required-opps = <&rpmhpd_opp_svs>,
130                                <&rpmhpd_opp_low_svs>;
131            };
132
133            opp-338000000 {
134                opp-hz = /bits/ 64 <338000000>;
135                required-opps = <&rpmhpd_opp_svs>,
136                                <&rpmhpd_opp_svs>;
137            };
138
139            opp-366000000 {
140                opp-hz = /bits/ 64 <366000000>;
141                required-opps = <&rpmhpd_opp_svs_l1>,
142                                <&rpmhpd_opp_svs_l1>;
143            };
144
145            opp-444000000 {
146                opp-hz = /bits/ 64 <444000000>;
147                required-opps = <&rpmhpd_opp_turbo>,
148                                <&rpmhpd_opp_turbo>;
149            };
150
151            opp-533333334 {
152                opp-hz = /bits/ 64 <533333334>;
153                required-opps = <&rpmhpd_opp_turbo_l1>,
154                                <&rpmhpd_opp_turbo_l1>;
155            };
156        };
157    };
158...
159