1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SM8550 Camera Subsystem (CAMSS) 8 9maintainers: 10 - Depeng Shao <quic_depengs@quicinc.com> 11 12description: 13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. 14 15properties: 16 compatible: 17 const: qcom,sm8550-camss 18 19 reg: 20 maxItems: 19 21 22 reg-names: 23 items: 24 - const: csid0 25 - const: csid1 26 - const: csid2 27 - const: csid_lite0 28 - const: csid_lite1 29 - const: csid_wrapper 30 - const: csiphy0 31 - const: csiphy1 32 - const: csiphy2 33 - const: csiphy3 34 - const: csiphy4 35 - const: csiphy5 36 - const: csiphy6 37 - const: csiphy7 38 - const: vfe0 39 - const: vfe1 40 - const: vfe2 41 - const: vfe_lite0 42 - const: vfe_lite1 43 44 clocks: 45 maxItems: 36 46 47 clock-names: 48 items: 49 - const: camnoc_axi 50 - const: cpas_ahb 51 - const: cpas_fast_ahb_clk 52 - const: cpas_ife_lite 53 - const: cpas_vfe0 54 - const: cpas_vfe1 55 - const: cpas_vfe2 56 - const: csid 57 - const: csiphy0 58 - const: csiphy0_timer 59 - const: csiphy1 60 - const: csiphy1_timer 61 - const: csiphy2 62 - const: csiphy2_timer 63 - const: csiphy3 64 - const: csiphy3_timer 65 - const: csiphy4 66 - const: csiphy4_timer 67 - const: csiphy5 68 - const: csiphy5_timer 69 - const: csiphy6 70 - const: csiphy6_timer 71 - const: csiphy7 72 - const: csiphy7_timer 73 - const: csiphy_rx 74 - const: gcc_axi_hf 75 - const: vfe0 76 - const: vfe0_fast_ahb 77 - const: vfe1 78 - const: vfe1_fast_ahb 79 - const: vfe2 80 - const: vfe2_fast_ahb 81 - const: vfe_lite 82 - const: vfe_lite_ahb 83 - const: vfe_lite_cphy_rx 84 - const: vfe_lite_csid 85 86 interrupts: 87 maxItems: 18 88 89 interrupt-names: 90 items: 91 - const: csid0 92 - const: csid1 93 - const: csid2 94 - const: csid_lite0 95 - const: csid_lite1 96 - const: csiphy0 97 - const: csiphy1 98 - const: csiphy2 99 - const: csiphy3 100 - const: csiphy4 101 - const: csiphy5 102 - const: csiphy6 103 - const: csiphy7 104 - const: vfe0 105 - const: vfe1 106 - const: vfe2 107 - const: vfe_lite0 108 - const: vfe_lite1 109 110 interconnects: 111 maxItems: 2 112 113 interconnect-names: 114 items: 115 - const: ahb 116 - const: hf_0_mnoc 117 118 iommus: 119 maxItems: 1 120 121 power-domains: 122 items: 123 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. 124 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. 125 - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. 126 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. 127 128 power-domain-names: 129 items: 130 - const: ife0 131 - const: ife1 132 - const: ife2 133 - const: top 134 135 vdda-phy-supply: 136 description: 137 Phandle to a regulator supply to PHY core block. 138 139 vdda-pll-supply: 140 description: 141 Phandle to 1.2V regulator supply to PHY refclk pll block. 142 143 ports: 144 $ref: /schemas/graph.yaml#/properties/ports 145 146 description: 147 CSI input ports. 148 149 properties: 150 port@0: 151 $ref: /schemas/graph.yaml#/$defs/port-base 152 unevaluatedProperties: false 153 description: 154 Input port for receiving CSI data on CSI0. 155 156 properties: 157 endpoint: 158 $ref: video-interfaces.yaml# 159 unevaluatedProperties: false 160 161 properties: 162 clock-lanes: 163 maxItems: 1 164 165 data-lanes: 166 minItems: 1 167 maxItems: 4 168 169 bus-type: 170 enum: 171 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 172 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 173 174 required: 175 - clock-lanes 176 - data-lanes 177 178 port@1: 179 $ref: /schemas/graph.yaml#/$defs/port-base 180 unevaluatedProperties: false 181 description: 182 Input port for receiving CSI data on CSI1. 183 184 properties: 185 endpoint: 186 $ref: video-interfaces.yaml# 187 unevaluatedProperties: false 188 189 properties: 190 clock-lanes: 191 maxItems: 1 192 193 data-lanes: 194 minItems: 1 195 maxItems: 4 196 197 bus-type: 198 enum: 199 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 200 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 201 202 required: 203 - clock-lanes 204 - data-lanes 205 206 port@2: 207 $ref: /schemas/graph.yaml#/$defs/port-base 208 unevaluatedProperties: false 209 description: 210 Input port for receiving CSI data on CSI2. 211 212 properties: 213 endpoint: 214 $ref: video-interfaces.yaml# 215 unevaluatedProperties: false 216 217 properties: 218 clock-lanes: 219 maxItems: 1 220 221 data-lanes: 222 minItems: 1 223 maxItems: 4 224 225 bus-type: 226 enum: 227 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 228 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 229 230 required: 231 - clock-lanes 232 - data-lanes 233 234 port@3: 235 $ref: /schemas/graph.yaml#/$defs/port-base 236 unevaluatedProperties: false 237 description: 238 Input port for receiving CSI data on CSI3. 239 240 properties: 241 endpoint: 242 $ref: video-interfaces.yaml# 243 unevaluatedProperties: false 244 245 properties: 246 clock-lanes: 247 maxItems: 1 248 249 data-lanes: 250 minItems: 1 251 maxItems: 4 252 253 bus-type: 254 enum: 255 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 256 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 257 258 required: 259 - clock-lanes 260 - data-lanes 261 262 port@4: 263 $ref: /schemas/graph.yaml#/$defs/port-base 264 unevaluatedProperties: false 265 description: 266 Input port for receiving CSI data on CSI4. 267 268 properties: 269 endpoint: 270 $ref: video-interfaces.yaml# 271 unevaluatedProperties: false 272 273 properties: 274 clock-lanes: 275 maxItems: 1 276 277 data-lanes: 278 minItems: 1 279 maxItems: 4 280 281 bus-type: 282 enum: 283 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 284 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 285 286 required: 287 - clock-lanes 288 - data-lanes 289 290 port@5: 291 $ref: /schemas/graph.yaml#/$defs/port-base 292 unevaluatedProperties: false 293 description: 294 Input port for receiving CSI data on CSI5. 295 296 properties: 297 endpoint: 298 $ref: video-interfaces.yaml# 299 unevaluatedProperties: false 300 301 properties: 302 clock-lanes: 303 maxItems: 1 304 305 data-lanes: 306 minItems: 1 307 maxItems: 4 308 309 bus-type: 310 enum: 311 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 312 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 313 314 required: 315 - clock-lanes 316 - data-lanes 317 318 port@6: 319 $ref: /schemas/graph.yaml#/$defs/port-base 320 unevaluatedProperties: false 321 description: 322 Input port for receiving CSI data on CSI6. 323 324 properties: 325 endpoint: 326 $ref: video-interfaces.yaml# 327 unevaluatedProperties: false 328 329 properties: 330 clock-lanes: 331 maxItems: 1 332 333 data-lanes: 334 minItems: 1 335 maxItems: 4 336 337 bus-type: 338 enum: 339 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 340 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 341 342 required: 343 - clock-lanes 344 - data-lanes 345 346 port@7: 347 $ref: /schemas/graph.yaml#/$defs/port-base 348 unevaluatedProperties: false 349 description: 350 Input port for receiving CSI data on CSI7. 351 352 properties: 353 endpoint: 354 $ref: video-interfaces.yaml# 355 unevaluatedProperties: false 356 357 properties: 358 clock-lanes: 359 maxItems: 1 360 361 data-lanes: 362 minItems: 1 363 maxItems: 4 364 365 bus-type: 366 enum: 367 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY 368 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 369 370 required: 371 - clock-lanes 372 - data-lanes 373 374required: 375 - compatible 376 - reg 377 - reg-names 378 - clocks 379 - clock-names 380 - interrupts 381 - interrupt-names 382 - interconnects 383 - interconnect-names 384 - iommus 385 - power-domains 386 - power-domain-names 387 - vdda-phy-supply 388 - vdda-pll-supply 389 390additionalProperties: false 391 392examples: 393 - | 394 #include <dt-bindings/clock/qcom,rpmh.h> 395 #include <dt-bindings/clock/qcom,sm8550-camcc.h> 396 #include <dt-bindings/clock/qcom,sm8550-gcc.h> 397 #include <dt-bindings/interconnect/qcom,icc.h> 398 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 399 #include <dt-bindings/interrupt-controller/arm-gic.h> 400 #include <dt-bindings/power/qcom-rpmpd.h> 401 402 soc { 403 #address-cells = <2>; 404 #size-cells = <2>; 405 406 isp@acb7000 { 407 compatible = "qcom,sm8550-camss"; 408 409 reg = <0 0x0acb7000 0 0xd00>, 410 <0 0x0acb9000 0 0xd00>, 411 <0 0x0acbb000 0 0xd00>, 412 <0 0x0acca000 0 0xa00>, 413 <0 0x0acce000 0 0xa00>, 414 <0 0x0acb6000 0 0x1000>, 415 <0 0x0ace4000 0 0x2000>, 416 <0 0x0ace6000 0 0x2000>, 417 <0 0x0ace8000 0 0x2000>, 418 <0 0x0acea000 0 0x2000>, 419 <0 0x0acec000 0 0x2000>, 420 <0 0x0acee000 0 0x2000>, 421 <0 0x0acf0000 0 0x2000>, 422 <0 0x0acf2000 0 0x2000>, 423 <0 0x0ac62000 0 0xf000>, 424 <0 0x0ac71000 0 0xf000>, 425 <0 0x0ac80000 0 0xf000>, 426 <0 0x0accb000 0 0x1800>, 427 <0 0x0accf000 0 0x1800>; 428 reg-names = "csid0", 429 "csid1", 430 "csid2", 431 "csid_lite0", 432 "csid_lite1", 433 "csid_wrapper", 434 "csiphy0", 435 "csiphy1", 436 "csiphy2", 437 "csiphy3", 438 "csiphy4", 439 "csiphy5", 440 "csiphy6", 441 "csiphy7", 442 "vfe0", 443 "vfe1", 444 "vfe2", 445 "vfe_lite0", 446 "vfe_lite1"; 447 448 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 449 <&camcc CAM_CC_CPAS_AHB_CLK>, 450 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 451 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 452 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 453 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 454 <&camcc CAM_CC_CPAS_IFE_2_CLK>, 455 <&camcc CAM_CC_CSID_CLK>, 456 <&camcc CAM_CC_CSIPHY0_CLK>, 457 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 458 <&camcc CAM_CC_CSIPHY1_CLK>, 459 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 460 <&camcc CAM_CC_CSIPHY2_CLK>, 461 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 462 <&camcc CAM_CC_CSIPHY3_CLK>, 463 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 464 <&camcc CAM_CC_CSIPHY4_CLK>, 465 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 466 <&camcc CAM_CC_CSIPHY5_CLK>, 467 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 468 <&camcc CAM_CC_CSIPHY6_CLK>, 469 <&camcc CAM_CC_CSI6PHYTIMER_CLK>, 470 <&camcc CAM_CC_CSIPHY7_CLK>, 471 <&camcc CAM_CC_CSI7PHYTIMER_CLK>, 472 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 473 <&gcc GCC_CAMERA_HF_AXI_CLK>, 474 <&camcc CAM_CC_IFE_0_CLK>, 475 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 476 <&camcc CAM_CC_IFE_1_CLK>, 477 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 478 <&camcc CAM_CC_IFE_2_CLK>, 479 <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, 480 <&camcc CAM_CC_IFE_LITE_CLK>, 481 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 482 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 483 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 484 clock-names = "camnoc_axi", 485 "cpas_ahb", 486 "cpas_fast_ahb_clk", 487 "cpas_ife_lite", 488 "cpas_vfe0", 489 "cpas_vfe1", 490 "cpas_vfe2", 491 "csid", 492 "csiphy0", 493 "csiphy0_timer", 494 "csiphy1", 495 "csiphy1_timer", 496 "csiphy2", 497 "csiphy2_timer", 498 "csiphy3", 499 "csiphy3_timer", 500 "csiphy4", 501 "csiphy4_timer", 502 "csiphy5", 503 "csiphy5_timer", 504 "csiphy6", 505 "csiphy6_timer", 506 "csiphy7", 507 "csiphy7_timer", 508 "csiphy_rx", 509 "gcc_axi_hf", 510 "vfe0", 511 "vfe0_fast_ahb", 512 "vfe1", 513 "vfe1_fast_ahb", 514 "vfe2", 515 "vfe2_fast_ahb", 516 "vfe_lite", 517 "vfe_lite_ahb", 518 "vfe_lite_cphy_rx", 519 "vfe_lite_csid"; 520 521 interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>, 522 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 523 <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, 524 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>, 525 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 526 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>; 539 interrupt-names = "csid0", 540 "csid1", 541 "csid2", 542 "csid_lite0", 543 "csid_lite1", 544 "csiphy0", 545 "csiphy1", 546 "csiphy2", 547 "csiphy3", 548 "csiphy4", 549 "csiphy5", 550 "csiphy6", 551 "csiphy7", 552 "vfe0", 553 "vfe1", 554 "vfe2", 555 "vfe_lite0", 556 "vfe_lite1"; 557 558 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 559 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 560 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 561 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 562 interconnect-names = "ahb", 563 "hf_0_mnoc"; 564 565 iommus = <&apps_smmu 0x800 0x20>; 566 567 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 568 <&camcc CAM_CC_IFE_1_GDSC>, 569 <&camcc CAM_CC_IFE_2_GDSC>, 570 <&camcc CAM_CC_TITAN_TOP_GDSC>; 571 power-domain-names = "ife0", 572 "ife1", 573 "ife2", 574 "top"; 575 576 vdda-phy-supply = <&vreg_l1e_0p88>; 577 vdda-pll-supply = <&vreg_l3e_1p2>; 578 579 ports { 580 #address-cells = <1>; 581 #size-cells = <0>; 582 583 port@0 { 584 reg = <0>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 588 csiphy_ep0: endpoint@0 { 589 reg = <0>; 590 clock-lanes = <7>; 591 data-lanes = <0 1>; 592 remote-endpoint = <&sensor_ep>; 593 }; 594 }; 595 }; 596 }; 597 }; 598