1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm CAMSS ISP 8 9maintainers: 10 - Robert Foss <robert.foss@linaro.org> 11 - Todor Tomov <todor.too@gmail.com> 12 13description: | 14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms 15 16properties: 17 compatible: 18 const: qcom,msm8916-camss 19 20 clocks: 21 minItems: 19 22 maxItems: 19 23 24 clock-names: 25 items: 26 - const: top_ahb 27 - const: ispif_ahb 28 - const: csiphy0_timer 29 - const: csiphy1_timer 30 - const: csi0_ahb 31 - const: csi0 32 - const: csi0_phy 33 - const: csi0_pix 34 - const: csi0_rdi 35 - const: csi1_ahb 36 - const: csi1 37 - const: csi1_phy 38 - const: csi1_pix 39 - const: csi1_rdi 40 - const: ahb 41 - const: vfe0 42 - const: csi_vfe0 43 - const: vfe_ahb 44 - const: vfe_axi 45 46 interrupts: 47 minItems: 6 48 maxItems: 6 49 50 interrupt-names: 51 items: 52 - const: csiphy0 53 - const: csiphy1 54 - const: csid0 55 - const: csid1 56 - const: ispif 57 - const: vfe0 58 59 iommus: 60 maxItems: 1 61 62 power-domains: 63 items: 64 - description: VFE GDSC - Video Front End, Global Distributed Switch Controller. 65 66 ports: 67 $ref: /schemas/graph.yaml#/properties/ports 68 69 description: 70 CSI input ports. 71 72 properties: 73 port@0: 74 $ref: /schemas/graph.yaml#/$defs/port-base 75 unevaluatedProperties: false 76 description: 77 Input port for receiving CSI data. 78 79 properties: 80 endpoint: 81 $ref: video-interfaces.yaml# 82 unevaluatedProperties: false 83 84 properties: 85 data-lanes: 86 description: 87 An array of physical data lanes indexes. 88 Position of an entry determines the logical 89 lane number, while the value of an entry 90 indicates physical lane index. Lane swapping 91 is supported. Physical lane indexes; 92 0, 2, 3, 4. 93 minItems: 1 94 maxItems: 4 95 96 bus-type: 97 enum: 98 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 99 100 required: 101 - data-lanes 102 103 port@1: 104 $ref: /schemas/graph.yaml#/$defs/port-base 105 unevaluatedProperties: false 106 description: 107 Input port for receiving CSI data. 108 109 properties: 110 endpoint: 111 $ref: video-interfaces.yaml# 112 unevaluatedProperties: false 113 114 properties: 115 data-lanes: 116 minItems: 1 117 maxItems: 4 118 119 bus-type: 120 enum: 121 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY 122 123 required: 124 - data-lanes 125 126 reg: 127 minItems: 9 128 maxItems: 9 129 130 reg-names: 131 items: 132 - const: csiphy0 133 - const: csiphy0_clk_mux 134 - const: csiphy1 135 - const: csiphy1_clk_mux 136 - const: csid0 137 - const: csid1 138 - const: ispif 139 - const: csi_clk_mux 140 - const: vfe0 141 142 vdda-supply: 143 description: 144 Definition of the regulator used as analog power supply. 145 146required: 147 - clock-names 148 - clocks 149 - compatible 150 - interrupt-names 151 - interrupts 152 - iommus 153 - power-domains 154 - reg 155 - reg-names 156 - vdda-supply 157 158additionalProperties: false 159 160examples: 161 - | 162 #include <dt-bindings/interrupt-controller/arm-gic.h> 163 #include <dt-bindings/clock/qcom,gcc-msm8916.h> 164 165 camss: camss@1b0ac00 { 166 compatible = "qcom,msm8916-camss"; 167 168 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 169 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 170 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 171 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 172 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 173 <&gcc GCC_CAMSS_CSI0_CLK>, 174 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 175 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 176 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 177 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 178 <&gcc GCC_CAMSS_CSI1_CLK>, 179 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 180 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 181 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 182 <&gcc GCC_CAMSS_AHB_CLK>, 183 <&gcc GCC_CAMSS_VFE0_CLK>, 184 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 185 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 186 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 187 188 clock-names = "top_ahb", 189 "ispif_ahb", 190 "csiphy0_timer", 191 "csiphy1_timer", 192 "csi0_ahb", 193 "csi0", 194 "csi0_phy", 195 "csi0_pix", 196 "csi0_rdi", 197 "csi1_ahb", 198 "csi1", 199 "csi1_phy", 200 "csi1_pix", 201 "csi1_rdi", 202 "ahb", 203 "vfe0", 204 "csi_vfe0", 205 "vfe_ahb", 206 "vfe_axi"; 207 208 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 209 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 210 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 211 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 212 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 213 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 214 215 interrupt-names = "csiphy0", 216 "csiphy1", 217 "csid0", 218 "csid1", 219 "ispif", 220 "vfe0"; 221 222 iommus = <&apps_iommu 3>; 223 224 power-domains = <&gcc VFE_GDSC>; 225 226 reg = <0x01b0ac00 0x200>, 227 <0x01b00030 0x4>, 228 <0x01b0b000 0x200>, 229 <0x01b00038 0x4>, 230 <0x01b08000 0x100>, 231 <0x01b08400 0x100>, 232 <0x01b0a000 0x500>, 233 <0x01b00020 0x10>, 234 <0x01b10000 0x1000>; 235 236 reg-names = "csiphy0", 237 "csiphy0_clk_mux", 238 "csiphy1", 239 "csiphy1_clk_mux", 240 "csid0", 241 "csid1", 242 "ispif", 243 "csi_clk_mux", 244 "vfe0"; 245 246 vdda-supply = <®_2v8>; 247 248 ports { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 }; 252 253 }; 254