xref: /linux/Documentation/devicetree/bindings/fsi/aspeed,ast2600-fsi-master.yaml (revision c771600c6af14749609b49565ffb4cac2959710d)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fsi/aspeed,ast2600-fsi-master.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed FSI master

maintainers:
  - Eddie James <eajames@linux.ibm.com>

description:
  The AST2600 and later contain two identical FSI masters. They share a
  clock and have a separate interrupt line and output pins.

properties:
  compatible:
    enum:
      - aspeed,ast2600-fsi-master
      - aspeed,ast2700-fsi-master

  clocks:
    maxItems: 1

  cfam-reset-gpios:
    maxItems: 1
    description:
      Output GPIO pin for CFAM reset

  fsi-routing-gpios:
    maxItems: 1
    description:
      Output GPIO pin for setting the FSI mux (internal or cabled)

  fsi-mux-gpios:
    maxItems: 1
    description:
      Input GPIO pin for detecting the desired FSI mux state

  interrupts:
    maxItems: 1

if:
  properties:
    compatible:
      contains:
        enum:
          - aspeed,ast2600-fsi-master
then:
  properties:
    reg:
      maxItems: 1
else:
  properties:
    reg:
      minItems: 1
      items:
        - description: OPB control registers
        - description: FSI controller registers
        - description: FSI link address space
    reg-names:
      items:
        - const: opb
        - const: ctrl
        - const: fsi

required:
  - compatible
  - reg
  - clocks
  - interrupts

allOf:
  - $ref: fsi-controller.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/ast2600-clock.h>
    #include <dt-bindings/gpio/aspeed-gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    fsi-master@1e79b000 {
        compatible = "aspeed,ast2600-fsi-master";
        reg = <0x1e79b000 0x94>;
        #address-cells = <2>;
        #size-cells = <0>;
        interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fsi1_default>;
        clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
        fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
        fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>;
        cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>;

        cfam@0,0 {
            reg = <0 0>;
            #address-cells = <1>;
            #size-cells = <1>;
            chip-id = <0>;
        };
    };
  - |
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        fsi-master@21800000 {
            compatible = "aspeed,ast2700-fsi-master";
            reg = <0x0 0x21800000 0x0 0x100>,
                  <0x0 0x21000000 0x0 0x1000>,
                  <0x0 0x20000000 0x0 0x1000000>;
            reg-names = "opb", "ctrl", "fsi";
            #interrupt-cells = <1>;
            interrupt-controller;
            interrupts-extended = <&intc 6>;
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_fsi0_default>;
            clocks = <&syscon 40>;
        };
    };