1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX System Controller Firmware (SCFW) 8 9maintainers: 10 - Dong Aisheng <aisheng.dong@nxp.com> 11 12description: 13 The System Controller Firmware (SCFW) is a low-level system function 14 which runs on a dedicated Cortex-M core to provide power, clock, and 15 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 16 (QM, QP), and i.MX8QX (QXP, DX). 17 The AP communicates with the SC using a multi-ported MU module found 18 in the LSIO subsystem. The current definition of this MU module provides 19 5 remote AP connections to the SC to support up to 5 execution environments 20 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 21 with the LSIO DSC IP bus. The SC firmware will communicate with this MU 22 using the MSI bus. 23 24properties: 25 compatible: 26 const: fsl,imx-scu 27 28 clock-controller: 29 description: 30 Clock controller node that provides the clocks controlled by the SCU 31 $ref: /schemas/clock/fsl,scu-clk.yaml 32 33 gpio: 34 description: 35 Control the GPIO PINs on SCU domain over the firmware APIs 36 $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml 37 38 ocotp: 39 description: 40 OCOTP controller node provided by the SCU 41 $ref: /schemas/nvmem/fsl,scu-ocotp.yaml 42 43 keys: 44 description: 45 Keys provided by the SCU 46 $ref: /schemas/input/fsl,scu-key.yaml 47 48 reset-controller: 49 type: object 50 properties: 51 compatible: 52 const: fsl,imx-scu-reset 53 '#reset-cells': 54 const: 1 55 required: 56 - compatible 57 - '#reset-cells' 58 additionalProperties: false 59 60 mboxes: 61 description: 62 A list of phandles of TX MU channels followed by a list of phandles of 63 RX MU channels. The list may include at the end one more optional MU 64 channel for general interrupt. The number of expected tx and rx 65 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu" 66 compatible, 4 TX and 4 RX channels otherwise. All MU channels must be 67 within the same MU instance. Cross instances are not allowed. The MU 68 instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users 69 need to ensure that one is used that does not conflict with other 70 execution environments such as ATF. 71 oneOf: 72 - items: 73 - description: TX0 MU channel 74 - description: RX0 MU channel 75 - items: 76 - description: TX0 MU channel 77 - description: RX0 MU channel 78 - description: optional MU channel for general interrupt 79 - items: 80 - description: TX0 MU channel 81 - description: TX1 MU channel 82 - description: TX2 MU channel 83 - description: TX3 MU channel 84 - description: RX0 MU channel 85 - description: RX1 MU channel 86 - description: RX2 MU channel 87 - description: RX3 MU channel 88 - items: 89 - description: TX0 MU channel 90 - description: TX1 MU channel 91 - description: TX2 MU channel 92 - description: TX3 MU channel 93 - description: RX0 MU channel 94 - description: RX1 MU channel 95 - description: RX2 MU channel 96 - description: RX3 MU channel 97 - description: optional MU channel for general interrupt 98 99 mbox-names: 100 oneOf: 101 - items: 102 - const: tx0 103 - const: rx0 104 - items: 105 - const: tx0 106 - const: rx0 107 - const: gip3 108 - items: 109 - const: tx0 110 - const: tx1 111 - const: tx2 112 - const: tx3 113 - const: rx0 114 - const: rx1 115 - const: rx2 116 - const: rx3 117 - items: 118 - const: tx0 119 - const: tx1 120 - const: tx2 121 - const: tx3 122 - const: rx0 123 - const: rx1 124 - const: rx2 125 - const: rx3 126 - const: gip3 127 128 pinctrl: 129 description: 130 Pin controller provided by the SCU 131 $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml 132 133 power-controller: 134 description: 135 Power domains controller node that provides the power domains 136 controlled by the SCU 137 $ref: /schemas/power/fsl,scu-pd.yaml 138 139 rtc: 140 description: 141 RTC controller provided by the SCU 142 $ref: /schemas/rtc/fsl,scu-rtc.yaml 143 144 thermal-sensor: 145 description: 146 Thermal sensor provided by the SCU 147 $ref: /schemas/thermal/fsl,scu-thermal.yaml 148 149 watchdog: 150 description: 151 Watchdog controller provided by the SCU 152 $ref: /schemas/watchdog/fsl,scu-wdt.yaml 153 154required: 155 - compatible 156 - mbox-names 157 - mboxes 158 159additionalProperties: false 160 161examples: 162 - | 163 #include <dt-bindings/firmware/imx/rsrc.h> 164 #include <dt-bindings/input/input.h> 165 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 166 167 firmware { 168 system-controller { 169 compatible = "fsl,imx-scu"; 170 mbox-names = "tx0", "tx1", "tx2", "tx3", 171 "rx0", "rx1", "rx2", "rx3", 172 "gip3"; 173 mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3 174 &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3 175 &lsio_mu1 3 3>; 176 177 clock-controller { 178 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 179 #clock-cells = <2>; 180 }; 181 182 pinctrl { 183 compatible = "fsl,imx8qxp-iomuxc"; 184 185 pinctrl_lpuart0: lpuart0grp { 186 fsl,pins = < 187 IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 188 IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 189 >; 190 }; 191 }; 192 193 ocotp { 194 compatible = "fsl,imx8qxp-scu-ocotp"; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 198 fec_mac0: mac@2c4 { 199 reg = <0x2c4 6>; 200 }; 201 }; 202 203 power-controller { 204 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 205 #power-domain-cells = <1>; 206 }; 207 208 rtc { 209 compatible = "fsl,imx8qxp-sc-rtc"; 210 }; 211 212 keys { 213 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 214 linux,keycodes = <KEY_POWER>; 215 }; 216 217 watchdog { 218 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 219 timeout-sec = <60>; 220 }; 221 222 thermal-sensor { 223 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 224 #thermal-sensor-cells = <1>; 225 }; 226 }; 227 }; 228