1*91d457ddSAndrew Bresticker* IMG Multi-threaded DMA Controller (MDC) 2*91d457ddSAndrew Bresticker 3*91d457ddSAndrew BrestickerRequired properties: 4*91d457ddSAndrew Bresticker- compatible: Must be "img,pistachio-mdc-dma". 5*91d457ddSAndrew Bresticker- reg: Must contain the base address and length of the MDC registers. 6*91d457ddSAndrew Bresticker- interrupts: Must contain all the per-channel DMA interrupts. 7*91d457ddSAndrew Bresticker- clocks: Must contain an entry for each entry in clock-names. 8*91d457ddSAndrew Bresticker See ../clock/clock-bindings.txt for details. 9*91d457ddSAndrew Bresticker- clock-names: Must include the following entries: 10*91d457ddSAndrew Bresticker - sys: MDC system interface clock. 11*91d457ddSAndrew Bresticker- img,cr-periph: Must contain a phandle to the peripheral control syscon 12*91d457ddSAndrew Bresticker node which contains the DMA request to channel mapping registers. 13*91d457ddSAndrew Bresticker- img,max-burst-multiplier: Must be the maximum supported burst size multiplier. 14*91d457ddSAndrew Bresticker The maximum burst size is this value multiplied by the hardware-reported bus 15*91d457ddSAndrew Bresticker width. 16*91d457ddSAndrew Bresticker- #dma-cells: Must be 3: 17*91d457ddSAndrew Bresticker - The first cell is the peripheral's DMA request line. 18*91d457ddSAndrew Bresticker - The second cell is a bitmap specifying to which channels the DMA request 19*91d457ddSAndrew Bresticker line may be mapped (i.e. bit N set indicates channel N is usable). 20*91d457ddSAndrew Bresticker - The third cell is the thread ID to be used by the channel. 21*91d457ddSAndrew Bresticker 22*91d457ddSAndrew BrestickerOptional properties: 23*91d457ddSAndrew Bresticker- dma-channels: Number of supported DMA channels, up to 32. If not specified 24*91d457ddSAndrew Bresticker the number reported by the hardware is used. 25*91d457ddSAndrew Bresticker 26*91d457ddSAndrew BrestickerExample: 27*91d457ddSAndrew Bresticker 28*91d457ddSAndrew Brestickermdc: dma-controller@18143000 { 29*91d457ddSAndrew Bresticker compatible = "img,pistachio-mdc-dma"; 30*91d457ddSAndrew Bresticker reg = <0x18143000 0x1000>; 31*91d457ddSAndrew Bresticker interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>, 32*91d457ddSAndrew Bresticker <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>, 33*91d457ddSAndrew Bresticker <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>, 34*91d457ddSAndrew Bresticker <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>, 35*91d457ddSAndrew Bresticker <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>, 36*91d457ddSAndrew Bresticker <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>, 37*91d457ddSAndrew Bresticker <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>, 38*91d457ddSAndrew Bresticker <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>, 39*91d457ddSAndrew Bresticker <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>, 40*91d457ddSAndrew Bresticker <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>, 41*91d457ddSAndrew Bresticker <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>, 42*91d457ddSAndrew Bresticker <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>; 43*91d457ddSAndrew Bresticker clocks = <&system_clk>; 44*91d457ddSAndrew Bresticker clock-names = "sys"; 45*91d457ddSAndrew Bresticker 46*91d457ddSAndrew Bresticker img,max-burst-multiplier = <16>; 47*91d457ddSAndrew Bresticker img,cr-periph = <&cr_periph>; 48*91d457ddSAndrew Bresticker 49*91d457ddSAndrew Bresticker #dma-cells = <3>; 50*91d457ddSAndrew Bresticker}; 51*91d457ddSAndrew Bresticker 52*91d457ddSAndrew Brestickerspi@18100f00 { 53*91d457ddSAndrew Bresticker ... 54*91d457ddSAndrew Bresticker dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; 55*91d457ddSAndrew Bresticker dma-names = "tx", "rx"; 56*91d457ddSAndrew Bresticker ... 57*91d457ddSAndrew Bresticker}; 58