1*a1f8ebe5SAlexey BrodkinARC PGU 2*a1f8ebe5SAlexey Brodkin 3*a1f8ebe5SAlexey BrodkinThis is a display controller found on several development boards produced 4*a1f8ebe5SAlexey Brodkinby Synopsys. The ARC PGU is an RGB streamer that reads the data from a 5*a1f8ebe5SAlexey Brodkinframebuffer and sends it to a single digital encoder (usually HDMI). 6*a1f8ebe5SAlexey Brodkin 7*a1f8ebe5SAlexey BrodkinRequired properties: 8*a1f8ebe5SAlexey Brodkin - compatible: "snps,arcpgu" 9*a1f8ebe5SAlexey Brodkin - reg: Physical base address and length of the controller's registers. 10*a1f8ebe5SAlexey Brodkin - clocks: A list of phandle + clock-specifier pairs, one for each 11*a1f8ebe5SAlexey Brodkin entry in 'clock-names'. 12*a1f8ebe5SAlexey Brodkin - clock-names: A list of clock names. For ARC PGU it should contain: 13*a1f8ebe5SAlexey Brodkin - "pxlclk" for the clock feeding the output PLL of the controller. 14*a1f8ebe5SAlexey Brodkin 15*a1f8ebe5SAlexey BrodkinRequired sub-nodes: 16*a1f8ebe5SAlexey Brodkin - port: The PGU connection to an encoder chip. 17*a1f8ebe5SAlexey Brodkin 18*a1f8ebe5SAlexey BrodkinExample: 19*a1f8ebe5SAlexey Brodkin 20*a1f8ebe5SAlexey Brodkin/ { 21*a1f8ebe5SAlexey Brodkin ... 22*a1f8ebe5SAlexey Brodkin 23*a1f8ebe5SAlexey Brodkin pgu@XXXXXXXX { 24*a1f8ebe5SAlexey Brodkin compatible = "snps,arcpgu"; 25*a1f8ebe5SAlexey Brodkin reg = <0xXXXXXXXX 0x400>; 26*a1f8ebe5SAlexey Brodkin clocks = <&clock_node>; 27*a1f8ebe5SAlexey Brodkin clock-names = "pxlclk"; 28*a1f8ebe5SAlexey Brodkin 29*a1f8ebe5SAlexey Brodkin port { 30*a1f8ebe5SAlexey Brodkin pgu_output: endpoint { 31*a1f8ebe5SAlexey Brodkin remote-endpoint = <&hdmi_enc_input>; 32*a1f8ebe5SAlexey Brodkin }; 33*a1f8ebe5SAlexey Brodkin }; 34*a1f8ebe5SAlexey Brodkin }; 35*a1f8ebe5SAlexey Brodkin}; 36