1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MSM Display Port Controller 8 9maintainers: 10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 11 - Abhinav Kumar <quic_abhinavk@quicinc.com> 12 13description: | 14 Device tree bindings for DisplayPort host controller for MSM targets 15 that are compatible with VESA DisplayPort interface specification. 16 17properties: 18 compatible: 19 oneOf: 20 - enum: 21 - qcom,sa8775p-dp 22 - qcom,sc7180-dp 23 - qcom,sc7280-dp 24 - qcom,sc7280-edp 25 - qcom,sc8180x-dp 26 - qcom,sc8180x-edp 27 - qcom,sc8280xp-dp 28 - qcom,sc8280xp-edp 29 - qcom,sdm845-dp 30 - qcom,sm8350-dp 31 - qcom,sm8650-dp 32 - items: 33 - enum: 34 - qcom,sar2130p-dp 35 - qcom,sm6350-dp 36 - qcom,sm8150-dp 37 - qcom,sm8250-dp 38 - qcom,sm8450-dp 39 - qcom,sm8550-dp 40 - const: qcom,sm8350-dp 41 42 reg: 43 minItems: 4 44 items: 45 - description: ahb register block 46 - description: aux register block 47 - description: link register block 48 - description: p0 register block 49 - description: p1 register block 50 51 interrupts: 52 maxItems: 1 53 54 clocks: 55 items: 56 - description: AHB clock to enable register access 57 - description: Display Port AUX clock 58 - description: Display Port Link clock 59 - description: Link interface clock between DP and PHY 60 - description: Display Port Pixel clock 61 62 clock-names: 63 items: 64 - const: core_iface 65 - const: core_aux 66 - const: ctrl_link 67 - const: ctrl_link_iface 68 - const: stream_pixel 69 70 assigned-clocks: 71 items: 72 - description: link clock source 73 - description: pixel clock source 74 75 assigned-clock-parents: 76 items: 77 - description: phy 0 parent 78 - description: phy 1 parent 79 80 phys: 81 maxItems: 1 82 83 phy-names: 84 items: 85 - const: dp 86 87 operating-points-v2: true 88 89 opp-table: 90 type: object 91 92 power-domains: 93 maxItems: 1 94 95 aux-bus: 96 $ref: /schemas/display/dp-aux-bus.yaml# 97 98 data-lanes: 99 $ref: /schemas/types.yaml#/definitions/uint32-array 100 deprecated: true 101 minItems: 1 102 maxItems: 4 103 items: 104 maximum: 3 105 106 "#sound-dai-cells": 107 const: 0 108 109 vdda-0p9-supply: 110 deprecated: true 111 vdda-1p2-supply: 112 deprecated: true 113 114 ports: 115 $ref: /schemas/graph.yaml#/properties/ports 116 properties: 117 port@0: 118 $ref: /schemas/graph.yaml#/properties/port 119 description: Input endpoint of the controller 120 121 port@1: 122 $ref: /schemas/graph.yaml#/$defs/port-base 123 unevaluatedProperties: false 124 description: Output endpoint of the controller 125 properties: 126 endpoint: 127 $ref: /schemas/media/video-interfaces.yaml# 128 unevaluatedProperties: false 129 properties: 130 data-lanes: 131 minItems: 1 132 maxItems: 4 133 items: 134 enum: [ 0, 1, 2, 3 ] 135 136 link-frequencies: 137 minItems: 1 138 maxItems: 4 139 items: 140 enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ] 141 142 required: 143 - port@0 144 - port@1 145 146required: 147 - compatible 148 - reg 149 - interrupts 150 - clocks 151 - clock-names 152 - phys 153 - phy-names 154 - power-domains 155 - ports 156 157allOf: 158 # AUX BUS does not exist on DP controllers 159 # Audio output also is present only on DP output 160 # p1 regions is present on DP, but not on eDP 161 - if: 162 properties: 163 compatible: 164 contains: 165 enum: 166 - qcom,sc7280-edp 167 - qcom,sc8180x-edp 168 - qcom,sc8280xp-edp 169 then: 170 properties: 171 "#sound-dai-cells": false 172 else: 173 properties: 174 aux-bus: false 175 reg: 176 minItems: 5 177 required: 178 - "#sound-dai-cells" 179 180additionalProperties: false 181 182examples: 183 - | 184 #include <dt-bindings/interrupt-controller/arm-gic.h> 185 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 186 #include <dt-bindings/power/qcom-rpmpd.h> 187 188 displayport-controller@ae90000 { 189 compatible = "qcom,sc7180-dp"; 190 reg = <0xae90000 0x200>, 191 <0xae90200 0x200>, 192 <0xae90400 0xc00>, 193 <0xae91000 0x400>, 194 <0xae91400 0x400>; 195 interrupt-parent = <&mdss>; 196 interrupts = <12>; 197 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 198 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 199 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 200 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 201 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 202 clock-names = "core_iface", "core_aux", 203 "ctrl_link", 204 "ctrl_link_iface", "stream_pixel"; 205 206 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 207 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 208 209 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 210 211 phys = <&dp_phy>; 212 phy-names = "dp"; 213 214 #sound-dai-cells = <0>; 215 216 power-domains = <&rpmhpd SC7180_CX>; 217 218 ports { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 222 port@0 { 223 reg = <0>; 224 endpoint { 225 remote-endpoint = <&dpu_intf0_out>; 226 }; 227 }; 228 229 port@1 { 230 reg = <1>; 231 endpoint { 232 remote-endpoint = <&typec>; 233 data-lanes = <0 1>; 234 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; 235 }; 236 }; 237 }; 238 }; 239... 240