1*5437d667SJohannes Zink# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5437d667SJohannes Zink%YAML 1.2 3*5437d667SJohannes Zink--- 4*5437d667SJohannes Zink$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml# 5*5437d667SJohannes Zink$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5437d667SJohannes Zink 7*5437d667SJohannes Zinktitle: LVDS Data Mapping 8*5437d667SJohannes Zink 9*5437d667SJohannes Zinkmaintainers: 10*5437d667SJohannes Zink - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11*5437d667SJohannes Zink - Thierry Reding <thierry.reding@gmail.com> 12*5437d667SJohannes Zink 13*5437d667SJohannes Zinkdescription: | 14*5437d667SJohannes Zink LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple 15*5437d667SJohannes Zink incompatible data link layers have been used over time to transmit image data 16*5437d667SJohannes Zink to LVDS devices. This bindings supports devices compatible with the following 17*5437d667SJohannes Zink specifications. 18*5437d667SJohannes Zink 19*5437d667SJohannes Zink [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February 20*5437d667SJohannes Zink 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA) 21*5437d667SJohannes Zink [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National 22*5437d667SJohannes Zink Semiconductor 23*5437d667SJohannes Zink [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video 24*5437d667SJohannes Zink Electronics Standards Association (VESA) 25*5437d667SJohannes Zink 26*5437d667SJohannes Zink Device compatible with those specifications have been marketed under the 27*5437d667SJohannes Zink FPD-Link and FlatLink brands. 28*5437d667SJohannes Zink 29*5437d667SJohannes Zink This bindings also supports 30-bit data mapping compatible with JEIDA and 30*5437d667SJohannes Zink VESA. 31*5437d667SJohannes Zink 32*5437d667SJohannes Zinkproperties: 33*5437d667SJohannes Zink data-mapping: 34*5437d667SJohannes Zink enum: 35*5437d667SJohannes Zink - jeida-18 36*5437d667SJohannes Zink - jeida-24 37*5437d667SJohannes Zink - jeida-30 38*5437d667SJohannes Zink - vesa-24 39*5437d667SJohannes Zink - vesa-30 40*5437d667SJohannes Zink description: | 41*5437d667SJohannes Zink The color signals mapping order. 42*5437d667SJohannes Zink 43*5437d667SJohannes Zink LVDS data mappings are defined as follows. 44*5437d667SJohannes Zink 45*5437d667SJohannes Zink - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and 46*5437d667SJohannes Zink [VESA] specifications. Data are transferred as follows on 3 LVDS lanes. 47*5437d667SJohannes Zink 48*5437d667SJohannes Zink Slot 0 1 2 3 4 5 6 49*5437d667SJohannes Zink ________________ _________________ 50*5437d667SJohannes Zink Clock \_______________________/ 51*5437d667SJohannes Zink ______ ______ ______ ______ ______ ______ ______ 52*5437d667SJohannes Zink DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 53*5437d667SJohannes Zink DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 54*5437d667SJohannes Zink DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 55*5437d667SJohannes Zink 56*5437d667SJohannes Zink - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI] 57*5437d667SJohannes Zink specifications. Data are transferred as follows on 4 LVDS lanes. 58*5437d667SJohannes Zink 59*5437d667SJohannes Zink Slot 0 1 2 3 4 5 6 60*5437d667SJohannes Zink ________________ _________________ 61*5437d667SJohannes Zink Clock \_______________________/ 62*5437d667SJohannes Zink ______ ______ ______ ______ ______ ______ ______ 63*5437d667SJohannes Zink DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__>< 64*5437d667SJohannes Zink DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__>< 65*5437d667SJohannes Zink DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__>< 66*5437d667SJohannes Zink DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 67*5437d667SJohannes Zink 68*5437d667SJohannes Zink - "jeida-30" - 30-bit data mapping compatible with JEIDA and VESA. Data 69*5437d667SJohannes Zink are transferred as follows on 5 LVDS lanes. 70*5437d667SJohannes Zink 71*5437d667SJohannes Zink Slot 0 1 2 3 4 5 6 72*5437d667SJohannes Zink ________________ _________________ 73*5437d667SJohannes Zink Clock \_______________________/ 74*5437d667SJohannes Zink ______ ______ ______ ______ ______ ______ ______ 75*5437d667SJohannes Zink DATA0 ><__G4__><__R9__><__R8__><__R7__><__R6__><__R5__><__R4__>< 76*5437d667SJohannes Zink DATA1 ><__B5__><__B4__><__G9__><__G8__><__G7__><__G6__><__G5__>< 77*5437d667SJohannes Zink DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B9__><__B8__><__B7__><__B6__>< 78*5437d667SJohannes Zink DATA3 ><_CTL3_><__B3__><__B2__><__G3__><__G2__><__R3__><__R2__>< 79*5437d667SJohannes Zink DATA4 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__>< 80*5437d667SJohannes Zink 81*5437d667SJohannes Zink - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification. 82*5437d667SJohannes Zink Data are transferred as follows on 4 LVDS lanes. 83*5437d667SJohannes Zink 84*5437d667SJohannes Zink Slot 0 1 2 3 4 5 6 85 ________________ _________________ 86 Clock \_______________________/ 87 ______ ______ ______ ______ ______ ______ ______ 88 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 89 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 90 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 91 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 92 93 - "vesa-30" - 30-bit data mapping compatible with VESA. Data are 94 transferred as follows on 5 LVDS lanes. 95 96 Slot 0 1 2 3 4 5 6 97 ________________ _________________ 98 Clock \_______________________/ 99 ______ ______ ______ ______ ______ ______ ______ 100 DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__>< 101 DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__>< 102 DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__>< 103 DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__>< 104 DATA4 ><_CTL3_><__B9__><__B8__><__G9__><__G8__><__R9__><__R8__>< 105 106 Control signals are mapped as follows. 107 108 CTL0: HSync 109 CTL1: VSync 110 CTL2: Data Enable 111 CTL3: 0 112 113additionalProperties: true 114 115... 116