1*1c0ff333SLiu Ying# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*1c0ff333SLiu Ying%YAML 1.2 3*1c0ff333SLiu Ying--- 4*1c0ff333SLiu Ying$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-fetchunit.yaml# 5*1c0ff333SLiu Ying$schema: http://devicetree.org/meta-schemas/core.yaml# 6*1c0ff333SLiu Ying 7*1c0ff333SLiu Yingtitle: Freescale i.MX8qxp Display Controller Fetch Unit 8*1c0ff333SLiu Ying 9*1c0ff333SLiu Yingdescription: | 10*1c0ff333SLiu Ying The Fetch Unit is the interface between the AXI bus for source buffer access 11*1c0ff333SLiu Ying and the internal pixel processing pipeline, which is 30-bit RGB plus 8-bit 12*1c0ff333SLiu Ying Alpha. 13*1c0ff333SLiu Ying 14*1c0ff333SLiu Ying It is used to generate foreground planes in Display Controllers and source 15*1c0ff333SLiu Ying planes in Blit Engines, and comprises the following built-in functions to 16*1c0ff333SLiu Ying convert a wide range of frame buffer types. 17*1c0ff333SLiu Ying 18*1c0ff333SLiu Ying +---------X-----------------------------------------+ 19*1c0ff333SLiu Ying | | Fetch Unit | 20*1c0ff333SLiu Ying | V | 21*1c0ff333SLiu Ying | +---------+ | 22*1c0ff333SLiu Ying | | | | 23*1c0ff333SLiu Ying | | Decode | Decompression [Decode] | 24*1c0ff333SLiu Ying | | | | 25*1c0ff333SLiu Ying | +---------+ | 26*1c0ff333SLiu Ying | | | 27*1c0ff333SLiu Ying | V | 28*1c0ff333SLiu Ying | +---------+ | 29*1c0ff333SLiu Ying | | Clip & | Clip Window [All] | 30*1c0ff333SLiu Ying | | Overlay | Plane composition [Layer, Warp] | 31*1c0ff333SLiu Ying | | | | 32*1c0ff333SLiu Ying | +---------+ | 33*1c0ff333SLiu Ying | | | 34*1c0ff333SLiu Ying | V | 35*1c0ff333SLiu Ying | +---------+ | 36*1c0ff333SLiu Ying | | Re- | Flip/Rotate/Repl./Drop [All] | 37*1c0ff333SLiu Ying X--> | sample | Perspective/Affine warping [Persp] | 38*1c0ff333SLiu Ying | | | | Arbitrary warping [Warp, Persp] | 39*1c0ff333SLiu Ying | | +---------+ | 40*1c0ff333SLiu Ying | | | | 41*1c0ff333SLiu Ying | | V | 42*1c0ff333SLiu Ying | | +---------+ | 43*1c0ff333SLiu Ying | | | | | 44*1c0ff333SLiu Ying | | | Palette | Color Palette [Layer, Decode] | 45*1c0ff333SLiu Ying | | | | | 46*1c0ff333SLiu Ying | | +---------+ | 47*1c0ff333SLiu Ying | | | | 48*1c0ff333SLiu Ying | | V | 49*1c0ff333SLiu Ying | | +---------+ | 50*1c0ff333SLiu Ying | | | Extract | Raw to RGBA/YUV [All] | 51*1c0ff333SLiu Ying | | | & | Bit width expansion [All] | 52*1c0ff333SLiu Ying | | | Expand | | 53*1c0ff333SLiu Ying | | +---------+ | 54*1c0ff333SLiu Ying | | | | 55*1c0ff333SLiu Ying | | V | 56*1c0ff333SLiu Ying | | +---------+ | 57*1c0ff333SLiu Ying | | | | Planar to packed | 58*1c0ff333SLiu Ying | |->| Combine | [Decode, Warp, Persp] | 59*1c0ff333SLiu Ying | | | | | 60*1c0ff333SLiu Ying | | +---------+ | 61*1c0ff333SLiu Ying | | | | 62*1c0ff333SLiu Ying | | V | 63*1c0ff333SLiu Ying | | +---------+ | 64*1c0ff333SLiu Ying | | | | YUV422 to YUV444 | 65*1c0ff333SLiu Ying | | | Chroma | [Decode, Persp] | 66*1c0ff333SLiu Ying | | | | | 67*1c0ff333SLiu Ying | | +---------+ | 68*1c0ff333SLiu Ying | | | | 69*1c0ff333SLiu Ying | | V | 70*1c0ff333SLiu Ying | | +---------+ | 71*1c0ff333SLiu Ying | | | | YUV to RGB | 72*1c0ff333SLiu Ying | | | Color | [Warp, Persp, Decode, Layer] | 73*1c0ff333SLiu Ying | | | | | 74*1c0ff333SLiu Ying | | +---------+ | 75*1c0ff333SLiu Ying | | | | 76*1c0ff333SLiu Ying | | V | 77*1c0ff333SLiu Ying | | +---------+ | 78*1c0ff333SLiu Ying | | | | Gamma removal | 79*1c0ff333SLiu Ying | | | Gamma | [Warp, Persp, Decode, Layer] | 80*1c0ff333SLiu Ying | | | | | 81*1c0ff333SLiu Ying | | +---------+ | 82*1c0ff333SLiu Ying | | | | 83*1c0ff333SLiu Ying | | V | 84*1c0ff333SLiu Ying | | +---------+ | 85*1c0ff333SLiu Ying | | | | Alpla multiply, RGB pre-multiply | 86*1c0ff333SLiu Ying | ->| Multiply| [Warp, Persp, Decode, Layer] | 87*1c0ff333SLiu Ying | | | | 88*1c0ff333SLiu Ying | --------- | 89*1c0ff333SLiu Ying | | | 90*1c0ff333SLiu Ying | V | 91*1c0ff333SLiu Ying | +---------+ | 92*1c0ff333SLiu Ying | | | Bilinear filter | 93*1c0ff333SLiu Ying | | Filter | [Warp, Persp] | 94*1c0ff333SLiu Ying | | | | 95*1c0ff333SLiu Ying | +---------+ | 96*1c0ff333SLiu Ying | | | 97*1c0ff333SLiu Ying | V | 98*1c0ff333SLiu Ying +---------X-----------------------------------------+ 99*1c0ff333SLiu Ying 100*1c0ff333SLiu Ying Note that different derivatives of the Fetch Unit exist. Each implements a 101*1c0ff333SLiu Ying specific subset only of the pipeline stages shown above. Restrictions for the 102*1c0ff333SLiu Ying units are specified in [square brackets]. 103*1c0ff333SLiu Ying 104*1c0ff333SLiu Yingmaintainers: 105*1c0ff333SLiu Ying - Liu Ying <victor.liu@nxp.com> 106*1c0ff333SLiu Ying 107*1c0ff333SLiu Yingproperties: 108*1c0ff333SLiu Ying compatible: 109*1c0ff333SLiu Ying enum: 110*1c0ff333SLiu Ying - fsl,imx8qxp-dc-fetchdecode 111*1c0ff333SLiu Ying - fsl,imx8qxp-dc-fetcheco 112*1c0ff333SLiu Ying - fsl,imx8qxp-dc-fetchlayer 113*1c0ff333SLiu Ying - fsl,imx8qxp-dc-fetchwarp 114*1c0ff333SLiu Ying 115*1c0ff333SLiu Ying reg: 116*1c0ff333SLiu Ying maxItems: 2 117*1c0ff333SLiu Ying 118*1c0ff333SLiu Ying reg-names: 119*1c0ff333SLiu Ying items: 120*1c0ff333SLiu Ying - const: pec 121*1c0ff333SLiu Ying - const: cfg 122*1c0ff333SLiu Ying 123*1c0ff333SLiu Ying fsl,prg: 124*1c0ff333SLiu Ying $ref: /schemas/types.yaml#/definitions/phandle 125*1c0ff333SLiu Ying description: 126*1c0ff333SLiu Ying Optional Prefetch Resolve Gasket associated with the Fetch Unit. 127*1c0ff333SLiu Ying 128*1c0ff333SLiu Yingrequired: 129*1c0ff333SLiu Ying - compatible 130*1c0ff333SLiu Ying - reg 131*1c0ff333SLiu Ying - reg-names 132*1c0ff333SLiu Ying 133*1c0ff333SLiu YingadditionalProperties: false 134*1c0ff333SLiu Ying 135*1c0ff333SLiu Yingexamples: 136*1c0ff333SLiu Ying - | 137*1c0ff333SLiu Ying fetchlayer@56180ac0 { 138*1c0ff333SLiu Ying compatible = "fsl,imx8qxp-dc-fetchlayer"; 139*1c0ff333SLiu Ying reg = <0x56180ac0 0xc>, <0x56188400 0x404>; 140*1c0ff333SLiu Ying reg-names = "pec", "cfg"; 141*1c0ff333SLiu Ying }; 142