1# SPDX-License-Identifier: GPL-2.0 2# Copyright (C) 2008-2011 Freescale Semiconductor Inc. 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: Freescale SEC 4 9 10maintainers: 11 - '"Horia Geantă" <horia.geanta@nxp.com>' 12 - Pankaj Gupta <pankaj.gupta@nxp.com> 13 - Gaurav Jain <gaurav.jain@nxp.com> 14 15description: | 16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator 17 Accelerator and Assurance Module (CAAM). 18 19 SEC 4 h/w can process requests from 2 types of sources. 20 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). 21 2. Job Rings (HW interface between cores & SEC 4 registers). 22 23 High Speed Data Path Configuration: 24 25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts 26 such as the P4080. The number of simultaneous dequeues the QI can make is 27 equal to the number of Descriptor Controller (DECO) engines in a particular 28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus 29 dequeue from 5 subportals simultaneously. 30 31 Job Ring Data Path Configuration: 32 33 Each JR is located on a separate 4k page, they may (or may not) be made visible 34 in the memory partition devoted to a particular core. The P4080 has 4 JRs, so 35 up to 4 JRs can be configured; and all 4 JRs process requests in parallel. 36 37properties: 38 compatible: 39 oneOf: 40 - items: 41 - enum: 42 - fsl,sec-v5.4 43 - fsl,sec-v6.0 44 - const: fsl,sec-v5.0 45 - const: fsl,sec-v4.0 46 - items: 47 - enum: 48 - fsl,imx6ul-caam 49 - fsl,sec-v5.0 50 - const: fsl,sec-v4.0 51 - const: fsl,sec-v4.0 52 53 reg: 54 maxItems: 1 55 56 ranges: 57 maxItems: 1 58 59 '#address-cells': 60 enum: [1, 2] 61 62 '#size-cells': 63 enum: [1, 2] 64 65 clocks: 66 minItems: 1 67 maxItems: 4 68 69 clock-names: 70 minItems: 1 71 maxItems: 4 72 items: 73 enum: [mem, aclk, ipg, emi_slow] 74 75 dma-coherent: true 76 77 interrupts: 78 maxItems: 1 79 80 fsl,sec-era: 81 description: Defines the 'ERA' of the SEC device. 82 $ref: /schemas/types.yaml#/definitions/uint32 83 84patternProperties: 85 '^jr@[0-9a-f]+$': 86 type: object 87 additionalProperties: false 88 description: 89 Job Ring (JR) Node. Defines data processing interface to SEC 4 across the 90 peripheral bus for purposes of processing cryptographic descriptors. The 91 specified address range can be made visible to one (or more) cores. The 92 interrupt defined for this node is controlled within the address range of 93 this node. 94 95 properties: 96 compatible: 97 oneOf: 98 - items: 99 - const: fsl,sec-v6.0-job-ring 100 - const: fsl,sec-v5.2-job-ring 101 - const: fsl,sec-v5.0-job-ring 102 - const: fsl,sec-v4.4-job-ring 103 - const: fsl,sec-v4.0-job-ring 104 - items: 105 - const: fsl,sec-v5.4-job-ring 106 - const: fsl,sec-v5.0-job-ring 107 - const: fsl,sec-v4.0-job-ring 108 - items: 109 - const: fsl,sec-v5.0-job-ring 110 - const: fsl,sec-v4.0-job-ring 111 - const: fsl,sec-v4.0-job-ring 112 113 reg: 114 maxItems: 1 115 116 interrupts: 117 maxItems: 1 118 119 fsl,liodn: 120 description: 121 Specifies the LIODN to be used in conjunction with the ppid-to-liodn 122 table that specifies the PPID to LIODN mapping. Needed if the PAMU is 123 used. Value is a 12 bit value where value is a LIODN ID for this JR. 124 This property is normally set by boot firmware. 125 $ref: /schemas/types.yaml#/definitions/uint32-array 126 items: 127 - maximum: 0xfff 128 129 '^rtic@[0-9a-f]+$': 130 type: object 131 additionalProperties: false 132 description: 133 Run Time Integrity Check (RTIC) Node. Defines a register space that 134 contains up to 5 sets of addresses and their lengths (sizes) that will be 135 checked at run time. After an initial hash result is calculated, these 136 addresses are checked by HW to monitor any change. If any memory is 137 modified, a Security Violation is triggered (see SNVS definition). 138 139 properties: 140 compatible: 141 oneOf: 142 - items: 143 - const: fsl,sec-v5.4-rtic 144 - const: fsl,sec-v5.0-rtic 145 - const: fsl,sec-v4.0-rtic 146 - const: fsl,sec-v4.0-rtic 147 148 reg: 149 items: 150 - description: RTIC control and status register space. 151 - description: RTIC recoverable error indication register space. 152 minItems: 1 153 154 ranges: 155 maxItems: 1 156 157 interrupts: 158 maxItems: 1 159 160 '#address-cells': 161 const: 1 162 163 '#size-cells': 164 const: 1 165 166 patternProperties: 167 '^rtic-[a-z]@[0-9a-f]+$': 168 type: object 169 additionalProperties: false 170 description: 171 Run Time Integrity Check (RTIC) Memory Node defines individual RTIC 172 memory regions that are used to perform run-time integrity check of 173 memory areas that should not modified. The node defines a register 174 that contains the memory address & length (combined) and a second 175 register that contains the hash result in big endian format. 176 177 properties: 178 compatible: 179 oneOf: 180 - items: 181 - const: fsl,sec-v5.4-rtic-memory 182 - const: fsl,sec-v5.0-rtic-memory 183 - const: fsl,sec-v4.0-rtic-memory 184 - const: fsl,sec-v4.0-rtic-memory 185 186 reg: 187 items: 188 - description: RTIC memory address 189 - description: RTIC hash result 190 191 fsl,liodn: 192 description: 193 Specifies the LIODN to be used in conjunction with the 194 ppid-to-liodn table that specifies the PPID to LIODN mapping. 195 Needed if the PAMU is used. Value is a 12 bit value where value 196 is a LIODN ID for this JR. This property is normally set by boot 197 firmware. 198 $ref: /schemas/types.yaml#/definitions/uint32-array 199 items: 200 - maximum: 0xfff 201 202 fsl,rtic-region: 203 description: 204 Specifies the HW address (36 bit address) for this region 205 followed by the length of the HW partition to be checked; 206 the address is represented as a 64 bit quantity followed 207 by a 32 bit length. 208 $ref: /schemas/types.yaml#/definitions/uint32-array 209 210required: 211 - compatible 212 - reg 213 - ranges 214 215additionalProperties: false 216 217examples: 218 - | 219 crypto@300000 { 220 compatible = "fsl,sec-v4.0"; 221 #address-cells = <1>; 222 #size-cells = <1>; 223 reg = <0x300000 0x10000>; 224 ranges = <0 0x300000 0x10000>; 225 interrupts = <92 2>; 226 227 jr@1000 { 228 compatible = "fsl,sec-v4.0-job-ring"; 229 reg = <0x1000 0x1000>; 230 interrupts = <88 2>; 231 }; 232 233 jr@2000 { 234 compatible = "fsl,sec-v4.0-job-ring"; 235 reg = <0x2000 0x1000>; 236 interrupts = <89 2>; 237 }; 238 239 jr@3000 { 240 compatible = "fsl,sec-v4.0-job-ring"; 241 reg = <0x3000 0x1000>; 242 interrupts = <90 2>; 243 }; 244 245 jr@4000 { 246 compatible = "fsl,sec-v4.0-job-ring"; 247 reg = <0x4000 0x1000>; 248 interrupts = <91 2>; 249 }; 250 251 rtic@6000 { 252 compatible = "fsl,sec-v4.0-rtic"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 reg = <0x6000 0x100>; 256 ranges = <0x0 0x6100 0xe00>; 257 258 rtic-a@0 { 259 compatible = "fsl,sec-v4.0-rtic-memory"; 260 reg = <0x00 0x20>, <0x100 0x80>; 261 }; 262 263 rtic-b@20 { 264 compatible = "fsl,sec-v4.0-rtic-memory"; 265 reg = <0x20 0x20>, <0x200 0x80>; 266 }; 267 268 rtic-c@40 { 269 compatible = "fsl,sec-v4.0-rtic-memory"; 270 reg = <0x40 0x20>, <0x300 0x80>; 271 }; 272 273 rtic-d@60 { 274 compatible = "fsl,sec-v4.0-rtic-memory"; 275 reg = <0x60 0x20>, <0x500 0x80>; 276 }; 277 }; 278 }; 279... 280