xref: /linux/Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml (revision e78f70bad29c5ae1e1076698b690b15794e9b81e) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Sophgo SG2044 Clock Controller
8
9maintainers:
10  - Inochi Amaoto <inochiama@gmail.com>
11
12description: |
13  The Sophgo SG2044 clock controller requires an external oscillator
14  as input clock.
15
16  All available clocks are defined as preprocessor macros in
17  include/dt-bindings/clock/sophgo,sg2044-clk.h
18
19properties:
20  compatible:
21    const: sophgo,sg2044-clk
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    items:
28      - description: fpll0
29      - description: fpll1
30      - description: fpll2
31      - description: dpll0
32      - description: dpll1
33      - description: dpll2
34      - description: dpll3
35      - description: dpll4
36      - description: dpll5
37      - description: dpll6
38      - description: dpll7
39      - description: mpll0
40      - description: mpll1
41      - description: mpll2
42      - description: mpll3
43      - description: mpll4
44      - description: mpll5
45
46  clock-names:
47    items:
48      - const: fpll0
49      - const: fpll1
50      - const: fpll2
51      - const: dpll0
52      - const: dpll1
53      - const: dpll2
54      - const: dpll3
55      - const: dpll4
56      - const: dpll5
57      - const: dpll6
58      - const: dpll7
59      - const: mpll0
60      - const: mpll1
61      - const: mpll2
62      - const: mpll3
63      - const: mpll4
64      - const: mpll5
65
66  '#clock-cells':
67    const: 1
68
69required:
70  - compatible
71  - reg
72  - clocks
73  - '#clock-cells'
74
75additionalProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/clock/sophgo,sg2044-pll.h>
80
81    clock-controller@50002000 {
82      compatible = "sophgo,sg2044-clk";
83      reg = <0x50002000 0x1000>;
84      #clock-cells = <1>;
85      clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
86               <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
87               <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
88               <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
89               <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
90               <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
91               <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
92               <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
93               <&syscon CLK_MPLL5>;
94      clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
95                    "dpll1", "dpll2", "dpll3", "dpll4",
96                    "dpll5", "dpll6", "dpll7", "mpll0",
97                    "mpll1", "mpll2", "mpll3", "mpll4",
98                    "mpll5";
99    };
100