xref: /linux/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml (revision f7f0adfe64de08803990dc4cbecd2849c04e314a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
8
9maintainers:
10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
12description:
13  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
14  generation and control of clock signals for the IP modules, generation and
15  control of resets, and control over booting, low power consumption and power
16  supply domains.
17
18properties:
19  compatible:
20    enum:
21      - renesas,r9a09g047-cpg # RZ/G3E
22      - renesas,r9a09g057-cpg # RZ/V2H
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    items:
29      - description: AUDIO_EXTAL clock input
30      - description: RTXIN clock input
31      - description: QEXTAL clock input
32
33  clock-names:
34    items:
35      - const: audio_extal
36      - const: rtxin
37      - const: qextal
38
39  '#clock-cells':
40    description: |
41      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
42        and a core clock reference, as defined in
43        <dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
44      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
45        a module number.  The module number is calculated as the CLKON register
46        offset index multiplied by 16, plus the actual bit in the register
47        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
48        calculation is (1 * 16 + 3) = 0x13.
49    const: 2
50
51  '#power-domain-cells':
52    const: 0
53
54  '#reset-cells':
55    description:
56      The single reset specifier cell must be the reset number. The reset number
57      is calculated as the reset register offset index multiplied by 16, plus the
58      actual bit in the register used to reset the specific IP block. For example,
59      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
60    const: 1
61
62required:
63  - compatible
64  - reg
65  - clocks
66  - clock-names
67  - '#clock-cells'
68  - '#power-domain-cells'
69  - '#reset-cells'
70
71additionalProperties: false
72
73examples:
74  - |
75    clock-controller@10420000 {
76        compatible = "renesas,r9a09g057-cpg";
77        reg = <0x10420000 0x10000>;
78        clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
79        clock-names = "audio_extal", "rtxin", "qextal";
80        #clock-cells = <2>;
81        #power-domain-cells = <0>;
82        #reset-cells = <1>;
83    };
84