11e910b2bSTaniya Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 21e910b2bSTaniya Das%YAML 1.2 31e910b2bSTaniya Das--- 41e910b2bSTaniya Das$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# 51e910b2bSTaniya Das$schema: http://devicetree.org/meta-schemas/core.yaml# 61e910b2bSTaniya Das 71e910b2bSTaniya Dastitle: Qualcomm Video Clock & Reset Controller on SM8450 81e910b2bSTaniya Das 91e910b2bSTaniya Dasmaintainers: 101e910b2bSTaniya Das - Taniya Das <quic_tdas@quicinc.com> 11a6a61b97SJagadeesh Kona - Jagadeesh Kona <quic_jkona@quicinc.com> 121e910b2bSTaniya Das 131e910b2bSTaniya Dasdescription: | 141e910b2bSTaniya Das Qualcomm video clock control module provides the clocks, resets and power 151e910b2bSTaniya Das domains on SM8450. 161e910b2bSTaniya Das 17a6a61b97SJagadeesh Kona See also: 18a6a61b97SJagadeesh Kona include/dt-bindings/clock/qcom,sm8450-videocc.h 19a6a61b97SJagadeesh Kona include/dt-bindings/clock/qcom,sm8650-videocc.h 201e910b2bSTaniya Das 211e910b2bSTaniya Dasproperties: 221e910b2bSTaniya Das compatible: 23c7d91f26SJagadeesh Kona enum: 24c7d91f26SJagadeesh Kona - qcom,sm8450-videocc 25c7d91f26SJagadeesh Kona - qcom,sm8550-videocc 26a6a61b97SJagadeesh Kona - qcom,sm8650-videocc 271e910b2bSTaniya Das 281e910b2bSTaniya Das reg: 291e910b2bSTaniya Das maxItems: 1 301e910b2bSTaniya Das 311e910b2bSTaniya Das clocks: 321e910b2bSTaniya Das items: 331e910b2bSTaniya Das - description: Board XO source 341e910b2bSTaniya Das - description: Video AHB clock from GCC 351e910b2bSTaniya Das 361e910b2bSTaniya Das power-domains: 371e910b2bSTaniya Das maxItems: 1 381e910b2bSTaniya Das description: 391e910b2bSTaniya Das MMCX power domain. 401e910b2bSTaniya Das 411e910b2bSTaniya Das required-opps: 421e910b2bSTaniya Das maxItems: 1 431e910b2bSTaniya Das description: 441e910b2bSTaniya Das A phandle to an OPP node describing required MMCX performance point. 451e910b2bSTaniya Das 461e910b2bSTaniya Das '#clock-cells': 471e910b2bSTaniya Das const: 1 481e910b2bSTaniya Das 491e910b2bSTaniya Das '#reset-cells': 501e910b2bSTaniya Das const: 1 511e910b2bSTaniya Das 521e910b2bSTaniya Das '#power-domain-cells': 531e910b2bSTaniya Das const: 1 541e910b2bSTaniya Das 551e910b2bSTaniya Dasrequired: 561e910b2bSTaniya Das - compatible 571e910b2bSTaniya Das - reg 581e910b2bSTaniya Das - clocks 591e910b2bSTaniya Das - power-domains 601e910b2bSTaniya Das - required-opps 611e910b2bSTaniya Das - '#clock-cells' 621e910b2bSTaniya Das - '#reset-cells' 631e910b2bSTaniya Das - '#power-domain-cells' 641e910b2bSTaniya Das 651e910b2bSTaniya DasadditionalProperties: false 661e910b2bSTaniya Das 671e910b2bSTaniya Dasexamples: 681e910b2bSTaniya Das - | 691e910b2bSTaniya Das #include <dt-bindings/clock/qcom,gcc-sm8450.h> 701e910b2bSTaniya Das #include <dt-bindings/clock/qcom,rpmh.h> 71014f3272SRohit Agarwal #include <dt-bindings/power/qcom,rpmhpd.h> 721e910b2bSTaniya Das videocc: clock-controller@aaf0000 { 731e910b2bSTaniya Das compatible = "qcom,sm8450-videocc"; 741e910b2bSTaniya Das reg = <0x0aaf0000 0x10000>; 751e910b2bSTaniya Das clocks = <&rpmhcc RPMH_CXO_CLK>, 761e910b2bSTaniya Das <&gcc GCC_VIDEO_AHB_CLK>; 77014f3272SRohit Agarwal power-domains = <&rpmhpd RPMHPD_MMCX>; 781e910b2bSTaniya Das required-opps = <&rpmhpd_opp_low_svs>; 791e910b2bSTaniya Das #clock-cells = <1>; 801e910b2bSTaniya Das #reset-cells = <1>; 811e910b2bSTaniya Das #power-domain-cells = <1>; 821e910b2bSTaniya Das }; 831e910b2bSTaniya Das... 84