xref: /linux/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml (revision c771600c6af14749609b49565ffb4cac2959710d)
14ae547ceSYassine Oudjana# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
24ae547ceSYassine Oudjana%YAML 1.2
34ae547ceSYassine Oudjana---
4c1a9a21fSRob Herring (Arm)$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml#
54b71ed9fSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml#
64ae547ceSYassine Oudjana
74ae547ceSYassine Oudjanatitle: MediaTek Infrastructure System Configuration Controller
84ae547ceSYassine Oudjana
94ae547ceSYassine Oudjanamaintainers:
104ae547ceSYassine Oudjana  - Matthias Brugger <matthias.bgg@gmail.com>
114ae547ceSYassine Oudjana
124ae547ceSYassine Oudjanadescription:
134ae547ceSYassine Oudjana  The Mediatek infracfg controller provides various clocks and reset outputs
14*ea1cca02SYassine Oudjana  to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>
15*ea1cca02SYassine Oudjana  and <dt-bindings/clock/mediatek,mt*-infracfg.h>, and reset values in
16*ea1cca02SYassine Oudjana  <dt-bindings/reset/mt*-reset.h>, <dt-bindings/reset/mt*-resets.h> and
17*ea1cca02SYassine Oudjana  <dt-bindings/reset/mediatek,mt*-infracfg.h>.
184ae547ceSYassine Oudjana
194ae547ceSYassine Oudjanaproperties:
204ae547ceSYassine Oudjana  compatible:
214ae547ceSYassine Oudjana    oneOf:
224ae547ceSYassine Oudjana      - items:
234ae547ceSYassine Oudjana          - enum:
244ae547ceSYassine Oudjana              - mediatek,mt2701-infracfg
254ae547ceSYassine Oudjana              - mediatek,mt2712-infracfg
26*ea1cca02SYassine Oudjana              - mediatek,mt6735-infracfg
274ae547ceSYassine Oudjana              - mediatek,mt6765-infracfg
28d5099c95SAngeloGioacchino Del Regno              - mediatek,mt6795-infracfg
294ae547ceSYassine Oudjana              - mediatek,mt6779-infracfg_ao
304ae547ceSYassine Oudjana              - mediatek,mt6797-infracfg
314ae547ceSYassine Oudjana              - mediatek,mt7622-infracfg
324ae547ceSYassine Oudjana              - mediatek,mt7629-infracfg
33cc4d9e0cSDaniel Golle              - mediatek,mt7981-infracfg
344ae547ceSYassine Oudjana              - mediatek,mt7986-infracfg
35afd36e9dSDaniel Golle              - mediatek,mt7988-infracfg
364ae547ceSYassine Oudjana              - mediatek,mt8135-infracfg
374ae547ceSYassine Oudjana              - mediatek,mt8167-infracfg
384ae547ceSYassine Oudjana              - mediatek,mt8173-infracfg
394ae547ceSYassine Oudjana              - mediatek,mt8183-infracfg
404ae547ceSYassine Oudjana              - mediatek,mt8516-infracfg
414ae547ceSYassine Oudjana          - const: syscon
424ae547ceSYassine Oudjana      - items:
434ae547ceSYassine Oudjana          - const: mediatek,mt7623-infracfg
444ae547ceSYassine Oudjana          - const: mediatek,mt2701-infracfg
454ae547ceSYassine Oudjana          - const: syscon
464ae547ceSYassine Oudjana
474ae547ceSYassine Oudjana  reg:
484ae547ceSYassine Oudjana    maxItems: 1
494ae547ceSYassine Oudjana
504ae547ceSYassine Oudjana  '#clock-cells':
514ae547ceSYassine Oudjana    const: 1
524ae547ceSYassine Oudjana
534ae547ceSYassine Oudjana  '#reset-cells':
544ae547ceSYassine Oudjana    const: 1
554ae547ceSYassine Oudjana
564ae547ceSYassine Oudjanarequired:
574ae547ceSYassine Oudjana  - compatible
584ae547ceSYassine Oudjana  - reg
594ae547ceSYassine Oudjana  - '#clock-cells'
604ae547ceSYassine Oudjana
614ae547ceSYassine Oudjanaif:
624ae547ceSYassine Oudjana  properties:
634ae547ceSYassine Oudjana    compatible:
644ae547ceSYassine Oudjana      contains:
654ae547ceSYassine Oudjana        enum:
664ae547ceSYassine Oudjana          - mediatek,mt2701-infracfg
674ae547ceSYassine Oudjana          - mediatek,mt2712-infracfg
68d5099c95SAngeloGioacchino Del Regno          - mediatek,mt6795-infracfg
694ae547ceSYassine Oudjana          - mediatek,mt7622-infracfg
704ae547ceSYassine Oudjana          - mediatek,mt7986-infracfg
714ae547ceSYassine Oudjana          - mediatek,mt8135-infracfg
724ae547ceSYassine Oudjana          - mediatek,mt8173-infracfg
734ae547ceSYassine Oudjana          - mediatek,mt8183-infracfg
744ae547ceSYassine Oudjanathen:
754ae547ceSYassine Oudjana  required:
764ae547ceSYassine Oudjana    - '#reset-cells'
774ae547ceSYassine Oudjana
784ae547ceSYassine OudjanaadditionalProperties: false
794ae547ceSYassine Oudjana
804ae547ceSYassine Oudjanaexamples:
814ae547ceSYassine Oudjana  - |
824ae547ceSYassine Oudjana    infracfg: clock-controller@10001000 {
834ae547ceSYassine Oudjana        compatible = "mediatek,mt8173-infracfg", "syscon";
844ae547ceSYassine Oudjana        reg = <0x10001000 0x1000>;
854ae547ceSYassine Oudjana        #clock-cells = <1>;
864ae547ceSYassine Oudjana        #reset-cells = <1>;
874ae547ceSYassine Oudjana    };
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