1*91ab38f7SAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*91ab38f7SAnson Huang%YAML 1.2 3*91ab38f7SAnson Huang--- 4*91ab38f7SAnson Huang$id: http://devicetree.org/schemas/clock/imx35-clock.yaml# 5*91ab38f7SAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*91ab38f7SAnson Huang 7*91ab38f7SAnson Huangtitle: Clock bindings for Freescale i.MX35 8*91ab38f7SAnson Huang 9*91ab38f7SAnson Huangmaintainers: 10*91ab38f7SAnson Huang - Steffen Trumtrar <s.trumtrar@pengutronix.de> 11*91ab38f7SAnson Huang 12*91ab38f7SAnson Huangdescription: | 13*91ab38f7SAnson Huang The clock consumer should specify the desired clock by having the clock 14*91ab38f7SAnson Huang ID in its "clocks" phandle cell. The following is a full list of i.MX35 15*91ab38f7SAnson Huang clocks and IDs. 16*91ab38f7SAnson Huang 17*91ab38f7SAnson Huang Clock ID 18*91ab38f7SAnson Huang --------------------------- 19*91ab38f7SAnson Huang ckih 0 20*91ab38f7SAnson Huang mpll 1 21*91ab38f7SAnson Huang ppll 2 22*91ab38f7SAnson Huang mpll_075 3 23*91ab38f7SAnson Huang arm 4 24*91ab38f7SAnson Huang hsp 5 25*91ab38f7SAnson Huang hsp_div 6 26*91ab38f7SAnson Huang hsp_sel 7 27*91ab38f7SAnson Huang ahb 8 28*91ab38f7SAnson Huang ipg 9 29*91ab38f7SAnson Huang arm_per_div 10 30*91ab38f7SAnson Huang ahb_per_div 11 31*91ab38f7SAnson Huang ipg_per 12 32*91ab38f7SAnson Huang uart_sel 13 33*91ab38f7SAnson Huang uart_div 14 34*91ab38f7SAnson Huang esdhc_sel 15 35*91ab38f7SAnson Huang esdhc1_div 16 36*91ab38f7SAnson Huang esdhc2_div 17 37*91ab38f7SAnson Huang esdhc3_div 18 38*91ab38f7SAnson Huang spdif_sel 19 39*91ab38f7SAnson Huang spdif_div_pre 20 40*91ab38f7SAnson Huang spdif_div_post 21 41*91ab38f7SAnson Huang ssi_sel 22 42*91ab38f7SAnson Huang ssi1_div_pre 23 43*91ab38f7SAnson Huang ssi1_div_post 24 44*91ab38f7SAnson Huang ssi2_div_pre 25 45*91ab38f7SAnson Huang ssi2_div_post 26 46*91ab38f7SAnson Huang usb_sel 27 47*91ab38f7SAnson Huang usb_div 28 48*91ab38f7SAnson Huang nfc_div 29 49*91ab38f7SAnson Huang asrc_gate 30 50*91ab38f7SAnson Huang pata_gate 31 51*91ab38f7SAnson Huang audmux_gate 32 52*91ab38f7SAnson Huang can1_gate 33 53*91ab38f7SAnson Huang can2_gate 34 54*91ab38f7SAnson Huang cspi1_gate 35 55*91ab38f7SAnson Huang cspi2_gate 36 56*91ab38f7SAnson Huang ect_gate 37 57*91ab38f7SAnson Huang edio_gate 38 58*91ab38f7SAnson Huang emi_gate 39 59*91ab38f7SAnson Huang epit1_gate 40 60*91ab38f7SAnson Huang epit2_gate 41 61*91ab38f7SAnson Huang esai_gate 42 62*91ab38f7SAnson Huang esdhc1_gate 43 63*91ab38f7SAnson Huang esdhc2_gate 44 64*91ab38f7SAnson Huang esdhc3_gate 45 65*91ab38f7SAnson Huang fec_gate 46 66*91ab38f7SAnson Huang gpio1_gate 47 67*91ab38f7SAnson Huang gpio2_gate 48 68*91ab38f7SAnson Huang gpio3_gate 49 69*91ab38f7SAnson Huang gpt_gate 50 70*91ab38f7SAnson Huang i2c1_gate 51 71*91ab38f7SAnson Huang i2c2_gate 52 72*91ab38f7SAnson Huang i2c3_gate 53 73*91ab38f7SAnson Huang iomuxc_gate 54 74*91ab38f7SAnson Huang ipu_gate 55 75*91ab38f7SAnson Huang kpp_gate 56 76*91ab38f7SAnson Huang mlb_gate 57 77*91ab38f7SAnson Huang mshc_gate 58 78*91ab38f7SAnson Huang owire_gate 59 79*91ab38f7SAnson Huang pwm_gate 60 80*91ab38f7SAnson Huang rngc_gate 61 81*91ab38f7SAnson Huang rtc_gate 62 82*91ab38f7SAnson Huang rtic_gate 63 83*91ab38f7SAnson Huang scc_gate 64 84*91ab38f7SAnson Huang sdma_gate 65 85*91ab38f7SAnson Huang spba_gate 66 86*91ab38f7SAnson Huang spdif_gate 67 87*91ab38f7SAnson Huang ssi1_gate 68 88*91ab38f7SAnson Huang ssi2_gate 69 89*91ab38f7SAnson Huang uart1_gate 70 90*91ab38f7SAnson Huang uart2_gate 71 91*91ab38f7SAnson Huang uart3_gate 72 92*91ab38f7SAnson Huang usbotg_gate 73 93*91ab38f7SAnson Huang wdog_gate 74 94*91ab38f7SAnson Huang max_gate 75 95*91ab38f7SAnson Huang admux_gate 76 96*91ab38f7SAnson Huang csi_gate 77 97*91ab38f7SAnson Huang csi_div 78 98*91ab38f7SAnson Huang csi_sel 79 99*91ab38f7SAnson Huang iim_gate 80 100*91ab38f7SAnson Huang gpu2d_gate 81 101*91ab38f7SAnson Huang ckli_gate 82 102*91ab38f7SAnson Huang 103*91ab38f7SAnson Huangproperties: 104*91ab38f7SAnson Huang compatible: 105*91ab38f7SAnson Huang const: fsl,imx35-ccm 106*91ab38f7SAnson Huang 107*91ab38f7SAnson Huang reg: 108*91ab38f7SAnson Huang maxItems: 1 109*91ab38f7SAnson Huang 110*91ab38f7SAnson Huang interrupts: 111*91ab38f7SAnson Huang maxItems: 1 112*91ab38f7SAnson Huang 113*91ab38f7SAnson Huang '#clock-cells': 114*91ab38f7SAnson Huang const: 1 115*91ab38f7SAnson Huang 116*91ab38f7SAnson Huangrequired: 117*91ab38f7SAnson Huang - compatible 118*91ab38f7SAnson Huang - reg 119*91ab38f7SAnson Huang - interrupts 120*91ab38f7SAnson Huang - '#clock-cells' 121*91ab38f7SAnson Huang 122*91ab38f7SAnson HuangadditionalProperties: false 123*91ab38f7SAnson Huang 124*91ab38f7SAnson Huangexamples: 125*91ab38f7SAnson Huang - | 126*91ab38f7SAnson Huang clock-controller@53f80000 { 127*91ab38f7SAnson Huang compatible = "fsl,imx35-ccm"; 128*91ab38f7SAnson Huang reg = <0x53f80000 0x4000>; 129*91ab38f7SAnson Huang interrupts = <31>; 130*91ab38f7SAnson Huang #clock-cells = <1>; 131*91ab38f7SAnson Huang }; 132