1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "dm.h"
15 #include "fw.h"
16 #include "led.h"
17 #include "sw.h"
18 #include "hw.h"
19
rtl92de_read_dword_dbi(struct ieee80211_hw * hw,u16 offset,u8 direct)20 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
21 {
22 struct rtl_priv *rtlpriv = rtl_priv(hw);
23 u32 value;
24
25 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
26 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
27 udelay(10);
28 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
29 return value;
30 }
31
rtl92de_write_dword_dbi(struct ieee80211_hw * hw,u16 offset,u32 value,u8 direct)32 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
33 u16 offset, u32 value, u8 direct)
34 {
35 struct rtl_priv *rtlpriv = rtl_priv(hw);
36
37 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
38 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
39 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
40 }
41
_rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)42 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
43 u8 set_bits, u8 clear_bits)
44 {
45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 rtlpci->reg_bcn_ctrl_val |= set_bits;
49 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
50 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
51 }
52
_rtl92de_stop_tx_beacon(struct ieee80211_hw * hw)53 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
54 {
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56 u8 tmp1byte;
57
58 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
59 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
60 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
61 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
62 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
63 tmp1byte &= ~(BIT(0));
64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
65 }
66
_rtl92de_resume_tx_beacon(struct ieee80211_hw * hw)67 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
68 {
69 struct rtl_priv *rtlpriv = rtl_priv(hw);
70 u8 tmp1byte;
71
72 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
73 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
74 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
75 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
76 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
77 tmp1byte |= BIT(0);
78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
79 }
80
_rtl92de_enable_bcn_sub_func(struct ieee80211_hw * hw)81 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
82 {
83 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
84 }
85
_rtl92de_disable_bcn_sub_func(struct ieee80211_hw * hw)86 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
87 {
88 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
89 }
90
rtl92de_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)91 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
92 {
93 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96
97 switch (variable) {
98 case HW_VAR_RCR:
99 *((u32 *) (val)) = rtlpci->receive_config;
100 break;
101 case HW_VAR_RF_STATE:
102 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
103 break;
104 case HW_VAR_FWLPS_RF_ON:{
105 enum rf_pwrstate rfstate;
106 u32 val_rcr;
107
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
109 (u8 *)(&rfstate));
110 if (rfstate == ERFOFF) {
111 *((bool *) (val)) = true;
112 } else {
113 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
114 val_rcr &= 0x00070000;
115 if (val_rcr)
116 *((bool *) (val)) = false;
117 else
118 *((bool *) (val)) = true;
119 }
120 break;
121 }
122 case HW_VAR_FW_PSMODE_STATUS:
123 *((bool *) (val)) = ppsc->fw_current_inpsmode;
124 break;
125 case HW_VAR_CORRECT_TSF:{
126 u64 tsf;
127 u32 *ptsf_low = (u32 *)&tsf;
128 u32 *ptsf_high = ((u32 *)&tsf) + 1;
129
130 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
131 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
132 *((u64 *) (val)) = tsf;
133 break;
134 }
135 case HW_VAR_INT_MIGRATION:
136 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
137 break;
138 case HW_VAR_INT_AC:
139 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
140 break;
141 case HAL_DEF_WOWLAN:
142 break;
143 default:
144 pr_err("switch case %#x not processed\n", variable);
145 break;
146 }
147 }
148
rtl92de_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)149 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 {
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
154 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
156 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
157 u8 idx;
158
159 switch (variable) {
160 case HW_VAR_ETHER_ADDR:
161 for (idx = 0; idx < ETH_ALEN; idx++) {
162 rtl_write_byte(rtlpriv, (REG_MACID + idx),
163 val[idx]);
164 }
165 break;
166 case HW_VAR_BASIC_RATE: {
167 u16 rate_cfg = ((u16 *) val)[0];
168 u8 rate_index = 0;
169
170 rate_cfg = rate_cfg & 0x15f;
171 if (mac->vendor == PEER_CISCO &&
172 ((rate_cfg & 0x150) == 0))
173 rate_cfg |= 0x01;
174 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
175 rtl_write_byte(rtlpriv, REG_RRSR + 1,
176 (rate_cfg >> 8) & 0xff);
177 while (rate_cfg > 0x1) {
178 rate_cfg = (rate_cfg >> 1);
179 rate_index++;
180 }
181 if (rtlhal->fw_version > 0xe)
182 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
183 rate_index);
184 break;
185 }
186 case HW_VAR_BSSID:
187 for (idx = 0; idx < ETH_ALEN; idx++) {
188 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
189 val[idx]);
190 }
191 break;
192 case HW_VAR_SIFS:
193 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
194 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197 if (!mac->ht_enable)
198 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
199 0x0e0e);
200 else
201 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
202 *((u16 *) val));
203 break;
204 case HW_VAR_SLOT_TIME: {
205 u8 e_aci;
206
207 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
208 "HW_VAR_SLOT_TIME %x\n", val[0]);
209 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
210 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
211 rtlpriv->cfg->ops->set_hw_reg(hw,
212 HW_VAR_AC_PARAM,
213 (&e_aci));
214 break;
215 }
216 case HW_VAR_ACK_PREAMBLE: {
217 u8 reg_tmp;
218 u8 short_preamble = (bool) (*val);
219
220 reg_tmp = (mac->cur_40_prime_sc) << 5;
221 if (short_preamble)
222 reg_tmp |= 0x80;
223 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
224 break;
225 }
226 case HW_VAR_AMPDU_MIN_SPACE: {
227 u8 min_spacing_to_set;
228
229 min_spacing_to_set = *val;
230 if (min_spacing_to_set <= 7) {
231 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
232 min_spacing_to_set);
233 *val = min_spacing_to_set;
234 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
235 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
236 mac->min_space_cfg);
237 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
238 mac->min_space_cfg);
239 }
240 break;
241 }
242 case HW_VAR_SHORTGI_DENSITY: {
243 u8 density_to_set;
244
245 density_to_set = *val;
246 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
247 mac->min_space_cfg |= (density_to_set << 3);
248 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
249 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
250 mac->min_space_cfg);
251 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
252 mac->min_space_cfg);
253 break;
254 }
255 case HW_VAR_AMPDU_FACTOR: {
256 u8 factor_toset;
257 u32 regtoset;
258 u8 *ptmp_byte = NULL;
259 u8 index;
260
261 if (rtlhal->macphymode == DUALMAC_DUALPHY)
262 regtoset = 0xb9726641;
263 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
264 regtoset = 0x66626641;
265 else
266 regtoset = 0xb972a841;
267 factor_toset = *val;
268 if (factor_toset <= 3) {
269 factor_toset = (1 << (factor_toset + 2));
270 if (factor_toset > 0xf)
271 factor_toset = 0xf;
272 for (index = 0; index < 4; index++) {
273 ptmp_byte = (u8 *)(®toset) + index;
274 if ((*ptmp_byte & 0xf0) >
275 (factor_toset << 4))
276 *ptmp_byte = (*ptmp_byte & 0x0f)
277 | (factor_toset << 4);
278 if ((*ptmp_byte & 0x0f) > factor_toset)
279 *ptmp_byte = (*ptmp_byte & 0xf0)
280 | (factor_toset);
281 }
282 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset);
283 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
284 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
285 factor_toset);
286 }
287 break;
288 }
289 case HW_VAR_AC_PARAM: {
290 u8 e_aci = *val;
291 rtl92d_dm_init_edca_turbo(hw);
292 if (rtlpci->acm_method != EACMWAY2_SW)
293 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
294 &e_aci);
295 break;
296 }
297 case HW_VAR_ACM_CTRL: {
298 u8 e_aci = *val;
299 union aci_aifsn *p_aci_aifsn =
300 (union aci_aifsn *)(&(mac->ac[0].aifs));
301 u8 acm = p_aci_aifsn->f.acm;
302 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
303
304 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
305 if (acm) {
306 switch (e_aci) {
307 case AC0_BE:
308 acm_ctrl |= ACMHW_BEQEN;
309 break;
310 case AC2_VI:
311 acm_ctrl |= ACMHW_VIQEN;
312 break;
313 case AC3_VO:
314 acm_ctrl |= ACMHW_VOQEN;
315 break;
316 default:
317 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
318 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
319 acm);
320 break;
321 }
322 } else {
323 switch (e_aci) {
324 case AC0_BE:
325 acm_ctrl &= (~ACMHW_BEQEN);
326 break;
327 case AC2_VI:
328 acm_ctrl &= (~ACMHW_VIQEN);
329 break;
330 case AC3_VO:
331 acm_ctrl &= (~ACMHW_VOQEN);
332 break;
333 default:
334 pr_err("switch case %#x not processed\n",
335 e_aci);
336 break;
337 }
338 }
339 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
340 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
341 acm_ctrl);
342 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
343 break;
344 }
345 case HW_VAR_RCR:
346 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
347 rtlpci->receive_config = ((u32 *) (val))[0];
348 break;
349 case HW_VAR_RETRY_LIMIT: {
350 u8 retry_limit = val[0];
351
352 rtl_write_word(rtlpriv, REG_RL,
353 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
354 retry_limit << RETRY_LIMIT_LONG_SHIFT);
355 break;
356 }
357 case HW_VAR_DUAL_TSF_RST:
358 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
359 break;
360 case HW_VAR_EFUSE_BYTES:
361 rtlefuse->efuse_usedbytes = *((u16 *) val);
362 break;
363 case HW_VAR_EFUSE_USAGE:
364 rtlefuse->efuse_usedpercentage = *val;
365 break;
366 case HW_VAR_IO_CMD:
367 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
368 break;
369 case HW_VAR_WPA_CONFIG:
370 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
371 break;
372 case HW_VAR_SET_RPWM:
373 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
374 break;
375 case HW_VAR_H2C_FW_PWRMODE:
376 break;
377 case HW_VAR_FW_PSMODE_STATUS:
378 ppsc->fw_current_inpsmode = *((bool *) val);
379 break;
380 case HW_VAR_H2C_FW_JOINBSSRPT: {
381 u8 mstatus = (*val);
382 u8 tmp_regcr, tmp_reg422;
383 bool recover = false;
384
385 if (mstatus == RT_MEDIA_CONNECT) {
386 rtlpriv->cfg->ops->set_hw_reg(hw,
387 HW_VAR_AID, NULL);
388 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
389 rtl_write_byte(rtlpriv, REG_CR + 1,
390 (tmp_regcr | BIT(0)));
391 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
392 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
393 tmp_reg422 = rtl_read_byte(rtlpriv,
394 REG_FWHW_TXQ_CTRL + 2);
395 if (tmp_reg422 & BIT(6))
396 recover = true;
397 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
398 tmp_reg422 & (~BIT(6)));
399 rtl92d_set_fw_rsvdpagepkt(hw, 0);
400 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
401 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
402 if (recover)
403 rtl_write_byte(rtlpriv,
404 REG_FWHW_TXQ_CTRL + 2,
405 tmp_reg422);
406 rtl_write_byte(rtlpriv, REG_CR + 1,
407 (tmp_regcr & ~(BIT(0))));
408 }
409 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
410 break;
411 }
412 case HW_VAR_AID: {
413 u16 u2btmp;
414 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
415 u2btmp &= 0xC000;
416 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
417 mac->assoc_id));
418 break;
419 }
420 case HW_VAR_CORRECT_TSF: {
421 u8 btype_ibss = val[0];
422
423 if (btype_ibss)
424 _rtl92de_stop_tx_beacon(hw);
425 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
426 rtl_write_dword(rtlpriv, REG_TSFTR,
427 (u32) (mac->tsf & 0xffffffff));
428 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
429 (u32) ((mac->tsf >> 32) & 0xffffffff));
430 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
431 if (btype_ibss)
432 _rtl92de_resume_tx_beacon(hw);
433
434 break;
435 }
436 case HW_VAR_INT_MIGRATION: {
437 bool int_migration = *(bool *) (val);
438
439 if (int_migration) {
440 /* Set interrupt migration timer and
441 * corresponding Tx/Rx counter.
442 * timer 25ns*0xfa0=100us for 0xf packets.
443 * 0x306:Rx, 0x307:Tx */
444 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
445 rtlpriv->dm.interrupt_migration = int_migration;
446 } else {
447 /* Reset all interrupt migration settings. */
448 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
449 rtlpriv->dm.interrupt_migration = int_migration;
450 }
451 break;
452 }
453 case HW_VAR_INT_AC: {
454 bool disable_ac_int = *((bool *) val);
455
456 /* Disable four ACs interrupts. */
457 if (disable_ac_int) {
458 /* Disable VO, VI, BE and BK four AC interrupts
459 * to gain more efficient CPU utilization.
460 * When extremely highly Rx OK occurs,
461 * we will disable Tx interrupts.
462 */
463 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
464 RT_AC_INT_MASKS);
465 rtlpriv->dm.disable_tx_int = disable_ac_int;
466 /* Enable four ACs interrupts. */
467 } else {
468 rtlpriv->cfg->ops->update_interrupt_mask(hw,
469 RT_AC_INT_MASKS, 0);
470 rtlpriv->dm.disable_tx_int = disable_ac_int;
471 }
472 break;
473 }
474 default:
475 pr_err("switch case %#x not processed\n", variable);
476 break;
477 }
478 }
479
_rtl92de_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)480 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
481 {
482 struct rtl_priv *rtlpriv = rtl_priv(hw);
483 bool status = true;
484 long count = 0;
485 u32 value = _LLT_INIT_ADDR(address) |
486 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
487
488 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
489 do {
490 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
491 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
492 break;
493 if (count > POLLING_LLT_THRESHOLD) {
494 pr_err("Failed to polling write LLT done at address %d!\n",
495 address);
496 status = false;
497 break;
498 }
499 } while (++count);
500 return status;
501 }
502
_rtl92de_llt_table_init(struct ieee80211_hw * hw)503 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
504 {
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 unsigned short i;
507 u8 txpktbuf_bndy;
508 u8 maxpage;
509 bool status;
510 u32 value32; /* High+low page number */
511 u8 value8; /* normal page number */
512
513 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
514 maxpage = 255;
515 txpktbuf_bndy = 246;
516 value8 = 0;
517 value32 = 0x80bf0d29;
518 } else {
519 maxpage = 127;
520 txpktbuf_bndy = 123;
521 value8 = 0;
522 value32 = 0x80750005;
523 }
524
525 /* Set reserved page for each queue */
526 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
527 /* load RQPN */
528 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
529 rtl_write_dword(rtlpriv, REG_RQPN, value32);
530
531 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
532 /* TXRKTBUG_PG_BNDY */
533 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
534 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
535 txpktbuf_bndy));
536
537 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
538 /* Beacon Head for TXDMA */
539 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
540
541 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
542 /* BCNQ_PGBNDY */
543 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
544 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
545
546 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
547 /* WMAC_LBK_BF_HD */
548 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
549
550 /* Set Tx/Rx page size (Tx must be 128 Bytes, */
551 /* Rx can be 64,128,256,512,1024 bytes) */
552 /* 16. PBP [7:0] = 0x11 */
553 /* TRX page size */
554 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
555
556 /* 17. DRV_INFO_SZ = 0x04 */
557 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
558
559 /* 18. LLT_table_init(Adapter); */
560 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
561 status = _rtl92de_llt_write(hw, i, i + 1);
562 if (!status)
563 return status;
564 }
565
566 /* end of list */
567 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
568 if (!status)
569 return status;
570
571 /* Make the other pages as ring buffer */
572 /* This ring buffer is used as beacon buffer if we */
573 /* config this MAC as two MAC transfer. */
574 /* Otherwise used as local loopback buffer. */
575 for (i = txpktbuf_bndy; i < maxpage; i++) {
576 status = _rtl92de_llt_write(hw, i, (i + 1));
577 if (!status)
578 return status;
579 }
580
581 /* Let last entry point to the start entry of ring buffer */
582 status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy);
583 if (!status)
584 return status;
585
586 return true;
587 }
588
_rtl92de_gen_refresh_led_state(struct ieee80211_hw * hw)589 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
590 {
591 struct rtl_priv *rtlpriv = rtl_priv(hw);
592 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
593 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
594 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
595
596 if (rtlpci->up_first_time)
597 return;
598 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
599 rtl92de_sw_led_on(hw, pin0);
600 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
601 rtl92de_sw_led_on(hw, pin0);
602 else
603 rtl92de_sw_led_off(hw, pin0);
604 }
605
_rtl92de_init_mac(struct ieee80211_hw * hw)606 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
607 {
608 struct rtl_priv *rtlpriv = rtl_priv(hw);
609 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
610 unsigned char bytetmp;
611 unsigned short wordtmp;
612 u16 retry;
613
614 rtl92d_phy_set_poweron(hw);
615 /* Add for resume sequence of power domain according
616 * to power document V11. Chapter V.11.... */
617 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
618 /* unlock ISO/CLK/Power control register */
619 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
620 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
621
622 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
623 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
624 /* 3. delay (1ms) this is not necessary when initially power on */
625
626 /* C. Resume Sequence */
627 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
628 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
629
630 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
631 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
632
633 /* c. DRV runs power on init flow */
634
635 /* auto enable WLAN */
636 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
637 /* Power On Reset for MAC Block */
638 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
639 udelay(2);
640 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
641 udelay(2);
642
643 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
644 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
645 udelay(50);
646 retry = 0;
647 while ((bytetmp & BIT(0)) && retry < 1000) {
648 retry++;
649 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
650 udelay(50);
651 }
652
653 /* Enable Radio off, GPIO, and LED function */
654 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
655 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
656
657 /* release RF digital isolation */
658 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
659 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
660 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
661 udelay(2);
662
663 /* make sure that BB reset OK. */
664 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
665
666 /* Disable REG_CR before enable it to assure reset */
667 rtl_write_word(rtlpriv, REG_CR, 0x0);
668
669 /* Release MAC IO register reset */
670 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
671
672 /* clear stopping tx/rx dma */
673 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
674
675 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
676
677 /* System init */
678 /* 18. LLT_table_init(Adapter); */
679 if (!_rtl92de_llt_table_init(hw))
680 return false;
681
682 /* Clear interrupt and enable interrupt */
683 /* 19. HISR 0x124[31:0] = 0xffffffff; */
684 /* HISRE 0x12C[7:0] = 0xFF */
685 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
686 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
687
688 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
689 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
690 /* The IMR should be enabled later after all init sequence
691 * is finished. */
692
693 /* 22. PCIE configuration space configuration */
694 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
695 /* and PCIe gated clock function is enabled. */
696 /* PCIE configuration space will be written after
697 * all init sequence.(Or by BIOS) */
698
699 rtl92d_phy_config_maccoexist_rfpage(hw);
700
701 /* THe below section is not related to power document Vxx . */
702 /* This is only useful for driver and OS setting. */
703 /* -------------------Software Relative Setting---------------------- */
704 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
705 wordtmp &= 0xf;
706 wordtmp |= 0xF771;
707 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
708
709 /* Reported Tx status from HW for rate adaptive. */
710 /* This should be realtive to power on step 14. But in document V11 */
711 /* still not contain the description.!!! */
712 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
713
714 /* Set Tx/Rx page size (Tx must be 128 Bytes,
715 * Rx can be 64,128,256,512,1024 bytes) */
716 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
717
718 /* Set RCR register */
719 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
720 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
721
722 /* Set TCR register */
723 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
724
725 /* disable earlymode */
726 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
727
728 /* Set TX/RX descriptor physical address(from OS API). */
729 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
730 rtlpci->tx_ring[BEACON_QUEUE].dma);
731 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
732 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
733 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
734 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
735 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
736 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
737 /* Set RX Desc Address */
738 rtl_write_dword(rtlpriv, REG_RX_DESA,
739 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
740
741 /* if we want to support 64 bit DMA, we should set it here,
742 * but now we do not support 64 bit DMA*/
743
744 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
745
746 /* Reset interrupt migration setting when initialization */
747 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
748
749 /* Reconsider when to do this operation after asking HWSD. */
750 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
751 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
752 do {
753 retry++;
754 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
755 } while ((retry < 200) && !(bytetmp & BIT(7)));
756
757 /* After MACIO reset,we must refresh LED state. */
758 _rtl92de_gen_refresh_led_state(hw);
759
760 /* Reset H2C protection register */
761 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
762
763 return true;
764 }
765
_rtl92de_hw_configure(struct ieee80211_hw * hw)766 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
767 {
768 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
769 struct rtl_priv *rtlpriv = rtl_priv(hw);
770 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
771 u8 reg_bw_opmode = BW_OPMODE_20MHZ;
772 u32 reg_rrsr;
773
774 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
775 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
776 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
777 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
778 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
779 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
780 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
781 rtl_write_word(rtlpriv, REG_RL, 0x0707);
782 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
783 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
784 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
785 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
786 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
787 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
788 /* Aggregation threshold */
789 if (rtlhal->macphymode == DUALMAC_DUALPHY)
790 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
791 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
792 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
793 else
794 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
795 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
796 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
797 rtlpci->reg_bcn_ctrl_val = 0x1f;
798 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
799 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
800 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
801 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
802 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
803 /* For throughput */
804 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
805 /* ACKTO for IOT issue. */
806 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
807 /* Set Spec SIFS (used in NAV) */
808 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
809 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
810 /* Set SIFS for CCK */
811 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
812 /* Set SIFS for OFDM */
813 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
814 /* Set Multicast Address. */
815 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
816 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
817 switch (rtlpriv->phy.rf_type) {
818 case RF_1T2R:
819 case RF_1T1R:
820 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
821 break;
822 case RF_2T2R:
823 case RF_2T2R_GREEN:
824 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
825 break;
826 }
827 }
828
_rtl92de_enable_aspm_back_door(struct ieee80211_hw * hw)829 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
830 {
831 struct rtl_priv *rtlpriv = rtl_priv(hw);
832 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
833
834 rtl_write_byte(rtlpriv, 0x34b, 0x93);
835 rtl_write_word(rtlpriv, 0x350, 0x870c);
836 rtl_write_byte(rtlpriv, 0x352, 0x1);
837 if (ppsc->support_backdoor)
838 rtl_write_byte(rtlpriv, 0x349, 0x1b);
839 else
840 rtl_write_byte(rtlpriv, 0x349, 0x03);
841 rtl_write_word(rtlpriv, 0x350, 0x2718);
842 rtl_write_byte(rtlpriv, 0x352, 0x1);
843 }
844
rtl92de_enable_hw_security_config(struct ieee80211_hw * hw)845 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
846 {
847 struct rtl_priv *rtlpriv = rtl_priv(hw);
848 u8 sec_reg_value;
849
850 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
851 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
852 rtlpriv->sec.pairwise_enc_algorithm,
853 rtlpriv->sec.group_enc_algorithm);
854 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
855 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
856 "not open hw encryption\n");
857 return;
858 }
859 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
860 if (rtlpriv->sec.use_defaultkey) {
861 sec_reg_value |= SCR_TXUSEDK;
862 sec_reg_value |= SCR_RXUSEDK;
863 }
864 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
865 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
866 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
867 "The SECR-value %x\n", sec_reg_value);
868 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
869 }
870
rtl92de_hw_init(struct ieee80211_hw * hw)871 int rtl92de_hw_init(struct ieee80211_hw *hw)
872 {
873 struct rtl_priv *rtlpriv = rtl_priv(hw);
874 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
875 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
876 struct rtl_phy *rtlphy = &(rtlpriv->phy);
877 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
878 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
879 bool rtstatus = true;
880 u8 tmp_u1b;
881 int i;
882 int err;
883 unsigned long flags;
884
885 rtlpci->being_init_adapter = true;
886 rtlpci->init_ready = false;
887 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
888 /* we should do iqk after disable/enable */
889 rtl92d_phy_reset_iqk_result(hw);
890 /* rtlpriv->intf_ops->disable_aspm(hw); */
891 rtstatus = _rtl92de_init_mac(hw);
892 if (!rtstatus) {
893 pr_err("Init MAC failed\n");
894 err = 1;
895 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
896 return err;
897 }
898 err = rtl92d_download_fw(hw);
899 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
900 if (err) {
901 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
902 "Failed to download FW. Init HW without FW..\n");
903 return 1;
904 }
905 rtlhal->last_hmeboxnum = 0;
906 rtlpriv->psc.fw_current_inpsmode = false;
907
908 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
909 tmp_u1b = tmp_u1b | 0x30;
910 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
911
912 if (rtlhal->earlymode_enable) {
913 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
914 "EarlyMode Enabled!!!\n");
915
916 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
917 tmp_u1b = tmp_u1b | 0x1f;
918 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
919
920 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
921
922 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
923 tmp_u1b = tmp_u1b | 0x40;
924 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
925 }
926
927 if (mac->rdg_en) {
928 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
929 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
930 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
931 }
932
933 rtl92d_phy_mac_config(hw);
934 /* because last function modify RCR, so we update
935 * rcr var here, or TP will unstable for receive_config
936 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
937 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
938 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
939 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
940
941 rtl92d_phy_bb_config(hw);
942
943 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
944 /* set before initialize RF */
945 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
946
947 /* config RF */
948 rtl92d_phy_rf_config(hw);
949
950 /* After read predefined TXT, we must set BB/MAC/RF
951 * register as our requirement */
952 /* After load BB,RF params,we need do more for 92D. */
953 rtl92d_update_bbrf_configuration(hw);
954 /* set default value after initialize RF, */
955 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
956 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
957 RF_CHNLBW, RFREG_OFFSET_MASK);
958 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
959 RF_CHNLBW, RFREG_OFFSET_MASK);
960
961 /*---- Set CCK and OFDM Block "ON"----*/
962 if (rtlhal->current_bandtype == BAND_ON_2_4G)
963 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
964 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
965 if (rtlhal->interfaceindex == 0) {
966 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
967 * set to 20MHz by default */
968 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
969 BIT(11), 3);
970 } else {
971 /* Mac1 */
972 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
973 BIT(10), 3);
974 }
975
976 _rtl92de_hw_configure(hw);
977
978 /* reset hw sec */
979 rtl_cam_reset_all_entry(hw);
980 rtl92de_enable_hw_security_config(hw);
981
982 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
983 /* TX power index for different rate set. */
984 rtl92d_phy_get_hw_reg_originalvalue(hw);
985 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
986
987 ppsc->rfpwr_state = ERFON;
988
989 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
990
991 _rtl92de_enable_aspm_back_door(hw);
992 /* rtlpriv->intf_ops->enable_aspm(hw); */
993
994 rtl92d_dm_init(hw);
995 rtlpci->being_init_adapter = false;
996
997 if (ppsc->rfpwr_state == ERFON) {
998 rtl92d_phy_lc_calibrate(hw);
999 /* 5G and 2.4G must wait sometime to let RF LO ready */
1000 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1001 u32 tmp_rega;
1002 for (i = 0; i < 10000; i++) {
1003 udelay(MAX_STALL_TIME);
1004
1005 tmp_rega = rtl_get_rfreg(hw,
1006 (enum radio_path)RF90_PATH_A,
1007 0x2a, MASKDWORD);
1008
1009 if (((tmp_rega & BIT(11)) == BIT(11)))
1010 break;
1011 }
1012 /* check that loop was successful. If not, exit now */
1013 if (i == 10000) {
1014 rtlpci->init_ready = false;
1015 return 1;
1016 }
1017 }
1018 }
1019 rtlpci->init_ready = true;
1020 return err;
1021 }
1022
_rtl92de_read_chip_version(struct ieee80211_hw * hw)1023 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1024 {
1025 struct rtl_priv *rtlpriv = rtl_priv(hw);
1026 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1027 u32 value32;
1028
1029 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1030 if (!(value32 & 0x000f0000)) {
1031 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1032 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1033 } else {
1034 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1035 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1036 }
1037 return version;
1038 }
1039
_rtl92de_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1040 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1041 enum nl80211_iftype type)
1042 {
1043 struct rtl_priv *rtlpriv = rtl_priv(hw);
1044 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1045 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1046
1047 bt_msr &= 0xfc;
1048
1049 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1050 type == NL80211_IFTYPE_STATION) {
1051 _rtl92de_stop_tx_beacon(hw);
1052 _rtl92de_enable_bcn_sub_func(hw);
1053 } else if (type == NL80211_IFTYPE_ADHOC ||
1054 type == NL80211_IFTYPE_AP) {
1055 _rtl92de_resume_tx_beacon(hw);
1056 _rtl92de_disable_bcn_sub_func(hw);
1057 } else {
1058 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1059 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1060 type);
1061 }
1062 switch (type) {
1063 case NL80211_IFTYPE_UNSPECIFIED:
1064 bt_msr |= MSR_NOLINK;
1065 ledaction = LED_CTL_LINK;
1066 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1067 "Set Network type to NO LINK!\n");
1068 break;
1069 case NL80211_IFTYPE_ADHOC:
1070 bt_msr |= MSR_ADHOC;
1071 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1072 "Set Network type to Ad Hoc!\n");
1073 break;
1074 case NL80211_IFTYPE_STATION:
1075 bt_msr |= MSR_INFRA;
1076 ledaction = LED_CTL_LINK;
1077 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1078 "Set Network type to STA!\n");
1079 break;
1080 case NL80211_IFTYPE_AP:
1081 bt_msr |= MSR_AP;
1082 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1083 "Set Network type to AP!\n");
1084 break;
1085 default:
1086 pr_err("Network type %d not supported!\n", type);
1087 return 1;
1088 }
1089 rtl_write_byte(rtlpriv, MSR, bt_msr);
1090 rtlpriv->cfg->ops->led_control(hw, ledaction);
1091 if ((bt_msr & MSR_MASK) == MSR_AP)
1092 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1093 else
1094 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1095 return 0;
1096 }
1097
rtl92de_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1098 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1099 {
1100 struct rtl_priv *rtlpriv = rtl_priv(hw);
1101 u32 reg_rcr;
1102
1103 if (rtlpriv->psc.rfpwr_state != ERFON)
1104 return;
1105
1106 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1107
1108 if (check_bssid) {
1109 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1110 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1111 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1112 } else if (!check_bssid) {
1113 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1114 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1115 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1116 }
1117 }
1118
rtl92de_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1119 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1120 {
1121 struct rtl_priv *rtlpriv = rtl_priv(hw);
1122
1123 if (_rtl92de_set_media_status(hw, type))
1124 return -EOPNOTSUPP;
1125
1126 /* check bssid */
1127 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1128 if (type != NL80211_IFTYPE_AP)
1129 rtl92de_set_check_bssid(hw, true);
1130 } else {
1131 rtl92de_set_check_bssid(hw, false);
1132 }
1133 return 0;
1134 }
1135
1136 /* do iqk or reload iqk */
1137 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1138 * but it's very strict for time sequence so we add
1139 * rtl92d_phy_reload_iqk_setting here */
rtl92d_linked_set_reg(struct ieee80211_hw * hw)1140 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1141 {
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1144 u8 indexforchannel;
1145 u8 channel = rtlphy->current_channel;
1146
1147 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1148 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1149 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1150 "Do IQK for channel:%d\n", channel);
1151 rtl92d_phy_iq_calibrate(hw);
1152 }
1153 }
1154
1155 /* don't set REG_EDCA_BE_PARAM here because
1156 * mac80211 will send pkt when scan */
rtl92de_set_qos(struct ieee80211_hw * hw,int aci)1157 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1158 {
1159 rtl92d_dm_init_edca_turbo(hw);
1160 }
1161
rtl92de_enable_interrupt(struct ieee80211_hw * hw)1162 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1163 {
1164 struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1166
1167 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1168 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1169 rtlpci->irq_enabled = true;
1170 }
1171
rtl92de_disable_interrupt(struct ieee80211_hw * hw)1172 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1173 {
1174 struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1176
1177 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1178 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1179 rtlpci->irq_enabled = false;
1180 }
1181
_rtl92de_poweroff_adapter(struct ieee80211_hw * hw)1182 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1183 {
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 u8 u1b_tmp;
1186 unsigned long flags;
1187
1188 rtlpriv->intf_ops->enable_aspm(hw);
1189 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1190 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1191 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1192
1193 /* 0x20:value 05-->04 */
1194 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1195
1196 /* ==== Reset digital sequence ====== */
1197 rtl92d_firmware_selfreset(hw);
1198
1199 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1200 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1201
1202 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1203 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1204
1205 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1206
1207 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1208 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1209
1210 /* i. Value = GPIO_PIN_CTRL[7:0] */
1211 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1212
1213 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1214 /* write external PIN level */
1215 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1216 0x00FF0000 | (u1b_tmp << 8));
1217
1218 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1219 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1220
1221 /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1222 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1223
1224 /* ==== Disable analog sequence === */
1225
1226 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1227 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1228
1229 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1230 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1231
1232 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1233 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1234
1235 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1236 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1237
1238 /* ==== interface into suspend === */
1239
1240 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1241 /* According to power document V11, we need to set this */
1242 /* value as 0x18. Otherwise, we may not L0s sometimes. */
1243 /* This indluences power consumption. Bases on SD1's test, */
1244 /* set as 0x00 do not affect power current. And if it */
1245 /* is set as 0x18, they had ever met auto load fail problem. */
1246 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1247
1248 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1249 "In PowerOff,reg0x%x=%X\n",
1250 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1251 /* r. Note: for PCIe interface, PON will not turn */
1252 /* off m-bias and BandGap in PCIe suspend mode. */
1253
1254 /* 0x17[7] 1b': power off in process 0b' : power off over */
1255 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1256 spin_lock_irqsave(&globalmutex_power, flags);
1257 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1258 u1b_tmp &= (~BIT(7));
1259 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1260 spin_unlock_irqrestore(&globalmutex_power, flags);
1261 }
1262
1263 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1264 }
1265
rtl92de_card_disable(struct ieee80211_hw * hw)1266 void rtl92de_card_disable(struct ieee80211_hw *hw)
1267 {
1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1269 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1270 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1271 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1272 enum nl80211_iftype opmode;
1273
1274 mac->link_state = MAC80211_NOLINK;
1275 opmode = NL80211_IFTYPE_UNSPECIFIED;
1276 _rtl92de_set_media_status(hw, opmode);
1277
1278 if (rtlpci->driver_is_goingto_unload ||
1279 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1280 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1281 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1282 /* Power sequence for each MAC. */
1283 /* a. stop tx DMA */
1284 /* b. close RF */
1285 /* c. clear rx buf */
1286 /* d. stop rx DMA */
1287 /* e. reset MAC */
1288
1289 /* a. stop tx DMA */
1290 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1291 udelay(50);
1292
1293 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1294
1295 /* c. ========RF OFF sequence========== */
1296 /* 0x88c[23:20] = 0xf. */
1297 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1298 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1299
1300 /* APSD_CTRL 0x600[7:0] = 0x40 */
1301 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1302
1303 /* Close antenna 0,0xc04,0xd04 */
1304 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1305 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1306
1307 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1308 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1309
1310 /* Mac0 can not do Global reset. Mac1 can do. */
1311 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1312 if (rtlpriv->rtlhal.interfaceindex == 1)
1313 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1314 udelay(50);
1315
1316 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1317 /* dma hang issue when disable/enable device. */
1318 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1319 udelay(50);
1320 rtl_write_byte(rtlpriv, REG_CR, 0x0);
1321 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1322 if (rtl92d_phy_check_poweroff(hw))
1323 _rtl92de_poweroff_adapter(hw);
1324 return;
1325 }
1326
rtl92de_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)1327 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1328 struct rtl_int *intvec)
1329 {
1330 struct rtl_priv *rtlpriv = rtl_priv(hw);
1331 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1332
1333 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1334 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1335 }
1336
rtl92de_set_beacon_related_registers(struct ieee80211_hw * hw)1337 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1338 {
1339 struct rtl_priv *rtlpriv = rtl_priv(hw);
1340 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1341 u16 bcn_interval, atim_window;
1342
1343 bcn_interval = mac->beacon_interval;
1344 atim_window = 2;
1345 rtl92de_disable_interrupt(hw);
1346 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1347 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1348 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1349 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1350 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1351 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1352 else
1353 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1354 rtl_write_byte(rtlpriv, 0x606, 0x30);
1355 }
1356
rtl92de_set_beacon_interval(struct ieee80211_hw * hw)1357 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1358 {
1359 struct rtl_priv *rtlpriv = rtl_priv(hw);
1360 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1361 u16 bcn_interval = mac->beacon_interval;
1362
1363 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1364 "beacon_interval:%d\n", bcn_interval);
1365 rtl92de_disable_interrupt(hw);
1366 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1367 rtl92de_enable_interrupt(hw);
1368 }
1369
rtl92de_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1370 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1371 u32 add_msr, u32 rm_msr)
1372 {
1373 struct rtl_priv *rtlpriv = rtl_priv(hw);
1374 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1375
1376 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1377 add_msr, rm_msr);
1378 if (add_msr)
1379 rtlpci->irq_mask[0] |= add_msr;
1380 if (rm_msr)
1381 rtlpci->irq_mask[0] &= (~rm_msr);
1382 rtl92de_disable_interrupt(hw);
1383 rtl92de_enable_interrupt(hw);
1384 }
1385
_rtl92de_readpowervalue_fromprom(struct txpower_info * pwrinfo,u8 * rom_content,bool autoloadfail)1386 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1387 u8 *rom_content, bool autoloadfail)
1388 {
1389 u32 rfpath, eeaddr, group, offset1, offset2;
1390 u8 i;
1391
1392 memset(pwrinfo, 0, sizeof(struct txpower_info));
1393 if (autoloadfail) {
1394 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1395 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1396 if (group < CHANNEL_GROUP_MAX_2G) {
1397 pwrinfo->cck_index[rfpath][group] =
1398 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1399 pwrinfo->ht40_1sindex[rfpath][group] =
1400 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1401 } else {
1402 pwrinfo->ht40_1sindex[rfpath][group] =
1403 EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1404 }
1405 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1406 EEPROM_DEFAULT_HT40_2SDIFF;
1407 pwrinfo->ht20indexdiff[rfpath][group] =
1408 EEPROM_DEFAULT_HT20_DIFF;
1409 pwrinfo->ofdmindexdiff[rfpath][group] =
1410 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1411 pwrinfo->ht40maxoffset[rfpath][group] =
1412 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1413 pwrinfo->ht20maxoffset[rfpath][group] =
1414 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1415 }
1416 }
1417 for (i = 0; i < 3; i++) {
1418 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1419 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1420 }
1421 return;
1422 }
1423
1424 /* Maybe autoload OK,buf the tx power index value is not filled.
1425 * If we find it, we set it to default value. */
1426 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1427 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1428 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1429 + group;
1430 pwrinfo->cck_index[rfpath][group] =
1431 (rom_content[eeaddr] == 0xFF) ?
1432 (eeaddr > 0x7B ?
1433 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1434 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1435 rom_content[eeaddr];
1436 }
1437 }
1438 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1439 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1440 offset1 = group / 3;
1441 offset2 = group % 3;
1442 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1443 offset2 + offset1 * 21;
1444 pwrinfo->ht40_1sindex[rfpath][group] =
1445 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1446 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1447 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1448 rom_content[eeaddr];
1449 }
1450 }
1451 /* These just for 92D efuse offset. */
1452 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1453 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1454 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1455
1456 offset1 = group / 3;
1457 offset2 = group % 3;
1458
1459 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1460 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1461 (rom_content[base1 +
1462 offset2 + offset1 * 21] >> (rfpath * 4))
1463 & 0xF;
1464 else
1465 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1466 EEPROM_DEFAULT_HT40_2SDIFF;
1467 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1468 + offset1 * 21] != 0xFF)
1469 pwrinfo->ht20indexdiff[rfpath][group] =
1470 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1471 + offset2 + offset1 * 21] >> (rfpath * 4))
1472 & 0xF;
1473 else
1474 pwrinfo->ht20indexdiff[rfpath][group] =
1475 EEPROM_DEFAULT_HT20_DIFF;
1476 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1477 + offset1 * 21] != 0xFF)
1478 pwrinfo->ofdmindexdiff[rfpath][group] =
1479 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1480 + offset2 + offset1 * 21] >> (rfpath * 4))
1481 & 0xF;
1482 else
1483 pwrinfo->ofdmindexdiff[rfpath][group] =
1484 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1485 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1486 + offset1 * 21] != 0xFF)
1487 pwrinfo->ht40maxoffset[rfpath][group] =
1488 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1489 + offset2 + offset1 * 21] >> (rfpath * 4))
1490 & 0xF;
1491 else
1492 pwrinfo->ht40maxoffset[rfpath][group] =
1493 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1494 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1495 + offset1 * 21] != 0xFF)
1496 pwrinfo->ht20maxoffset[rfpath][group] =
1497 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1498 offset2 + offset1 * 21] >> (rfpath * 4)) &
1499 0xF;
1500 else
1501 pwrinfo->ht20maxoffset[rfpath][group] =
1502 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1503 }
1504 }
1505 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1506 /* 5GL */
1507 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1508 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1509 /* 5GM */
1510 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1511 pwrinfo->tssi_b[1] =
1512 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1513 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1514 /* 5GH */
1515 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1516 0xF0) >> 4 |
1517 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1518 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1519 0xFC) >> 2;
1520 } else {
1521 for (i = 0; i < 3; i++) {
1522 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1523 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1524 }
1525 }
1526 }
1527
_rtl92de_read_txpower_info(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1528 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1529 bool autoload_fail, u8 *hwinfo)
1530 {
1531 struct rtl_priv *rtlpriv = rtl_priv(hw);
1532 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1533 struct txpower_info pwrinfo;
1534 u8 tempval[2], i, pwr, diff;
1535 u32 ch, rfpath, group;
1536
1537 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1538 if (!autoload_fail) {
1539 /* bit0~2 */
1540 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1541 rtlefuse->eeprom_thermalmeter =
1542 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1543 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1544 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1545 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1546 rtlefuse->txpwr_fromeprom = true;
1547 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1548 IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1549 rtlefuse->internal_pa_5g[0] =
1550 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1551 rtlefuse->internal_pa_5g[1] =
1552 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1553 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1554 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1555 rtlefuse->internal_pa_5g[0],
1556 rtlefuse->internal_pa_5g[1]);
1557 }
1558 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1559 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1560 } else {
1561 rtlefuse->eeprom_regulatory = 0;
1562 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1563 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1564 tempval[0] = tempval[1] = 3;
1565 }
1566
1567 /* Use default value to fill parameters if
1568 * efuse is not filled on some place. */
1569
1570 /* ThermalMeter from EEPROM */
1571 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1572 rtlefuse->eeprom_thermalmeter > 0x1c)
1573 rtlefuse->eeprom_thermalmeter = 0x12;
1574 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1575
1576 /* check XTAL_K */
1577 if (rtlefuse->crystalcap == 0xFF)
1578 rtlefuse->crystalcap = 0;
1579 if (rtlefuse->eeprom_regulatory > 3)
1580 rtlefuse->eeprom_regulatory = 0;
1581
1582 for (i = 0; i < 2; i++) {
1583 switch (tempval[i]) {
1584 case 0:
1585 tempval[i] = 5;
1586 break;
1587 case 1:
1588 tempval[i] = 4;
1589 break;
1590 case 2:
1591 tempval[i] = 3;
1592 break;
1593 case 3:
1594 default:
1595 tempval[i] = 0;
1596 break;
1597 }
1598 }
1599
1600 rtlefuse->delta_iqk = tempval[0];
1601 if (tempval[1] > 0)
1602 rtlefuse->delta_lck = tempval[1] - 1;
1603 if (rtlefuse->eeprom_c9 == 0xFF)
1604 rtlefuse->eeprom_c9 = 0x00;
1605 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1606 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1607 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1608 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1609 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1610 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1611 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1612 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1613 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1614
1615 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1616 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1617 group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1618 if (ch < CHANNEL_MAX_NUMBER_2G)
1619 rtlefuse->txpwrlevel_cck[rfpath][ch] =
1620 pwrinfo.cck_index[rfpath][group];
1621 rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] =
1622 pwrinfo.ht40_1sindex[rfpath][group];
1623 rtlefuse->txpwr_ht20diff[rfpath][ch] =
1624 pwrinfo.ht20indexdiff[rfpath][group];
1625 rtlefuse->txpwr_legacyhtdiff[rfpath][ch] =
1626 pwrinfo.ofdmindexdiff[rfpath][group];
1627 rtlefuse->pwrgroup_ht20[rfpath][ch] =
1628 pwrinfo.ht20maxoffset[rfpath][group];
1629 rtlefuse->pwrgroup_ht40[rfpath][ch] =
1630 pwrinfo.ht40maxoffset[rfpath][group];
1631 pwr = pwrinfo.ht40_1sindex[rfpath][group];
1632 diff = pwrinfo.ht40_2sindexdiff[rfpath][group];
1633 rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] =
1634 (pwr > diff) ? (pwr - diff) : 0;
1635 }
1636 }
1637 }
1638
_rtl92de_read_macphymode_from_prom(struct ieee80211_hw * hw,u8 * content)1639 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1640 u8 *content)
1641 {
1642 struct rtl_priv *rtlpriv = rtl_priv(hw);
1643 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1644 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1645
1646 if (macphy_crvalue & BIT(3)) {
1647 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1648 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1649 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1650 } else {
1651 rtlhal->macphymode = DUALMAC_DUALPHY;
1652 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1653 "MacPhyMode DUALMAC_DUALPHY\n");
1654 }
1655 }
1656
_rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw * hw,u8 * content)1657 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1658 u8 *content)
1659 {
1660 _rtl92de_read_macphymode_from_prom(hw, content);
1661 rtl92d_phy_config_macphymode(hw);
1662 rtl92d_phy_config_macphymode_info(hw);
1663 }
1664
_rtl92de_efuse_update_chip_version(struct ieee80211_hw * hw)1665 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1666 {
1667 struct rtl_priv *rtlpriv = rtl_priv(hw);
1668 enum version_8192d chipver = rtlpriv->rtlhal.version;
1669 u8 cutvalue[2];
1670 u16 chipvalue;
1671
1672 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1673 &cutvalue[1]);
1674 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1675 &cutvalue[0]);
1676 chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1677 switch (chipvalue) {
1678 case 0xAA55:
1679 chipver |= CHIP_92D_C_CUT;
1680 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1681 break;
1682 case 0x9966:
1683 chipver |= CHIP_92D_D_CUT;
1684 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1685 break;
1686 case 0xCC33:
1687 chipver |= CHIP_92D_E_CUT;
1688 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1689 break;
1690 default:
1691 chipver |= CHIP_92D_D_CUT;
1692 pr_err("Unknown CUT!\n");
1693 break;
1694 }
1695 rtlpriv->rtlhal.version = chipver;
1696 }
1697
_rtl92de_read_adapter_info(struct ieee80211_hw * hw)1698 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1699 {
1700 struct rtl_priv *rtlpriv = rtl_priv(hw);
1701 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1702 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1703 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1704 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
1705 EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1706 COUNTRY_CODE_WORLD_WIDE_13};
1707 int i;
1708 u16 usvalue;
1709 u8 *hwinfo;
1710
1711 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1712 if (!hwinfo)
1713 return;
1714
1715 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1716 goto exit;
1717
1718 _rtl92de_efuse_update_chip_version(hw);
1719 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1720
1721 /* Read Permanent MAC address for 2nd interface */
1722 if (rtlhal->interfaceindex != 0) {
1723 for (i = 0; i < 6; i += 2) {
1724 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1725 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1726 }
1727 }
1728 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1729 rtlefuse->dev_addr);
1730 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1731 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1732
1733 /* Read Channel Plan */
1734 switch (rtlhal->bandset) {
1735 case BAND_ON_2_4G:
1736 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1737 break;
1738 case BAND_ON_5G:
1739 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1740 break;
1741 case BAND_ON_BOTH:
1742 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1743 break;
1744 default:
1745 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1746 break;
1747 }
1748 rtlefuse->txpwr_fromeprom = true;
1749 exit:
1750 kfree(hwinfo);
1751 }
1752
rtl92de_read_eeprom_info(struct ieee80211_hw * hw)1753 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1754 {
1755 struct rtl_priv *rtlpriv = rtl_priv(hw);
1756 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1757 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1758 u8 tmp_u1b;
1759
1760 rtlhal->version = _rtl92de_read_chip_version(hw);
1761 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1762 rtlefuse->autoload_status = tmp_u1b;
1763 if (tmp_u1b & BIT(4)) {
1764 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1765 rtlefuse->epromtype = EEPROM_93C46;
1766 } else {
1767 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1768 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1769 }
1770 if (tmp_u1b & BIT(5)) {
1771 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1772
1773 rtlefuse->autoload_failflag = false;
1774 _rtl92de_read_adapter_info(hw);
1775 } else {
1776 pr_err("Autoload ERR!!\n");
1777 }
1778 return;
1779 }
1780
rtl92de_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1781 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1782 struct ieee80211_sta *sta)
1783 {
1784 struct rtl_priv *rtlpriv = rtl_priv(hw);
1785 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1786 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1787 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1788 u32 ratr_value;
1789 u8 ratr_index = 0;
1790 u8 nmode = mac->ht_enable;
1791 u8 mimo_ps = IEEE80211_SMPS_OFF;
1792 u16 shortgi_rate;
1793 u32 tmp_ratr_value;
1794 u8 curtxbw_40mhz = mac->bw_40;
1795 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1796 1 : 0;
1797 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1798 1 : 0;
1799 enum wireless_mode wirelessmode = mac->mode;
1800
1801 if (rtlhal->current_bandtype == BAND_ON_5G)
1802 ratr_value = sta->deflink.supp_rates[1] << 4;
1803 else
1804 ratr_value = sta->deflink.supp_rates[0];
1805 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1806 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1807 switch (wirelessmode) {
1808 case WIRELESS_MODE_A:
1809 ratr_value &= 0x00000FF0;
1810 break;
1811 case WIRELESS_MODE_B:
1812 if (ratr_value & 0x0000000c)
1813 ratr_value &= 0x0000000d;
1814 else
1815 ratr_value &= 0x0000000f;
1816 break;
1817 case WIRELESS_MODE_G:
1818 ratr_value &= 0x00000FF5;
1819 break;
1820 case WIRELESS_MODE_N_24G:
1821 case WIRELESS_MODE_N_5G:
1822 nmode = 1;
1823 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1824 ratr_value &= 0x0007F005;
1825 } else {
1826 u32 ratr_mask;
1827
1828 if (get_rf_type(rtlphy) == RF_1T2R ||
1829 get_rf_type(rtlphy) == RF_1T1R) {
1830 ratr_mask = 0x000ff005;
1831 } else {
1832 ratr_mask = 0x0f0ff005;
1833 }
1834
1835 ratr_value &= ratr_mask;
1836 }
1837 break;
1838 default:
1839 if (rtlphy->rf_type == RF_1T2R)
1840 ratr_value &= 0x000ff0ff;
1841 else
1842 ratr_value &= 0x0f0ff0ff;
1843
1844 break;
1845 }
1846 ratr_value &= 0x0FFFFFFF;
1847 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1848 (!curtxbw_40mhz && curshortgi_20mhz))) {
1849 ratr_value |= 0x10000000;
1850 tmp_ratr_value = (ratr_value >> 12);
1851 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1852 if ((1 << shortgi_rate) & tmp_ratr_value)
1853 break;
1854 }
1855 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1856 (shortgi_rate << 4) | (shortgi_rate);
1857 }
1858 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1859 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1860 rtl_read_dword(rtlpriv, REG_ARFR0));
1861 }
1862
rtl92de_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)1863 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1864 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1865 {
1866 struct rtl_priv *rtlpriv = rtl_priv(hw);
1867 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1868 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1869 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1870 struct rtl_sta_info *sta_entry = NULL;
1871 u32 ratr_bitmap;
1872 u8 ratr_index;
1873 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1874 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1875 1 : 0;
1876 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1877 1 : 0;
1878 enum wireless_mode wirelessmode = 0;
1879 bool shortgi = false;
1880 u32 value[2];
1881 u8 macid = 0;
1882 u8 mimo_ps = IEEE80211_SMPS_OFF;
1883
1884 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1885 mimo_ps = sta_entry->mimo_ps;
1886 wirelessmode = sta_entry->wireless_mode;
1887 if (mac->opmode == NL80211_IFTYPE_STATION)
1888 curtxbw_40mhz = mac->bw_40;
1889 else if (mac->opmode == NL80211_IFTYPE_AP ||
1890 mac->opmode == NL80211_IFTYPE_ADHOC)
1891 macid = sta->aid + 1;
1892
1893 if (rtlhal->current_bandtype == BAND_ON_5G)
1894 ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1895 else
1896 ratr_bitmap = sta->deflink.supp_rates[0];
1897 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1898 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1899 switch (wirelessmode) {
1900 case WIRELESS_MODE_B:
1901 ratr_index = RATR_INX_WIRELESS_B;
1902 if (ratr_bitmap & 0x0000000c)
1903 ratr_bitmap &= 0x0000000d;
1904 else
1905 ratr_bitmap &= 0x0000000f;
1906 break;
1907 case WIRELESS_MODE_G:
1908 ratr_index = RATR_INX_WIRELESS_GB;
1909
1910 if (rssi_level == 1)
1911 ratr_bitmap &= 0x00000f00;
1912 else if (rssi_level == 2)
1913 ratr_bitmap &= 0x00000ff0;
1914 else
1915 ratr_bitmap &= 0x00000ff5;
1916 break;
1917 case WIRELESS_MODE_A:
1918 ratr_index = RATR_INX_WIRELESS_G;
1919 ratr_bitmap &= 0x00000ff0;
1920 break;
1921 case WIRELESS_MODE_N_24G:
1922 case WIRELESS_MODE_N_5G:
1923 if (wirelessmode == WIRELESS_MODE_N_24G)
1924 ratr_index = RATR_INX_WIRELESS_NGB;
1925 else
1926 ratr_index = RATR_INX_WIRELESS_NG;
1927 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1928 if (rssi_level == 1)
1929 ratr_bitmap &= 0x00070000;
1930 else if (rssi_level == 2)
1931 ratr_bitmap &= 0x0007f000;
1932 else
1933 ratr_bitmap &= 0x0007f005;
1934 } else {
1935 if (rtlphy->rf_type == RF_1T2R ||
1936 rtlphy->rf_type == RF_1T1R) {
1937 if (curtxbw_40mhz) {
1938 if (rssi_level == 1)
1939 ratr_bitmap &= 0x000f0000;
1940 else if (rssi_level == 2)
1941 ratr_bitmap &= 0x000ff000;
1942 else
1943 ratr_bitmap &= 0x000ff015;
1944 } else {
1945 if (rssi_level == 1)
1946 ratr_bitmap &= 0x000f0000;
1947 else if (rssi_level == 2)
1948 ratr_bitmap &= 0x000ff000;
1949 else
1950 ratr_bitmap &= 0x000ff005;
1951 }
1952 } else {
1953 if (curtxbw_40mhz) {
1954 if (rssi_level == 1)
1955 ratr_bitmap &= 0x0f0f0000;
1956 else if (rssi_level == 2)
1957 ratr_bitmap &= 0x0f0ff000;
1958 else
1959 ratr_bitmap &= 0x0f0ff015;
1960 } else {
1961 if (rssi_level == 1)
1962 ratr_bitmap &= 0x0f0f0000;
1963 else if (rssi_level == 2)
1964 ratr_bitmap &= 0x0f0ff000;
1965 else
1966 ratr_bitmap &= 0x0f0ff005;
1967 }
1968 }
1969 }
1970 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1971 (!curtxbw_40mhz && curshortgi_20mhz)) {
1972
1973 if (macid == 0)
1974 shortgi = true;
1975 else if (macid == 1)
1976 shortgi = false;
1977 }
1978 break;
1979 default:
1980 ratr_index = RATR_INX_WIRELESS_NGB;
1981
1982 if (rtlphy->rf_type == RF_1T2R)
1983 ratr_bitmap &= 0x000ff0ff;
1984 else
1985 ratr_bitmap &= 0x0f0ff0ff;
1986 break;
1987 }
1988
1989 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
1990 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1991 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1992 "ratr_bitmap :%x value0:%x value1:%x\n",
1993 ratr_bitmap, value[0], value[1]);
1994 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
1995 if (macid != 0)
1996 sta_entry->ratr_index = ratr_index;
1997 }
1998
rtl92de_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)1999 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2000 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2001 {
2002 struct rtl_priv *rtlpriv = rtl_priv(hw);
2003
2004 if (rtlpriv->dm.useramask)
2005 rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2006 else
2007 rtl92de_update_hal_rate_table(hw, sta);
2008 }
2009
rtl92de_update_channel_access_setting(struct ieee80211_hw * hw)2010 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2011 {
2012 struct rtl_priv *rtlpriv = rtl_priv(hw);
2013 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2014 u16 sifs_timer;
2015
2016 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2017 &mac->slot_time);
2018 if (!mac->ht_enable)
2019 sifs_timer = 0x0a0a;
2020 else
2021 sifs_timer = 0x1010;
2022 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2023 }
2024
rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2025 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2026 {
2027 struct rtl_priv *rtlpriv = rtl_priv(hw);
2028 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2029 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2030 enum rf_pwrstate e_rfpowerstate_toset;
2031 u8 u1tmp;
2032 bool actuallyset = false;
2033 unsigned long flag;
2034
2035 if (rtlpci->being_init_adapter)
2036 return false;
2037 if (ppsc->swrf_processing)
2038 return false;
2039 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2040 if (ppsc->rfchange_inprogress) {
2041 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2042 return false;
2043 } else {
2044 ppsc->rfchange_inprogress = true;
2045 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2046 }
2047 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2048 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2049 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2050 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2051 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2052 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2053 "GPIOChangeRF - HW Radio ON, RF ON\n");
2054 e_rfpowerstate_toset = ERFON;
2055 ppsc->hwradiooff = false;
2056 actuallyset = true;
2057 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2058 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2059 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2060 e_rfpowerstate_toset = ERFOFF;
2061 ppsc->hwradiooff = true;
2062 actuallyset = true;
2063 }
2064 if (actuallyset) {
2065 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2066 ppsc->rfchange_inprogress = false;
2067 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2068 } else {
2069 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2070 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2071 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2072 ppsc->rfchange_inprogress = false;
2073 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2074 }
2075 *valid = 1;
2076 return !ppsc->hwradiooff;
2077 }
2078
rtl92de_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2079 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2080 u8 *p_macaddr, bool is_group, u8 enc_algo,
2081 bool is_wepkey, bool clear_all)
2082 {
2083 struct rtl_priv *rtlpriv = rtl_priv(hw);
2084 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2085 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2086 u8 *macaddr = p_macaddr;
2087 u32 entry_id;
2088 bool is_pairwise = false;
2089 static u8 cam_const_addr[4][6] = {
2090 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2091 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2092 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2093 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2094 };
2095 static u8 cam_const_broad[] = {
2096 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2097 };
2098
2099 if (clear_all) {
2100 u8 idx;
2101 u8 cam_offset = 0;
2102 u8 clear_number = 5;
2103 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2104 for (idx = 0; idx < clear_number; idx++) {
2105 rtl_cam_mark_invalid(hw, cam_offset + idx);
2106 rtl_cam_empty_entry(hw, cam_offset + idx);
2107
2108 if (idx < 5) {
2109 memset(rtlpriv->sec.key_buf[idx], 0,
2110 MAX_KEY_LEN);
2111 rtlpriv->sec.key_len[idx] = 0;
2112 }
2113 }
2114 } else {
2115 switch (enc_algo) {
2116 case WEP40_ENCRYPTION:
2117 enc_algo = CAM_WEP40;
2118 break;
2119 case WEP104_ENCRYPTION:
2120 enc_algo = CAM_WEP104;
2121 break;
2122 case TKIP_ENCRYPTION:
2123 enc_algo = CAM_TKIP;
2124 break;
2125 case AESCCMP_ENCRYPTION:
2126 enc_algo = CAM_AES;
2127 break;
2128 default:
2129 pr_err("switch case %#x not processed\n",
2130 enc_algo);
2131 enc_algo = CAM_TKIP;
2132 break;
2133 }
2134 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2135 macaddr = cam_const_addr[key_index];
2136 entry_id = key_index;
2137 } else {
2138 if (is_group) {
2139 macaddr = cam_const_broad;
2140 entry_id = key_index;
2141 } else {
2142 if (mac->opmode == NL80211_IFTYPE_AP) {
2143 entry_id = rtl_cam_get_free_entry(hw,
2144 p_macaddr);
2145 if (entry_id >= TOTAL_CAM_ENTRY) {
2146 pr_err("Can not find free hw security cam entry\n");
2147 return;
2148 }
2149 } else {
2150 entry_id = CAM_PAIRWISE_KEY_POSITION;
2151 }
2152 key_index = PAIRWISE_KEYIDX;
2153 is_pairwise = true;
2154 }
2155 }
2156 if (rtlpriv->sec.key_len[key_index] == 0) {
2157 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2158 "delete one entry, entry_id is %d\n",
2159 entry_id);
2160 if (mac->opmode == NL80211_IFTYPE_AP)
2161 rtl_cam_del_entry(hw, p_macaddr);
2162 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2163 } else {
2164 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2165 "The insert KEY length is %d\n",
2166 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2167 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2168 "The insert KEY is %x %x\n",
2169 rtlpriv->sec.key_buf[0][0],
2170 rtlpriv->sec.key_buf[0][1]);
2171 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2172 "add one entry\n");
2173 if (is_pairwise) {
2174 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2175 "Pairwise Key content",
2176 rtlpriv->sec.pairwise_key,
2177 rtlpriv->
2178 sec.key_len[PAIRWISE_KEYIDX]);
2179 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2180 "set Pairwise key\n");
2181 rtl_cam_add_one_entry(hw, macaddr, key_index,
2182 entry_id, enc_algo,
2183 CAM_CONFIG_NO_USEDK,
2184 rtlpriv->
2185 sec.key_buf[key_index]);
2186 } else {
2187 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2188 "set group key\n");
2189 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2190 rtl_cam_add_one_entry(hw,
2191 rtlefuse->dev_addr,
2192 PAIRWISE_KEYIDX,
2193 CAM_PAIRWISE_KEY_POSITION,
2194 enc_algo, CAM_CONFIG_NO_USEDK,
2195 rtlpriv->sec.key_buf[entry_id]);
2196 }
2197 rtl_cam_add_one_entry(hw, macaddr, key_index,
2198 entry_id, enc_algo,
2199 CAM_CONFIG_NO_USEDK,
2200 rtlpriv->sec.key_buf
2201 [entry_id]);
2202 }
2203 }
2204 }
2205 }
2206
rtl92de_suspend(struct ieee80211_hw * hw)2207 void rtl92de_suspend(struct ieee80211_hw *hw)
2208 {
2209 struct rtl_priv *rtlpriv = rtl_priv(hw);
2210
2211 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2212 REG_MAC_PHY_CTRL_NORMAL);
2213 }
2214
rtl92de_resume(struct ieee80211_hw * hw)2215 void rtl92de_resume(struct ieee80211_hw *hw)
2216 {
2217 struct rtl_priv *rtlpriv = rtl_priv(hw);
2218
2219 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2220 rtlpriv->rtlhal.macphyctl_reg);
2221 }
2222