1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3 
4 #ifndef __SDW_INTEL_LOCAL_H
5 #define __SDW_INTEL_LOCAL_H
6 
7 struct hdac_bus;
8 
9 /**
10  * struct sdw_intel_link_res - Soundwire Intel link resource structure,
11  * typically populated by the controller driver.
12  * @hw_ops: platform-specific ops
13  * @mmio_base: mmio base of SoundWire registers
14  * @registers: Link IO registers base
15  * @ip_offset: offset for MCP_IP registers
16  * @shim: Audio shim pointer
17  * @shim_vs: Audio vendor-specific shim pointer
18  * @alh: ALH (Audio Link Hub) pointer
19  * @irq: Interrupt line
20  * @ops: Shim callback ops
21  * @dev: device implementing hw_params and free callbacks
22  * @shim_lock: mutex to handle access to shared SHIM registers
23  * @shim_mask: global pointer to check SHIM register initialization
24  * @clock_stop_quirks: mask defining requested behavior on pm_suspend
25  * @link_mask: global mask needed for power-up/down sequences
26  * @cdns: Cadence master descriptor
27  * @list: used to walk-through all masters exposed by the same controller
28  * @hbus: hdac_bus pointer, needed for power management
29  */
30 struct sdw_intel_link_res {
31 	const struct sdw_intel_hw_ops *hw_ops;
32 
33 	void __iomem *mmio_base; /* not strictly needed, useful for debug */
34 	void __iomem *registers;
35 	u32 ip_offset;
36 	void __iomem *shim;
37 	void __iomem *shim_vs;
38 	void __iomem *alh;
39 	int irq;
40 	const struct sdw_intel_ops *ops;
41 	struct device *dev;
42 	struct mutex *shim_lock; /* protect shared registers */
43 	u32 *shim_mask;
44 	u32 clock_stop_quirks;
45 	u32 link_mask;
46 	struct sdw_cdns *cdns;
47 	struct list_head list;
48 	struct hdac_bus *hbus;
49 };
50 
51 /**
52  * struct sdw_intel_bpt - SoundWire Intel BPT context
53  * @bpt_tx_stream: BPT TX stream
54  * @dmab_tx_bdl: BPT TX buffer descriptor list
55  * @bpt_rx_stream: BPT RX stream
56  * @dmab_rx_bdl: BPT RX buffer descriptor list
57  * @pdi0_buffer_size: PDI0 buffer size
58  * @pdi1_buffer_size: PDI1 buffer size
59  * @num_frames: number of frames
60  * @data_per_frame: data per frame
61  */
62 struct sdw_intel_bpt {
63 	struct hdac_ext_stream *bpt_tx_stream;
64 	struct snd_dma_buffer dmab_tx_bdl;
65 	struct hdac_ext_stream *bpt_rx_stream;
66 	struct snd_dma_buffer dmab_rx_bdl;
67 	unsigned int pdi0_buffer_size;
68 	unsigned int pdi1_buffer_size;
69 	unsigned int num_frames;
70 	unsigned int data_per_frame;
71 };
72 
73 struct sdw_intel {
74 	struct sdw_cdns cdns;
75 	int instance;
76 	struct sdw_intel_link_res *link_res;
77 	bool startup_done;
78 	struct sdw_intel_bpt bpt_ctx;
79 #ifdef CONFIG_DEBUG_FS
80 	struct dentry *debugfs;
81 #endif
82 };
83 
84 struct sdw_intel_prop {
85 	u16 clde;
86 	u16 doaise2;
87 	u16 dodse2;
88 	u16 clds;
89 	u16 clss;
90 	u16 doaise;
91 	u16 doais;
92 	u16 dodse;
93 	u16 dods;
94 };
95 
96 enum intel_pdi_type {
97 	INTEL_PDI_IN = 0,
98 	INTEL_PDI_OUT = 1,
99 	INTEL_PDI_BD = 2,
100 };
101 
102 /*
103  * Read, write helpers for HW registers
104  */
intel_readl(void __iomem * base,int offset)105 static inline int intel_readl(void __iomem *base, int offset)
106 {
107 	return readl(base + offset);
108 }
109 
intel_writel(void __iomem * base,int offset,int value)110 static inline void intel_writel(void __iomem *base, int offset, int value)
111 {
112 	writel(value, base + offset);
113 }
114 
intel_readw(void __iomem * base,int offset)115 static inline u16 intel_readw(void __iomem *base, int offset)
116 {
117 	return readw(base + offset);
118 }
119 
intel_writew(void __iomem * base,int offset,u16 value)120 static inline void intel_writew(void __iomem *base, int offset, u16 value)
121 {
122 	writew(value, base + offset);
123 }
124 
125 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
126 
127 #define INTEL_MASTER_RESET_ITERATIONS	10
128 
129 #define SDW_INTEL_DELAYED_ENUMERATION_MS	100
130 
131 #define SDW_INTEL_CHECK_OPS(sdw, cb)	((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \
132 					 (sdw)->link_res->hw_ops->cb)
133 #define SDW_INTEL_OPS(sdw, cb)		((sdw)->link_res->hw_ops->cb)
134 
135 #ifdef CONFIG_DEBUG_FS
136 void intel_ace2x_debugfs_init(struct sdw_intel *sdw);
137 void intel_ace2x_debugfs_exit(struct sdw_intel *sdw);
138 #else
intel_ace2x_debugfs_init(struct sdw_intel * sdw)139 static inline void intel_ace2x_debugfs_init(struct sdw_intel *sdw) {}
intel_ace2x_debugfs_exit(struct sdw_intel * sdw)140 static inline void intel_ace2x_debugfs_exit(struct sdw_intel *sdw) {}
141 #endif
142 
sdw_intel_debugfs_init(struct sdw_intel * sdw)143 static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw)
144 {
145 	if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init))
146 		SDW_INTEL_OPS(sdw, debugfs_init)(sdw);
147 }
148 
sdw_intel_debugfs_exit(struct sdw_intel * sdw)149 static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw)
150 {
151 	if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit))
152 		SDW_INTEL_OPS(sdw, debugfs_exit)(sdw);
153 }
154 
sdw_intel_register_dai(struct sdw_intel * sdw)155 static inline int sdw_intel_register_dai(struct sdw_intel *sdw)
156 {
157 	if (SDW_INTEL_CHECK_OPS(sdw, register_dai))
158 		return SDW_INTEL_OPS(sdw, register_dai)(sdw);
159 	return -ENOTSUPP;
160 }
161 
sdw_intel_check_clock_stop(struct sdw_intel * sdw)162 static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw)
163 {
164 	if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop))
165 		SDW_INTEL_OPS(sdw, check_clock_stop)(sdw);
166 }
167 
sdw_intel_start_bus(struct sdw_intel * sdw)168 static inline int sdw_intel_start_bus(struct sdw_intel *sdw)
169 {
170 	if (SDW_INTEL_CHECK_OPS(sdw, start_bus))
171 		return SDW_INTEL_OPS(sdw, start_bus)(sdw);
172 	return -ENOTSUPP;
173 }
174 
sdw_intel_start_bus_after_reset(struct sdw_intel * sdw)175 static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw)
176 {
177 	if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset))
178 		return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw);
179 	return -ENOTSUPP;
180 }
181 
sdw_intel_start_bus_after_clock_stop(struct sdw_intel * sdw)182 static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw)
183 {
184 	if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop))
185 		return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw);
186 	return -ENOTSUPP;
187 }
188 
sdw_intel_stop_bus(struct sdw_intel * sdw,bool clock_stop)189 static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop)
190 {
191 	if (SDW_INTEL_CHECK_OPS(sdw, stop_bus))
192 		return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop);
193 	return -ENOTSUPP;
194 }
195 
sdw_intel_link_power_up(struct sdw_intel * sdw)196 static inline int sdw_intel_link_power_up(struct sdw_intel *sdw)
197 {
198 	if (SDW_INTEL_CHECK_OPS(sdw, link_power_up))
199 		return SDW_INTEL_OPS(sdw, link_power_up)(sdw);
200 	return -ENOTSUPP;
201 }
202 
sdw_intel_link_power_down(struct sdw_intel * sdw)203 static inline int sdw_intel_link_power_down(struct sdw_intel *sdw)
204 {
205 	if (SDW_INTEL_CHECK_OPS(sdw, link_power_down))
206 		return SDW_INTEL_OPS(sdw, link_power_down)(sdw);
207 	return -ENOTSUPP;
208 }
209 
sdw_intel_shim_check_wake(struct sdw_intel * sdw)210 static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw)
211 {
212 	if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake))
213 		return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw);
214 	return -ENOTSUPP;
215 }
216 
sdw_intel_shim_wake(struct sdw_intel * sdw,bool wake_enable)217 static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
218 {
219 	if (SDW_INTEL_CHECK_OPS(sdw, shim_wake))
220 		SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable);
221 }
222 
sdw_intel_sync_arm(struct sdw_intel * sdw)223 static inline void sdw_intel_sync_arm(struct sdw_intel *sdw)
224 {
225 	if (SDW_INTEL_CHECK_OPS(sdw, sync_arm))
226 		SDW_INTEL_OPS(sdw, sync_arm)(sdw);
227 }
228 
sdw_intel_sync_go_unlocked(struct sdw_intel * sdw)229 static inline int sdw_intel_sync_go_unlocked(struct sdw_intel *sdw)
230 {
231 	if (SDW_INTEL_CHECK_OPS(sdw, sync_go_unlocked))
232 		return SDW_INTEL_OPS(sdw, sync_go_unlocked)(sdw);
233 	return -ENOTSUPP;
234 }
235 
sdw_intel_sync_go(struct sdw_intel * sdw)236 static inline int sdw_intel_sync_go(struct sdw_intel *sdw)
237 {
238 	if (SDW_INTEL_CHECK_OPS(sdw, sync_go))
239 		return SDW_INTEL_OPS(sdw, sync_go)(sdw);
240 	return -ENOTSUPP;
241 }
242 
sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel * sdw)243 static inline bool sdw_intel_sync_check_cmdsync_unlocked(struct sdw_intel *sdw)
244 {
245 	if (SDW_INTEL_CHECK_OPS(sdw, sync_check_cmdsync_unlocked))
246 		return SDW_INTEL_OPS(sdw, sync_check_cmdsync_unlocked)(sdw);
247 	return false;
248 }
249 
sdw_intel_get_link_count(struct sdw_intel * sdw)250 static inline int sdw_intel_get_link_count(struct sdw_intel *sdw)
251 {
252 	if (SDW_INTEL_CHECK_OPS(sdw, get_link_count))
253 		return SDW_INTEL_OPS(sdw, get_link_count)(sdw);
254 	return 4; /* default on older generations */
255 }
256 
257 /* common bus management */
258 int intel_start_bus(struct sdw_intel *sdw);
259 int intel_start_bus_after_reset(struct sdw_intel *sdw);
260 void intel_check_clock_stop(struct sdw_intel *sdw);
261 int intel_start_bus_after_clock_stop(struct sdw_intel *sdw);
262 int intel_stop_bus(struct sdw_intel *sdw, bool clock_stop);
263 
264 /* common bank switch routines */
265 int intel_pre_bank_switch(struct sdw_intel *sdw);
266 int intel_post_bank_switch(struct sdw_intel *sdw);
267 
268 #endif /* __SDW_INTEL_LOCAL_H */
269