1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI Camera Access Layer (CAL) - Driver
4 *
5 * Copyright (c) 2015-2020 Texas Instruments Inc.
6 *
7 * Authors:
8 * Benoit Parrot <bparrot@ti.com>
9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 */
11
12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22
23 #include <media/media-device.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-common.h>
26 #include <media/v4l2-device.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
29
30 #include "cal.h"
31 #include "cal_regs.h"
32
33 MODULE_DESCRIPTION("TI CAL driver");
34 MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>");
35 MODULE_LICENSE("GPL v2");
36 MODULE_VERSION("0.1.0");
37
38 int cal_video_nr = -1;
39 module_param_named(video_nr, cal_video_nr, uint, 0644);
40 MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect");
41
42 unsigned int cal_debug;
43 module_param_named(debug, cal_debug, uint, 0644);
44 MODULE_PARM_DESC(debug, "activates debug info");
45
46 #ifdef CONFIG_VIDEO_TI_CAL_MC
47 #define CAL_MC_API_DEFAULT 1
48 #else
49 #define CAL_MC_API_DEFAULT 0
50 #endif
51
52 bool cal_mc_api = CAL_MC_API_DEFAULT;
53 module_param_named(mc_api, cal_mc_api, bool, 0444);
54 MODULE_PARM_DESC(mc_api, "activates the MC API");
55
56 /* ------------------------------------------------------------------
57 * Format Handling
58 * ------------------------------------------------------------------
59 */
60
61 const struct cal_format_info cal_formats[] = {
62 {
63 .fourcc = V4L2_PIX_FMT_YUYV,
64 .code = MEDIA_BUS_FMT_YUYV8_1X16,
65 .bpp = 16,
66 }, {
67 .fourcc = V4L2_PIX_FMT_UYVY,
68 .code = MEDIA_BUS_FMT_UYVY8_1X16,
69 .bpp = 16,
70 }, {
71 .fourcc = V4L2_PIX_FMT_YVYU,
72 .code = MEDIA_BUS_FMT_YVYU8_1X16,
73 .bpp = 16,
74 }, {
75 .fourcc = V4L2_PIX_FMT_VYUY,
76 .code = MEDIA_BUS_FMT_VYUY8_1X16,
77 .bpp = 16,
78 }, {
79 .fourcc = V4L2_PIX_FMT_RGB565,
80 .code = MEDIA_BUS_FMT_RGB565_1X16,
81 .bpp = 16,
82 }, {
83 .fourcc = V4L2_PIX_FMT_SBGGR8,
84 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
85 .bpp = 8,
86 }, {
87 .fourcc = V4L2_PIX_FMT_SGBRG8,
88 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
89 .bpp = 8,
90 }, {
91 .fourcc = V4L2_PIX_FMT_SGRBG8,
92 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
93 .bpp = 8,
94 }, {
95 .fourcc = V4L2_PIX_FMT_SRGGB8,
96 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
97 .bpp = 8,
98 }, {
99 .fourcc = V4L2_PIX_FMT_SBGGR10,
100 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
101 .bpp = 10,
102 }, {
103 .fourcc = V4L2_PIX_FMT_SGBRG10,
104 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
105 .bpp = 10,
106 }, {
107 .fourcc = V4L2_PIX_FMT_SGRBG10,
108 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
109 .bpp = 10,
110 }, {
111 .fourcc = V4L2_PIX_FMT_SRGGB10,
112 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
113 .bpp = 10,
114 }, {
115 .fourcc = V4L2_PIX_FMT_SBGGR12,
116 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
117 .bpp = 12,
118 }, {
119 .fourcc = V4L2_PIX_FMT_SGBRG12,
120 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
121 .bpp = 12,
122 }, {
123 .fourcc = V4L2_PIX_FMT_SGRBG12,
124 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
125 .bpp = 12,
126 }, {
127 .fourcc = V4L2_PIX_FMT_SRGGB12,
128 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
129 .bpp = 12,
130 },
131 };
132
133 const unsigned int cal_num_formats = ARRAY_SIZE(cal_formats);
134
cal_format_by_fourcc(u32 fourcc)135 const struct cal_format_info *cal_format_by_fourcc(u32 fourcc)
136 {
137 unsigned int i;
138
139 for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) {
140 if (cal_formats[i].fourcc == fourcc)
141 return &cal_formats[i];
142 }
143
144 return NULL;
145 }
146
cal_format_by_code(u32 code)147 const struct cal_format_info *cal_format_by_code(u32 code)
148 {
149 unsigned int i;
150
151 for (i = 0; i < ARRAY_SIZE(cal_formats); ++i) {
152 if (cal_formats[i].code == code)
153 return &cal_formats[i];
154 }
155
156 return NULL;
157 }
158
159 /* ------------------------------------------------------------------
160 * Platform Data
161 * ------------------------------------------------------------------
162 */
163
164 static const struct cal_camerarx_data dra72x_cal_camerarx[] = {
165 {
166 .fields = {
167 [F_CTRLCLKEN] = { 10, 10 },
168 [F_CAMMODE] = { 11, 12 },
169 [F_LANEENABLE] = { 13, 16 },
170 [F_CSI_MODE] = { 17, 17 },
171 },
172 .num_lanes = 4,
173 },
174 {
175 .fields = {
176 [F_CTRLCLKEN] = { 0, 0 },
177 [F_CAMMODE] = { 1, 2 },
178 [F_LANEENABLE] = { 3, 4 },
179 [F_CSI_MODE] = { 5, 5 },
180 },
181 .num_lanes = 2,
182 },
183 };
184
185 static const struct cal_data dra72x_cal_data = {
186 .camerarx = dra72x_cal_camerarx,
187 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
188 };
189
190 static const struct cal_data dra72x_es1_cal_data = {
191 .camerarx = dra72x_cal_camerarx,
192 .num_csi2_phy = ARRAY_SIZE(dra72x_cal_camerarx),
193 .flags = DRA72_CAL_PRE_ES2_LDO_DISABLE,
194 };
195
196 static const struct cal_camerarx_data dra76x_cal_csi_phy[] = {
197 {
198 .fields = {
199 [F_CTRLCLKEN] = { 8, 8 },
200 [F_CAMMODE] = { 9, 10 },
201 [F_CSI_MODE] = { 11, 11 },
202 [F_LANEENABLE] = { 27, 31 },
203 },
204 .num_lanes = 5,
205 },
206 {
207 .fields = {
208 [F_CTRLCLKEN] = { 0, 0 },
209 [F_CAMMODE] = { 1, 2 },
210 [F_CSI_MODE] = { 3, 3 },
211 [F_LANEENABLE] = { 24, 26 },
212 },
213 .num_lanes = 3,
214 },
215 };
216
217 static const struct cal_data dra76x_cal_data = {
218 .camerarx = dra76x_cal_csi_phy,
219 .num_csi2_phy = ARRAY_SIZE(dra76x_cal_csi_phy),
220 };
221
222 static const struct cal_camerarx_data am654_cal_csi_phy[] = {
223 {
224 .fields = {
225 [F_CTRLCLKEN] = { 15, 15 },
226 [F_CAMMODE] = { 24, 25 },
227 [F_LANEENABLE] = { 0, 4 },
228 },
229 .num_lanes = 5,
230 },
231 };
232
233 static const struct cal_data am654_cal_data = {
234 .camerarx = am654_cal_csi_phy,
235 .num_csi2_phy = ARRAY_SIZE(am654_cal_csi_phy),
236 };
237
238 /* ------------------------------------------------------------------
239 * I/O Register Accessors
240 * ------------------------------------------------------------------
241 */
242
cal_quickdump_regs(struct cal_dev * cal)243 void cal_quickdump_regs(struct cal_dev *cal)
244 {
245 unsigned int i;
246
247 cal_info(cal, "CAL Registers @ 0x%pa:\n", &cal->res->start);
248 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
249 (__force const void *)cal->base,
250 resource_size(cal->res), false);
251
252 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
253 struct cal_camerarx *phy = cal->phy[i];
254
255 cal_info(cal, "CSI2 Core %u Registers @ %pa:\n", i,
256 &phy->res->start);
257 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
258 (__force const void *)phy->base,
259 resource_size(phy->res),
260 false);
261 }
262 }
263
264 /* ------------------------------------------------------------------
265 * Context Management
266 * ------------------------------------------------------------------
267 */
268
269 #define CAL_MAX_PIX_PROC 4
270
cal_reserve_pix_proc(struct cal_dev * cal)271 static int cal_reserve_pix_proc(struct cal_dev *cal)
272 {
273 unsigned long ret;
274
275 spin_lock(&cal->v4l2_dev.lock);
276
277 ret = find_first_zero_bit(&cal->reserved_pix_proc_mask, CAL_MAX_PIX_PROC);
278
279 if (ret == CAL_MAX_PIX_PROC) {
280 spin_unlock(&cal->v4l2_dev.lock);
281 return -ENOSPC;
282 }
283
284 cal->reserved_pix_proc_mask |= BIT(ret);
285
286 spin_unlock(&cal->v4l2_dev.lock);
287
288 return ret;
289 }
290
cal_release_pix_proc(struct cal_dev * cal,unsigned int pix_proc_num)291 static void cal_release_pix_proc(struct cal_dev *cal, unsigned int pix_proc_num)
292 {
293 spin_lock(&cal->v4l2_dev.lock);
294
295 cal->reserved_pix_proc_mask &= ~BIT(pix_proc_num);
296
297 spin_unlock(&cal->v4l2_dev.lock);
298 }
299
cal_ctx_csi2_config(struct cal_ctx * ctx)300 static void cal_ctx_csi2_config(struct cal_ctx *ctx)
301 {
302 u32 val;
303
304 val = cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx));
305 cal_set_field(&val, ctx->cport, CAL_CSI2_CTX_CPORT_MASK);
306 /*
307 * DT type: MIPI CSI-2 Specs
308 * 0x1: All - DT filter is disabled
309 * 0x24: RGB888 1 pixel = 3 bytes
310 * 0x2B: RAW10 4 pixels = 5 bytes
311 * 0x2A: RAW8 1 pixel = 1 byte
312 * 0x1E: YUV422 2 pixels = 4 bytes
313 */
314 cal_set_field(&val, ctx->datatype, CAL_CSI2_CTX_DT_MASK);
315 cal_set_field(&val, ctx->vc, CAL_CSI2_CTX_VC_MASK);
316 cal_set_field(&val, ctx->v_fmt.fmt.pix.height, CAL_CSI2_CTX_LINES_MASK);
317 cal_set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
318 cal_set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
319 CAL_CSI2_CTX_PACK_MODE_MASK);
320 cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), val);
321 ctx_dbg(3, ctx, "CAL_CSI2_CTX(%u, %u) = 0x%08x\n",
322 ctx->phy->instance, ctx->csi2_ctx,
323 cal_read(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx)));
324 }
325
cal_ctx_pix_proc_config(struct cal_ctx * ctx)326 static void cal_ctx_pix_proc_config(struct cal_ctx *ctx)
327 {
328 u32 val, extract, pack;
329
330 switch (ctx->fmtinfo->bpp) {
331 case 8:
332 extract = CAL_PIX_PROC_EXTRACT_B8;
333 pack = CAL_PIX_PROC_PACK_B8;
334 break;
335 case 10:
336 extract = CAL_PIX_PROC_EXTRACT_B10_MIPI;
337 pack = CAL_PIX_PROC_PACK_B16;
338 break;
339 case 12:
340 extract = CAL_PIX_PROC_EXTRACT_B12_MIPI;
341 pack = CAL_PIX_PROC_PACK_B16;
342 break;
343 case 16:
344 extract = CAL_PIX_PROC_EXTRACT_B16_LE;
345 pack = CAL_PIX_PROC_PACK_B16;
346 break;
347 default:
348 /*
349 * If you see this warning then it means that you added
350 * some new entry in the cal_formats[] array with a different
351 * bit per pixel values then the one supported below.
352 * Either add support for the new bpp value below or adjust
353 * the new entry to use one of the value below.
354 *
355 * Instead of failing here just use 8 bpp as a default.
356 */
357 dev_warn_once(ctx->cal->dev,
358 "%s:%d:%s: bpp:%d unsupported! Overwritten with 8.\n",
359 __FILE__, __LINE__, __func__, ctx->fmtinfo->bpp);
360 extract = CAL_PIX_PROC_EXTRACT_B8;
361 pack = CAL_PIX_PROC_PACK_B8;
362 break;
363 }
364
365 val = cal_read(ctx->cal, CAL_PIX_PROC(ctx->pix_proc));
366 cal_set_field(&val, extract, CAL_PIX_PROC_EXTRACT_MASK);
367 cal_set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);
368 cal_set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
369 cal_set_field(&val, pack, CAL_PIX_PROC_PACK_MASK);
370 cal_set_field(&val, ctx->cport, CAL_PIX_PROC_CPORT_MASK);
371 cal_set_field(&val, 1, CAL_PIX_PROC_EN_MASK);
372 cal_write(ctx->cal, CAL_PIX_PROC(ctx->pix_proc), val);
373 ctx_dbg(3, ctx, "CAL_PIX_PROC(%u) = 0x%08x\n", ctx->pix_proc,
374 cal_read(ctx->cal, CAL_PIX_PROC(ctx->pix_proc)));
375 }
376
cal_ctx_wr_dma_config(struct cal_ctx * ctx)377 static void cal_ctx_wr_dma_config(struct cal_ctx *ctx)
378 {
379 unsigned int stride = ctx->v_fmt.fmt.pix.bytesperline;
380 u32 val;
381
382 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
383 cal_set_field(&val, ctx->cport, CAL_WR_DMA_CTRL_CPORT_MASK);
384 cal_set_field(&val, ctx->v_fmt.fmt.pix.height,
385 CAL_WR_DMA_CTRL_YSIZE_MASK);
386 cal_set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
387 CAL_WR_DMA_CTRL_DTAG_MASK);
388 cal_set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
389 CAL_WR_DMA_CTRL_PATTERN_MASK);
390 cal_set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK);
391 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
392 ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->dma_ctx,
393 cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx)));
394
395 cal_write_field(ctx->cal, CAL_WR_DMA_OFST(ctx->dma_ctx),
396 stride / 16, CAL_WR_DMA_OFST_MASK);
397 ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->dma_ctx,
398 cal_read(ctx->cal, CAL_WR_DMA_OFST(ctx->dma_ctx)));
399
400 val = cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx));
401 /* 64 bit word means no skipping */
402 cal_set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);
403 /*
404 * The XSIZE field is expressed in 64-bit units and prevents overflows
405 * in case of synchronization issues by limiting the number of bytes
406 * written per line.
407 */
408 cal_set_field(&val, stride / 8, CAL_WR_DMA_XSIZE_MASK);
409 cal_write(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx), val);
410 ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->dma_ctx,
411 cal_read(ctx->cal, CAL_WR_DMA_XSIZE(ctx->dma_ctx)));
412 }
413
cal_ctx_set_dma_addr(struct cal_ctx * ctx,dma_addr_t addr)414 void cal_ctx_set_dma_addr(struct cal_ctx *ctx, dma_addr_t addr)
415 {
416 cal_write(ctx->cal, CAL_WR_DMA_ADDR(ctx->dma_ctx), addr);
417 }
418
cal_ctx_wr_dma_enable(struct cal_ctx * ctx)419 static void cal_ctx_wr_dma_enable(struct cal_ctx *ctx)
420 {
421 u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
422
423 cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
424 CAL_WR_DMA_CTRL_MODE_MASK);
425 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
426 }
427
cal_ctx_wr_dma_disable(struct cal_ctx * ctx)428 static void cal_ctx_wr_dma_disable(struct cal_ctx *ctx)
429 {
430 u32 val = cal_read(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx));
431
432 cal_set_field(&val, CAL_WR_DMA_CTRL_MODE_DIS,
433 CAL_WR_DMA_CTRL_MODE_MASK);
434 cal_write(ctx->cal, CAL_WR_DMA_CTRL(ctx->dma_ctx), val);
435 }
436
cal_ctx_wr_dma_stopped(struct cal_ctx * ctx)437 static bool cal_ctx_wr_dma_stopped(struct cal_ctx *ctx)
438 {
439 bool stopped;
440
441 spin_lock_irq(&ctx->dma.lock);
442 stopped = ctx->dma.state == CAL_DMA_STOPPED;
443 spin_unlock_irq(&ctx->dma.lock);
444
445 return stopped;
446 }
447
448 static int
cal_get_remote_frame_desc_entry(struct cal_ctx * ctx,struct v4l2_mbus_frame_desc_entry * entry)449 cal_get_remote_frame_desc_entry(struct cal_ctx *ctx,
450 struct v4l2_mbus_frame_desc_entry *entry)
451 {
452 struct v4l2_mbus_frame_desc fd;
453 struct media_pad *phy_source_pad;
454 int ret;
455
456 phy_source_pad = media_pad_remote_pad_first(&ctx->pad);
457 if (!phy_source_pad)
458 return -ENODEV;
459
460 ret = v4l2_subdev_call(&ctx->phy->subdev, pad, get_frame_desc,
461 phy_source_pad->index, &fd);
462 if (ret)
463 return ret;
464
465 if (fd.num_entries != 1)
466 return -EINVAL;
467
468 *entry = fd.entry[0];
469
470 return 0;
471 }
472
cal_ctx_prepare(struct cal_ctx * ctx)473 int cal_ctx_prepare(struct cal_ctx *ctx)
474 {
475 struct v4l2_mbus_frame_desc_entry entry;
476 int ret;
477
478 ret = cal_get_remote_frame_desc_entry(ctx, &entry);
479
480 if (ret == -ENOIOCTLCMD) {
481 ctx->vc = 0;
482 ctx->datatype = CAL_CSI2_CTX_DT_ANY;
483 } else if (!ret) {
484 ctx_dbg(2, ctx, "Framedesc: len %u, vc %u, dt %#x\n",
485 entry.length, entry.bus.csi2.vc, entry.bus.csi2.dt);
486
487 ctx->vc = entry.bus.csi2.vc;
488 ctx->datatype = entry.bus.csi2.dt;
489 } else {
490 return ret;
491 }
492
493 ctx->use_pix_proc = !ctx->fmtinfo->meta;
494
495 if (ctx->use_pix_proc) {
496 ret = cal_reserve_pix_proc(ctx->cal);
497 if (ret < 0) {
498 ctx_err(ctx, "Failed to reserve pix proc: %d\n", ret);
499 return ret;
500 }
501
502 ctx->pix_proc = ret;
503 }
504
505 return 0;
506 }
507
cal_ctx_unprepare(struct cal_ctx * ctx)508 void cal_ctx_unprepare(struct cal_ctx *ctx)
509 {
510 if (ctx->use_pix_proc)
511 cal_release_pix_proc(ctx->cal, ctx->pix_proc);
512 }
513
cal_ctx_start(struct cal_ctx * ctx)514 void cal_ctx_start(struct cal_ctx *ctx)
515 {
516 struct cal_camerarx *phy = ctx->phy;
517
518 /*
519 * Reset the frame number & sequence number, but only if the
520 * virtual channel is not already in use.
521 */
522
523 spin_lock(&phy->vc_lock);
524
525 if (phy->vc_enable_count[ctx->vc]++ == 0) {
526 phy->vc_frame_number[ctx->vc] = 0;
527 phy->vc_sequence[ctx->vc] = 0;
528 }
529
530 spin_unlock(&phy->vc_lock);
531
532 ctx->dma.state = CAL_DMA_RUNNING;
533
534 /* Configure the CSI-2, pixel processing and write DMA contexts. */
535 cal_ctx_csi2_config(ctx);
536 if (ctx->use_pix_proc)
537 cal_ctx_pix_proc_config(ctx);
538 cal_ctx_wr_dma_config(ctx);
539
540 /* Enable IRQ_WDMA_END and IRQ_WDMA_START. */
541 cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(1),
542 CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
543 cal_write(ctx->cal, CAL_HL_IRQENABLE_SET(2),
544 CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
545
546 cal_ctx_wr_dma_enable(ctx);
547 }
548
cal_ctx_stop(struct cal_ctx * ctx)549 void cal_ctx_stop(struct cal_ctx *ctx)
550 {
551 struct cal_camerarx *phy = ctx->phy;
552 long time_left;
553
554 WARN_ON(phy->vc_enable_count[ctx->vc] == 0);
555
556 spin_lock(&phy->vc_lock);
557 phy->vc_enable_count[ctx->vc]--;
558 spin_unlock(&phy->vc_lock);
559
560 /*
561 * Request DMA stop and wait until it completes. If completion times
562 * out, forcefully disable the DMA.
563 */
564 spin_lock_irq(&ctx->dma.lock);
565 ctx->dma.state = CAL_DMA_STOP_REQUESTED;
566 spin_unlock_irq(&ctx->dma.lock);
567
568 time_left = wait_event_timeout(ctx->dma.wait, cal_ctx_wr_dma_stopped(ctx),
569 msecs_to_jiffies(500));
570 if (!time_left) {
571 ctx_err(ctx, "failed to disable dma cleanly\n");
572 cal_ctx_wr_dma_disable(ctx);
573 }
574
575 /* Disable IRQ_WDMA_END and IRQ_WDMA_START. */
576 cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(1),
577 CAL_HL_IRQ_WDMA_END_MASK(ctx->dma_ctx));
578 cal_write(ctx->cal, CAL_HL_IRQENABLE_CLR(2),
579 CAL_HL_IRQ_WDMA_START_MASK(ctx->dma_ctx));
580
581 ctx->dma.state = CAL_DMA_STOPPED;
582
583 /* Disable CSI2 context */
584 cal_write(ctx->cal, CAL_CSI2_CTX(ctx->phy->instance, ctx->csi2_ctx), 0);
585
586 /* Disable pix proc */
587 if (ctx->use_pix_proc)
588 cal_write(ctx->cal, CAL_PIX_PROC(ctx->pix_proc), 0);
589 }
590
591 /* ------------------------------------------------------------------
592 * IRQ Handling
593 * ------------------------------------------------------------------
594 */
595
596 /*
597 * Track a sequence number for each virtual channel, which is shared by
598 * all contexts using the same virtual channel. This is done using the
599 * CSI-2 frame number as a base.
600 */
cal_update_seq_number(struct cal_ctx * ctx)601 static void cal_update_seq_number(struct cal_ctx *ctx)
602 {
603 struct cal_dev *cal = ctx->cal;
604 struct cal_camerarx *phy = ctx->phy;
605 u16 prev_frame_num, frame_num;
606 u8 vc = ctx->vc;
607
608 frame_num =
609 cal_read(cal, CAL_CSI2_STATUS(phy->instance, ctx->csi2_ctx)) &
610 0xffff;
611
612 if (phy->vc_frame_number[vc] != frame_num) {
613 prev_frame_num = phy->vc_frame_number[vc];
614
615 if (prev_frame_num >= frame_num)
616 phy->vc_sequence[vc] += 1;
617 else
618 phy->vc_sequence[vc] += frame_num - prev_frame_num;
619
620 phy->vc_frame_number[vc] = frame_num;
621 }
622 }
623
cal_irq_wdma_start(struct cal_ctx * ctx)624 static inline void cal_irq_wdma_start(struct cal_ctx *ctx)
625 {
626 spin_lock(&ctx->dma.lock);
627
628 if (ctx->dma.state == CAL_DMA_STOP_REQUESTED) {
629 /*
630 * If a stop is requested, disable the write DMA context
631 * immediately. The CAL_WR_DMA_CTRL_j.MODE field is shadowed,
632 * the current frame will complete and the DMA will then stop.
633 */
634 cal_ctx_wr_dma_disable(ctx);
635 ctx->dma.state = CAL_DMA_STOP_PENDING;
636 } else if (!list_empty(&ctx->dma.queue) && !ctx->dma.pending) {
637 /*
638 * Otherwise, if a new buffer is available, queue it to the
639 * hardware.
640 */
641 struct cal_buffer *buf;
642 dma_addr_t addr;
643
644 buf = list_first_entry(&ctx->dma.queue, struct cal_buffer,
645 list);
646 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
647 cal_ctx_set_dma_addr(ctx, addr);
648
649 ctx->dma.pending = buf;
650 list_del(&buf->list);
651 }
652
653 spin_unlock(&ctx->dma.lock);
654
655 cal_update_seq_number(ctx);
656 }
657
cal_irq_wdma_end(struct cal_ctx * ctx)658 static inline void cal_irq_wdma_end(struct cal_ctx *ctx)
659 {
660 struct cal_buffer *buf = NULL;
661
662 spin_lock(&ctx->dma.lock);
663
664 /* If the DMA context was stopping, it is now stopped. */
665 if (ctx->dma.state == CAL_DMA_STOP_PENDING) {
666 ctx->dma.state = CAL_DMA_STOPPED;
667 wake_up(&ctx->dma.wait);
668 }
669
670 /* If a new buffer was queued, complete the current buffer. */
671 if (ctx->dma.pending) {
672 buf = ctx->dma.active;
673 ctx->dma.active = ctx->dma.pending;
674 ctx->dma.pending = NULL;
675 }
676
677 spin_unlock(&ctx->dma.lock);
678
679 if (buf) {
680 buf->vb.vb2_buf.timestamp = ktime_get_ns();
681 buf->vb.field = ctx->v_fmt.fmt.pix.field;
682 buf->vb.sequence = ctx->phy->vc_sequence[ctx->vc];
683
684 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
685 }
686 }
687
cal_irq_handle_wdma(struct cal_ctx * ctx,bool start,bool end)688 static void cal_irq_handle_wdma(struct cal_ctx *ctx, bool start, bool end)
689 {
690 /*
691 * CAL HW interrupts are inherently racy. If we get both start and end
692 * interrupts, we don't know what has happened: did the DMA for a single
693 * frame start and end, or did one frame end and a new frame start?
694 *
695 * Usually for normal pixel frames we get the interrupts separately. If
696 * we do get both, we have to guess. The assumption in the code below is
697 * that the active vertical area is larger than the blanking vertical
698 * area, and thus it is more likely that we get the end of the old frame
699 * and the start of a new frame.
700 *
701 * However, for embedded data, which is only a few lines high, we always
702 * get both interrupts. Here the assumption is that we get both for the
703 * same frame.
704 */
705 if (ctx->v_fmt.fmt.pix.height < 10) {
706 if (start)
707 cal_irq_wdma_start(ctx);
708
709 if (end)
710 cal_irq_wdma_end(ctx);
711 } else {
712 if (end)
713 cal_irq_wdma_end(ctx);
714
715 if (start)
716 cal_irq_wdma_start(ctx);
717 }
718 }
719
cal_irq(int irq_cal,void * data)720 static irqreturn_t cal_irq(int irq_cal, void *data)
721 {
722 struct cal_dev *cal = data;
723 u32 status[3];
724 unsigned int i;
725
726 for (i = 0; i < 3; ++i) {
727 status[i] = cal_read(cal, CAL_HL_IRQSTATUS(i));
728 if (status[i])
729 cal_write(cal, CAL_HL_IRQSTATUS(i), status[i]);
730 }
731
732 if (status[0]) {
733 if (status[0] & CAL_HL_IRQ_OCPO_ERR_MASK)
734 dev_err_ratelimited(cal->dev, "OCPO ERROR\n");
735
736 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
737 if (status[0] & CAL_HL_IRQ_CIO_MASK(i)) {
738 u32 cio_stat = cal_read(cal,
739 CAL_CSI2_COMPLEXIO_IRQSTATUS(i));
740
741 dev_err_ratelimited(cal->dev,
742 "CIO%u error: %#08x\n", i, cio_stat);
743
744 cal_write(cal, CAL_CSI2_COMPLEXIO_IRQSTATUS(i),
745 cio_stat);
746 }
747
748 if (status[0] & CAL_HL_IRQ_VC_MASK(i)) {
749 u32 vc_stat = cal_read(cal, CAL_CSI2_VC_IRQSTATUS(i));
750
751 dev_err_ratelimited(cal->dev,
752 "CIO%u VC error: %#08x\n",
753 i, vc_stat);
754
755 cal_write(cal, CAL_CSI2_VC_IRQSTATUS(i), vc_stat);
756 }
757 }
758 }
759
760 for (i = 0; i < cal->num_contexts; ++i) {
761 bool end = !!(status[1] & CAL_HL_IRQ_WDMA_END_MASK(i));
762 bool start = !!(status[2] & CAL_HL_IRQ_WDMA_START_MASK(i));
763
764 if (start || end)
765 cal_irq_handle_wdma(cal->ctx[i], start, end);
766 }
767
768 return IRQ_HANDLED;
769 }
770
771 /* ------------------------------------------------------------------
772 * Asynchronous V4L2 subdev binding
773 * ------------------------------------------------------------------
774 */
775
776 struct cal_v4l2_async_subdev {
777 struct v4l2_async_connection asd; /* Must be first */
778 struct cal_camerarx *phy;
779 };
780
781 static inline struct cal_v4l2_async_subdev *
to_cal_asd(struct v4l2_async_connection * asd)782 to_cal_asd(struct v4l2_async_connection *asd)
783 {
784 return container_of(asd, struct cal_v4l2_async_subdev, asd);
785 }
786
cal_async_notifier_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asd)787 static int cal_async_notifier_bound(struct v4l2_async_notifier *notifier,
788 struct v4l2_subdev *subdev,
789 struct v4l2_async_connection *asd)
790 {
791 struct cal_camerarx *phy = to_cal_asd(asd)->phy;
792 int pad;
793 int ret;
794
795 if (phy->source) {
796 phy_info(phy, "Rejecting subdev %s (Already set!!)",
797 subdev->name);
798 return 0;
799 }
800
801 phy_dbg(1, phy, "Using source %s for capture\n", subdev->name);
802
803 pad = media_entity_get_fwnode_pad(&subdev->entity,
804 of_fwnode_handle(phy->source_ep_node),
805 MEDIA_PAD_FL_SOURCE);
806 if (pad < 0) {
807 phy_err(phy, "Source %s has no connected source pad\n",
808 subdev->name);
809 return pad;
810 }
811
812 ret = media_create_pad_link(&subdev->entity, pad,
813 &phy->subdev.entity, CAL_CAMERARX_PAD_SINK,
814 MEDIA_LNK_FL_IMMUTABLE |
815 MEDIA_LNK_FL_ENABLED);
816 if (ret) {
817 phy_err(phy, "Failed to create media link for source %s\n",
818 subdev->name);
819 return ret;
820 }
821
822 phy->source = subdev;
823 phy->source_pad = pad;
824
825 return 0;
826 }
827
cal_async_notifier_complete(struct v4l2_async_notifier * notifier)828 static int cal_async_notifier_complete(struct v4l2_async_notifier *notifier)
829 {
830 struct cal_dev *cal = container_of(notifier, struct cal_dev, notifier);
831 unsigned int i;
832 int ret;
833
834 for (i = 0; i < cal->num_contexts; ++i) {
835 ret = cal_ctx_v4l2_register(cal->ctx[i]);
836 if (ret)
837 goto err_ctx_unreg;
838 }
839
840 if (!cal_mc_api)
841 return 0;
842
843 ret = v4l2_device_register_subdev_nodes(&cal->v4l2_dev);
844 if (ret)
845 goto err_ctx_unreg;
846
847 return 0;
848
849 err_ctx_unreg:
850 for (; i > 0; --i) {
851 if (!cal->ctx[i - 1])
852 continue;
853
854 cal_ctx_v4l2_unregister(cal->ctx[i - 1]);
855 }
856
857 return ret;
858 }
859
860 static const struct v4l2_async_notifier_operations cal_async_notifier_ops = {
861 .bound = cal_async_notifier_bound,
862 .complete = cal_async_notifier_complete,
863 };
864
cal_async_notifier_register(struct cal_dev * cal)865 static int cal_async_notifier_register(struct cal_dev *cal)
866 {
867 unsigned int i;
868 int ret;
869
870 v4l2_async_nf_init(&cal->notifier, &cal->v4l2_dev);
871 cal->notifier.ops = &cal_async_notifier_ops;
872
873 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
874 struct cal_camerarx *phy = cal->phy[i];
875 struct cal_v4l2_async_subdev *casd;
876 struct fwnode_handle *fwnode;
877
878 if (!phy->source_node)
879 continue;
880
881 fwnode = of_fwnode_handle(phy->source_node);
882 casd = v4l2_async_nf_add_fwnode(&cal->notifier,
883 fwnode,
884 struct cal_v4l2_async_subdev);
885 if (IS_ERR(casd)) {
886 phy_err(phy, "Failed to add subdev to notifier\n");
887 ret = PTR_ERR(casd);
888 goto error;
889 }
890
891 casd->phy = phy;
892 }
893
894 ret = v4l2_async_nf_register(&cal->notifier);
895 if (ret) {
896 cal_err(cal, "Error registering async notifier\n");
897 goto error;
898 }
899
900 return 0;
901
902 error:
903 v4l2_async_nf_cleanup(&cal->notifier);
904 return ret;
905 }
906
cal_async_notifier_unregister(struct cal_dev * cal)907 static void cal_async_notifier_unregister(struct cal_dev *cal)
908 {
909 v4l2_async_nf_unregister(&cal->notifier);
910 v4l2_async_nf_cleanup(&cal->notifier);
911 }
912
913 /* ------------------------------------------------------------------
914 * Media and V4L2 device handling
915 * ------------------------------------------------------------------
916 */
917
918 /*
919 * Register user-facing devices. To be called at the end of the probe function
920 * when all resources are initialized and ready.
921 */
cal_media_register(struct cal_dev * cal)922 static int cal_media_register(struct cal_dev *cal)
923 {
924 int ret;
925
926 ret = media_device_register(&cal->mdev);
927 if (ret) {
928 cal_err(cal, "Failed to register media device\n");
929 return ret;
930 }
931
932 /*
933 * Register the async notifier. This may trigger registration of the
934 * V4L2 video devices if all subdevs are ready.
935 */
936 ret = cal_async_notifier_register(cal);
937 if (ret) {
938 media_device_unregister(&cal->mdev);
939 return ret;
940 }
941
942 return 0;
943 }
944
945 /*
946 * Unregister the user-facing devices, but don't free memory yet. To be called
947 * at the beginning of the remove function, to disallow access from userspace.
948 */
cal_media_unregister(struct cal_dev * cal)949 static void cal_media_unregister(struct cal_dev *cal)
950 {
951 unsigned int i;
952
953 /* Unregister all the V4L2 video devices. */
954 for (i = 0; i < cal->num_contexts; i++)
955 cal_ctx_v4l2_unregister(cal->ctx[i]);
956
957 cal_async_notifier_unregister(cal);
958 media_device_unregister(&cal->mdev);
959 }
960
961 /*
962 * Initialize the in-kernel objects. To be called at the beginning of the probe
963 * function, before the V4L2 device is used by the driver.
964 */
cal_media_init(struct cal_dev * cal)965 static int cal_media_init(struct cal_dev *cal)
966 {
967 struct media_device *mdev = &cal->mdev;
968 int ret;
969
970 mdev->dev = cal->dev;
971 mdev->hw_revision = cal->revision;
972 strscpy(mdev->model, "CAL", sizeof(mdev->model));
973 media_device_init(mdev);
974
975 /*
976 * Initialize the V4L2 device (despite the function name, this performs
977 * initialization, not registration).
978 */
979 cal->v4l2_dev.mdev = mdev;
980 ret = v4l2_device_register(cal->dev, &cal->v4l2_dev);
981 if (ret) {
982 cal_err(cal, "Failed to register V4L2 device\n");
983 return ret;
984 }
985
986 vb2_dma_contig_set_max_seg_size(cal->dev, DMA_BIT_MASK(32));
987
988 return 0;
989 }
990
991 /*
992 * Cleanup the in-kernel objects, freeing memory. To be called at the very end
993 * of the remove sequence, when nothing (including userspace) can access the
994 * objects anymore.
995 */
cal_media_cleanup(struct cal_dev * cal)996 static void cal_media_cleanup(struct cal_dev *cal)
997 {
998 v4l2_device_unregister(&cal->v4l2_dev);
999 media_device_cleanup(&cal->mdev);
1000
1001 vb2_dma_contig_clear_max_seg_size(cal->dev);
1002 }
1003
1004 /* ------------------------------------------------------------------
1005 * Initialization and module stuff
1006 * ------------------------------------------------------------------
1007 */
1008
cal_ctx_create(struct cal_dev * cal,int inst)1009 static struct cal_ctx *cal_ctx_create(struct cal_dev *cal, int inst)
1010 {
1011 struct cal_ctx *ctx;
1012 int ret;
1013
1014 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1015 if (!ctx)
1016 return NULL;
1017
1018 ctx->cal = cal;
1019 ctx->phy = cal->phy[inst];
1020 ctx->dma_ctx = inst;
1021 ctx->csi2_ctx = inst;
1022 ctx->cport = inst;
1023
1024 ret = cal_ctx_v4l2_init(ctx);
1025 if (ret) {
1026 kfree(ctx);
1027 return NULL;
1028 }
1029
1030 return ctx;
1031 }
1032
cal_ctx_destroy(struct cal_ctx * ctx)1033 static void cal_ctx_destroy(struct cal_ctx *ctx)
1034 {
1035 cal_ctx_v4l2_cleanup(ctx);
1036
1037 kfree(ctx);
1038 }
1039
1040 static const struct of_device_id cal_of_match[] = {
1041 {
1042 .compatible = "ti,dra72-cal",
1043 .data = (void *)&dra72x_cal_data,
1044 },
1045 {
1046 .compatible = "ti,dra72-pre-es2-cal",
1047 .data = (void *)&dra72x_es1_cal_data,
1048 },
1049 {
1050 .compatible = "ti,dra76-cal",
1051 .data = (void *)&dra76x_cal_data,
1052 },
1053 {
1054 .compatible = "ti,am654-cal",
1055 .data = (void *)&am654_cal_data,
1056 },
1057 {},
1058 };
1059 MODULE_DEVICE_TABLE(of, cal_of_match);
1060
1061 /* Get hardware revision and info. */
1062
1063 #define CAL_HL_HWINFO_VALUE 0xa3c90469
1064
cal_get_hwinfo(struct cal_dev * cal)1065 static void cal_get_hwinfo(struct cal_dev *cal)
1066 {
1067 u32 hwinfo;
1068
1069 cal->revision = cal_read(cal, CAL_HL_REVISION);
1070 switch (FIELD_GET(CAL_HL_REVISION_SCHEME_MASK, cal->revision)) {
1071 case CAL_HL_REVISION_SCHEME_H08:
1072 cal_dbg(3, cal, "CAL HW revision %lu.%lu.%lu (0x%08x)\n",
1073 FIELD_GET(CAL_HL_REVISION_MAJOR_MASK, cal->revision),
1074 FIELD_GET(CAL_HL_REVISION_MINOR_MASK, cal->revision),
1075 FIELD_GET(CAL_HL_REVISION_RTL_MASK, cal->revision),
1076 cal->revision);
1077 break;
1078
1079 case CAL_HL_REVISION_SCHEME_LEGACY:
1080 default:
1081 cal_info(cal, "Unexpected CAL HW revision 0x%08x\n",
1082 cal->revision);
1083 break;
1084 }
1085
1086 hwinfo = cal_read(cal, CAL_HL_HWINFO);
1087 if (hwinfo != CAL_HL_HWINFO_VALUE)
1088 cal_info(cal, "CAL_HL_HWINFO = 0x%08x, expected 0x%08x\n",
1089 hwinfo, CAL_HL_HWINFO_VALUE);
1090 }
1091
cal_init_camerarx_regmap(struct cal_dev * cal)1092 static int cal_init_camerarx_regmap(struct cal_dev *cal)
1093 {
1094 struct platform_device *pdev = to_platform_device(cal->dev);
1095 struct device_node *np = cal->dev->of_node;
1096 struct regmap_config config = { };
1097 struct regmap *syscon;
1098 struct resource *res;
1099 unsigned int offset;
1100 void __iomem *base;
1101
1102 syscon = syscon_regmap_lookup_by_phandle_args(np, "ti,camerrx-control",
1103 1, &offset);
1104 if (!IS_ERR(syscon)) {
1105 cal->syscon_camerrx = syscon;
1106 cal->syscon_camerrx_offset = offset;
1107 return 0;
1108 }
1109
1110 dev_warn(cal->dev, "failed to get ti,camerrx-control: %ld\n",
1111 PTR_ERR(syscon));
1112
1113 /*
1114 * Backward DTS compatibility. If syscon entry is not present then
1115 * check if the camerrx_control resource is present.
1116 */
1117 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1118 "camerrx_control");
1119 base = devm_ioremap_resource(cal->dev, res);
1120 if (IS_ERR(base)) {
1121 cal_err(cal, "failed to ioremap camerrx_control\n");
1122 return PTR_ERR(base);
1123 }
1124
1125 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
1126 res->name, &res->start, &res->end);
1127
1128 config.reg_bits = 32;
1129 config.reg_stride = 4;
1130 config.val_bits = 32;
1131 config.max_register = resource_size(res) - 4;
1132
1133 syscon = regmap_init_mmio(NULL, base, &config);
1134 if (IS_ERR(syscon)) {
1135 pr_err("regmap init failed\n");
1136 return PTR_ERR(syscon);
1137 }
1138
1139 /*
1140 * In this case the base already point to the direct CM register so no
1141 * need for an offset.
1142 */
1143 cal->syscon_camerrx = syscon;
1144 cal->syscon_camerrx_offset = 0;
1145
1146 return 0;
1147 }
1148
cal_probe(struct platform_device * pdev)1149 static int cal_probe(struct platform_device *pdev)
1150 {
1151 struct cal_dev *cal;
1152 bool connected = false;
1153 unsigned int i;
1154 int ret;
1155 int irq;
1156
1157 cal = devm_kzalloc(&pdev->dev, sizeof(*cal), GFP_KERNEL);
1158 if (!cal)
1159 return -ENOMEM;
1160
1161 cal->data = of_device_get_match_data(&pdev->dev);
1162 if (!cal->data) {
1163 dev_err(&pdev->dev, "Could not get feature data based on compatible version\n");
1164 return -ENODEV;
1165 }
1166
1167 cal->dev = &pdev->dev;
1168 platform_set_drvdata(pdev, cal);
1169
1170 /* Acquire resources: clocks, CAMERARX regmap, I/O memory and IRQ. */
1171 cal->fclk = devm_clk_get(&pdev->dev, "fck");
1172 if (IS_ERR(cal->fclk)) {
1173 dev_err(&pdev->dev, "cannot get CAL fclk\n");
1174 return PTR_ERR(cal->fclk);
1175 }
1176
1177 ret = cal_init_camerarx_regmap(cal);
1178 if (ret < 0)
1179 return ret;
1180
1181 cal->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1182 "cal_top");
1183 cal->base = devm_ioremap_resource(&pdev->dev, cal->res);
1184 if (IS_ERR(cal->base))
1185 return PTR_ERR(cal->base);
1186
1187 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n",
1188 cal->res->name, &cal->res->start, &cal->res->end);
1189
1190 irq = platform_get_irq(pdev, 0);
1191 cal_dbg(1, cal, "got irq# %d\n", irq);
1192 ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME,
1193 cal);
1194 if (ret)
1195 return ret;
1196
1197 /* Read the revision and hardware info to verify hardware access. */
1198 pm_runtime_enable(&pdev->dev);
1199 ret = pm_runtime_resume_and_get(&pdev->dev);
1200 if (ret)
1201 goto error_pm_runtime;
1202
1203 cal_get_hwinfo(cal);
1204 pm_runtime_put_sync(&pdev->dev);
1205
1206 /* Initialize the media device. */
1207 ret = cal_media_init(cal);
1208 if (ret < 0)
1209 goto error_pm_runtime;
1210
1211 /* Create CAMERARX PHYs. */
1212 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
1213 cal->phy[i] = cal_camerarx_create(cal, i);
1214 if (IS_ERR(cal->phy[i])) {
1215 ret = PTR_ERR(cal->phy[i]);
1216 cal->phy[i] = NULL;
1217 goto error_camerarx;
1218 }
1219
1220 if (cal->phy[i]->source_node)
1221 connected = true;
1222 }
1223
1224 if (!connected) {
1225 cal_err(cal, "Neither port is configured, no point in staying up\n");
1226 ret = -ENODEV;
1227 goto error_camerarx;
1228 }
1229
1230 /* Create contexts. */
1231 for (i = 0; i < cal->data->num_csi2_phy; ++i) {
1232 if (!cal->phy[i]->source_node)
1233 continue;
1234
1235 cal->ctx[cal->num_contexts] = cal_ctx_create(cal, i);
1236 if (!cal->ctx[cal->num_contexts]) {
1237 cal_err(cal, "Failed to create context %u\n", cal->num_contexts);
1238 ret = -ENODEV;
1239 goto error_context;
1240 }
1241
1242 cal->num_contexts++;
1243 }
1244
1245 /* Register the media device. */
1246 ret = cal_media_register(cal);
1247 if (ret)
1248 goto error_context;
1249
1250 return 0;
1251
1252 error_context:
1253 for (i = 0; i < cal->num_contexts; i++)
1254 cal_ctx_destroy(cal->ctx[i]);
1255
1256 error_camerarx:
1257 for (i = 0; i < cal->data->num_csi2_phy; i++)
1258 cal_camerarx_destroy(cal->phy[i]);
1259
1260 cal_media_cleanup(cal);
1261
1262 error_pm_runtime:
1263 pm_runtime_disable(&pdev->dev);
1264
1265 return ret;
1266 }
1267
cal_remove(struct platform_device * pdev)1268 static void cal_remove(struct platform_device *pdev)
1269 {
1270 struct cal_dev *cal = platform_get_drvdata(pdev);
1271 unsigned int i;
1272 int ret;
1273
1274 cal_dbg(1, cal, "Removing %s\n", CAL_MODULE_NAME);
1275
1276 ret = pm_runtime_resume_and_get(&pdev->dev);
1277
1278 cal_media_unregister(cal);
1279
1280 for (i = 0; i < cal->data->num_csi2_phy; i++)
1281 cal_camerarx_disable(cal->phy[i]);
1282
1283 for (i = 0; i < cal->num_contexts; i++)
1284 cal_ctx_destroy(cal->ctx[i]);
1285
1286 for (i = 0; i < cal->data->num_csi2_phy; i++)
1287 cal_camerarx_destroy(cal->phy[i]);
1288
1289 cal_media_cleanup(cal);
1290
1291 if (ret >= 0)
1292 pm_runtime_put_sync(&pdev->dev);
1293 pm_runtime_disable(&pdev->dev);
1294 }
1295
cal_runtime_resume(struct device * dev)1296 static int cal_runtime_resume(struct device *dev)
1297 {
1298 struct cal_dev *cal = dev_get_drvdata(dev);
1299 unsigned int i;
1300 u32 val;
1301
1302 if (cal->data->flags & DRA72_CAL_PRE_ES2_LDO_DISABLE) {
1303 /*
1304 * Apply errata on both port everytime we (re-)enable
1305 * the clock
1306 */
1307 for (i = 0; i < cal->data->num_csi2_phy; i++)
1308 cal_camerarx_i913_errata(cal->phy[i]);
1309 }
1310
1311 /*
1312 * Enable global interrupts that are not related to a particular
1313 * CAMERARAX or context.
1314 */
1315 cal_write(cal, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK);
1316
1317 val = cal_read(cal, CAL_CTRL);
1318 cal_set_field(&val, CAL_CTRL_BURSTSIZE_BURST128,
1319 CAL_CTRL_BURSTSIZE_MASK);
1320 cal_set_field(&val, 0xf, CAL_CTRL_TAGCNT_MASK);
1321 cal_set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,
1322 CAL_CTRL_POSTED_WRITES_MASK);
1323 cal_set_field(&val, 0xff, CAL_CTRL_MFLAGL_MASK);
1324 cal_set_field(&val, 0xff, CAL_CTRL_MFLAGH_MASK);
1325 cal_write(cal, CAL_CTRL, val);
1326 cal_dbg(3, cal, "CAL_CTRL = 0x%08x\n", cal_read(cal, CAL_CTRL));
1327
1328 return 0;
1329 }
1330
1331 static const struct dev_pm_ops cal_pm_ops = {
1332 .runtime_resume = cal_runtime_resume,
1333 };
1334
1335 static struct platform_driver cal_pdrv = {
1336 .probe = cal_probe,
1337 .remove = cal_remove,
1338 .driver = {
1339 .name = CAL_MODULE_NAME,
1340 .pm = &cal_pm_ops,
1341 .of_match_table = cal_of_match,
1342 },
1343 };
1344
1345 module_platform_driver(cal_pdrv);
1346