1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MICROCODE_H 3 #define _ASM_X86_MICROCODE_H 4 5 struct cpu_signature { 6 unsigned int sig; 7 unsigned int pf; 8 unsigned int rev; 9 }; 10 11 struct ucode_cpu_info { 12 struct cpu_signature cpu_sig; 13 void *mc; 14 }; 15 16 #ifdef CONFIG_MICROCODE 17 void load_ucode_bsp(void); 18 void load_ucode_ap(void); 19 void microcode_bsp_resume(void); 20 bool __init microcode_loader_disabled(void); 21 #else load_ucode_bsp(void)22static inline void load_ucode_bsp(void) { } load_ucode_ap(void)23static inline void load_ucode_ap(void) { } microcode_bsp_resume(void)24static inline void microcode_bsp_resume(void) { } microcode_loader_disabled(void)25static inline bool __init microcode_loader_disabled(void) { return false; } 26 #endif 27 28 extern unsigned long initrd_start_early; 29 30 #ifdef CONFIG_CPU_SUP_INTEL 31 /* Intel specific microcode defines. Public for IFS */ 32 struct microcode_header_intel { 33 unsigned int hdrver; 34 unsigned int rev; 35 unsigned int date; 36 unsigned int sig; 37 unsigned int cksum; 38 unsigned int ldrver; 39 unsigned int pf; 40 unsigned int datasize; 41 unsigned int totalsize; 42 unsigned int metasize; 43 unsigned int min_req_ver; 44 unsigned int reserved; 45 }; 46 47 struct microcode_intel { 48 struct microcode_header_intel hdr; 49 unsigned int bits[]; 50 }; 51 52 #define DEFAULT_UCODE_DATASIZE (2000) 53 #define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) 54 #define MC_HEADER_TYPE_MICROCODE 1 55 #define MC_HEADER_TYPE_IFS 2 56 intel_microcode_get_datasize(struct microcode_header_intel * hdr)57static inline int intel_microcode_get_datasize(struct microcode_header_intel *hdr) 58 { 59 return hdr->datasize ? : DEFAULT_UCODE_DATASIZE; 60 } 61 intel_get_microcode_revision(void)62static inline u32 intel_get_microcode_revision(void) 63 { 64 u32 rev, dummy; 65 66 native_wrmsrl(MSR_IA32_UCODE_REV, 0); 67 68 /* As documented in the SDM: Do a CPUID 1 here */ 69 native_cpuid_eax(1); 70 71 /* get the current revision from MSR 0x8B */ 72 native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); 73 74 return rev; 75 } 76 #endif /* !CONFIG_CPU_SUP_INTEL */ 77 78 bool microcode_nmi_handler(void); 79 void microcode_offline_nmi_handler(void); 80 81 #ifdef CONFIG_MICROCODE_LATE_LOADING 82 DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); microcode_nmi_handler_enabled(void)83static __always_inline bool microcode_nmi_handler_enabled(void) 84 { 85 return static_branch_unlikely(µcode_nmi_handler_enable); 86 } 87 #else microcode_nmi_handler_enabled(void)88static __always_inline bool microcode_nmi_handler_enabled(void) { return false; } 89 #endif 90 91 #endif /* _ASM_X86_MICROCODE_H */ 92