1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/ioport.h>
12 #include <linux/irq.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/core.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/mmc.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
34
35 #include "cqhci.h"
36
37 #define MAX_BD_NUM 1024
38
39 /*--------------------------------------------------------------------------*/
40 /* Common Definition */
41 /*--------------------------------------------------------------------------*/
42 #define MSDC_BUS_1BITS 0x0
43 #define MSDC_BUS_4BITS 0x1
44 #define MSDC_BUS_8BITS 0x2
45
46 #define MSDC_BURST_64B 0x6
47
48 /*--------------------------------------------------------------------------*/
49 /* Register Offset */
50 /*--------------------------------------------------------------------------*/
51 #define MSDC_CFG 0x0
52 #define MSDC_IOCON 0x04
53 #define MSDC_PS 0x08
54 #define MSDC_INT 0x0c
55 #define MSDC_INTEN 0x10
56 #define MSDC_FIFOCS 0x14
57 #define SDC_CFG 0x30
58 #define SDC_CMD 0x34
59 #define SDC_ARG 0x38
60 #define SDC_STS 0x3c
61 #define SDC_RESP0 0x40
62 #define SDC_RESP1 0x44
63 #define SDC_RESP2 0x48
64 #define SDC_RESP3 0x4c
65 #define SDC_BLK_NUM 0x50
66 #define SDC_ADV_CFG0 0x64
67 #define EMMC_IOCON 0x7c
68 #define SDC_ACMD_RESP 0x80
69 #define DMA_SA_H4BIT 0x8c
70 #define MSDC_DMA_SA 0x90
71 #define MSDC_DMA_CTRL 0x98
72 #define MSDC_DMA_CFG 0x9c
73 #define MSDC_PATCH_BIT 0xb0
74 #define MSDC_PATCH_BIT1 0xb4
75 #define MSDC_PATCH_BIT2 0xb8
76 #define MSDC_PAD_TUNE 0xec
77 #define MSDC_PAD_TUNE0 0xf0
78 #define PAD_DS_TUNE 0x188
79 #define PAD_CMD_TUNE 0x18c
80 #define EMMC50_CFG0 0x208
81 #define EMMC50_CFG3 0x220
82 #define SDC_FIFO_CFG 0x228
83
84 /*--------------------------------------------------------------------------*/
85 /* Top Pad Register Offset */
86 /*--------------------------------------------------------------------------*/
87 #define EMMC_TOP_CONTROL 0x00
88 #define EMMC_TOP_CMD 0x04
89 #define EMMC50_PAD_DS_TUNE 0x0c
90
91 /*--------------------------------------------------------------------------*/
92 /* Register Mask */
93 /*--------------------------------------------------------------------------*/
94
95 /* MSDC_CFG mask */
96 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
97 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
98 #define MSDC_CFG_RST (0x1 << 2) /* RW */
99 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
100 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
101 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
102 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
103 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
104 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
105 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
106 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
107 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
108 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
109 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
110
111 /* MSDC_IOCON mask */
112 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
113 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
114 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
115 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
116 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
117 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
118 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
119 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
120 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
121 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
122 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
123 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
124 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
125 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
126 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
127 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
128
129 /* MSDC_PS mask */
130 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
131 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
132 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
133 #define MSDC_PS_DAT (0xff << 16) /* R */
134 #define MSDC_PS_DATA1 (0x1 << 17) /* R */
135 #define MSDC_PS_CMD (0x1 << 24) /* R */
136 #define MSDC_PS_WP (0x1 << 31) /* R */
137
138 /* MSDC_INT mask */
139 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
140 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
141 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
142 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
143 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
144 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
145 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
146 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
147 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
148 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
149 #define MSDC_INT_CSTA (0x1 << 11) /* R */
150 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
151 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
152 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
153 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
154 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
155 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
156 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
157 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
158 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */
159
160 /* MSDC_INTEN mask */
161 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
162 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
163 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
164 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
165 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
166 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
167 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
168 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
169 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
170 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
171 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
172 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
173 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
174 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
175 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
176 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
177 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
178 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
179 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
180
181 /* MSDC_FIFOCS mask */
182 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
183 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
184 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
185
186 /* SDC_CFG mask */
187 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
188 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
189 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
190 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
191 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
192 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
193 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
194 #define SDC_CFG_DTOC (0xff << 24) /* RW */
195
196 /* SDC_STS mask */
197 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
198 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
199 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
200
201 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */
202 /* SDC_ADV_CFG0 mask */
203 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
204
205 /* DMA_SA_H4BIT mask */
206 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
207
208 /* MSDC_DMA_CTRL mask */
209 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
210 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
211 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
212 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
213 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
214 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
215
216 /* MSDC_DMA_CFG mask */
217 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
218 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
219 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
220 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
221 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
222
223 /* MSDC_PATCH_BIT mask */
224 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
225 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
226 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
227 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
228 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
229 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
230 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
231 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
232 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
233 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
234 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
235 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
236
237 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
238 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */
239 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
240
241 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
242 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
243 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
244 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
245 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
246 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
247
248 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
249 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
250 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
251 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
252 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
253 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
254 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
255 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
256
257 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
258 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
259 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
260
261 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
262
263 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
264 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
265 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
266
267 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
268
269 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
270 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
271
272 /* EMMC_TOP_CONTROL mask */
273 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */
274 #define DELAY_EN (0x1 << 1) /* RW */
275 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
276 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
277 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
278 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
279 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
280 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */
281
282 /* EMMC_TOP_CMD mask */
283 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
284 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */
285 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
286 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
287 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
288
289 #define REQ_CMD_EIO (0x1 << 0)
290 #define REQ_CMD_TMO (0x1 << 1)
291 #define REQ_DAT_ERR (0x1 << 2)
292 #define REQ_STOP_EIO (0x1 << 3)
293 #define REQ_STOP_TMO (0x1 << 4)
294 #define REQ_CMD_BUSY (0x1 << 5)
295
296 #define MSDC_PREPARE_FLAG (0x1 << 0)
297 #define MSDC_ASYNC_FLAG (0x1 << 1)
298 #define MSDC_MMAP_FLAG (0x1 << 2)
299
300 #define MTK_MMC_AUTOSUSPEND_DELAY 50
301 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
302 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
303
304 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
305
306 #define PAD_DELAY_MAX 32 /* PAD delay cells */
307 /*--------------------------------------------------------------------------*/
308 /* Descriptor Structure */
309 /*--------------------------------------------------------------------------*/
310 struct mt_gpdma_desc {
311 u32 gpd_info;
312 #define GPDMA_DESC_HWO (0x1 << 0)
313 #define GPDMA_DESC_BDP (0x1 << 1)
314 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
315 #define GPDMA_DESC_INT (0x1 << 16)
316 #define GPDMA_DESC_NEXT_H4 (0xf << 24)
317 #define GPDMA_DESC_PTR_H4 (0xf << 28)
318 u32 next;
319 u32 ptr;
320 u32 gpd_data_len;
321 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
322 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
323 u32 arg;
324 u32 blknum;
325 u32 cmd;
326 };
327
328 struct mt_bdma_desc {
329 u32 bd_info;
330 #define BDMA_DESC_EOL (0x1 << 0)
331 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
332 #define BDMA_DESC_BLKPAD (0x1 << 17)
333 #define BDMA_DESC_DWPAD (0x1 << 18)
334 #define BDMA_DESC_NEXT_H4 (0xf << 24)
335 #define BDMA_DESC_PTR_H4 (0xf << 28)
336 u32 next;
337 u32 ptr;
338 u32 bd_data_len;
339 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
340 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */
341 };
342
343 struct msdc_dma {
344 struct scatterlist *sg; /* I/O scatter list */
345 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
346 struct mt_bdma_desc *bd; /* pointer to bd array */
347 dma_addr_t gpd_addr; /* the physical address of gpd array */
348 dma_addr_t bd_addr; /* the physical address of bd array */
349 };
350
351 struct msdc_save_para {
352 u32 msdc_cfg;
353 u32 iocon;
354 u32 sdc_cfg;
355 u32 pad_tune;
356 u32 patch_bit0;
357 u32 patch_bit1;
358 u32 patch_bit2;
359 u32 pad_ds_tune;
360 u32 pad_cmd_tune;
361 u32 emmc50_cfg0;
362 u32 emmc50_cfg3;
363 u32 sdc_fifo_cfg;
364 u32 emmc_top_control;
365 u32 emmc_top_cmd;
366 u32 emmc50_pad_ds_tune;
367 };
368
369 struct mtk_mmc_compatible {
370 u8 clk_div_bits;
371 bool recheck_sdio_irq;
372 bool hs400_tune; /* only used for MT8173 */
373 u32 pad_tune_reg;
374 bool async_fifo;
375 bool data_tune;
376 bool busy_check;
377 bool stop_clk_fix;
378 bool enhance_rx;
379 bool support_64g;
380 bool use_internal_cd;
381 };
382
383 struct msdc_tune_para {
384 u32 iocon;
385 u32 pad_tune;
386 u32 pad_cmd_tune;
387 u32 emmc_top_control;
388 u32 emmc_top_cmd;
389 };
390
391 struct msdc_delay_phase {
392 u8 maxlen;
393 u8 start;
394 u8 final_phase;
395 };
396
397 struct msdc_host {
398 struct device *dev;
399 const struct mtk_mmc_compatible *dev_comp;
400 int cmd_rsp;
401
402 spinlock_t lock;
403 struct mmc_request *mrq;
404 struct mmc_command *cmd;
405 struct mmc_data *data;
406 int error;
407
408 void __iomem *base; /* host base address */
409 void __iomem *top_base; /* host top register base address */
410
411 struct msdc_dma dma; /* dma channel */
412 u64 dma_mask;
413
414 u32 timeout_ns; /* data timeout ns */
415 u32 timeout_clks; /* data timeout clks */
416
417 struct pinctrl *pinctrl;
418 struct pinctrl_state *pins_default;
419 struct pinctrl_state *pins_uhs;
420 struct delayed_work req_timeout;
421 int irq; /* host interrupt */
422 struct reset_control *reset;
423
424 struct clk *src_clk; /* msdc source clock */
425 struct clk *h_clk; /* msdc h_clk */
426 struct clk *bus_clk; /* bus clock which used to access register */
427 struct clk *src_clk_cg; /* msdc source clock control gate */
428 u32 mclk; /* mmc subsystem clock frequency */
429 u32 src_clk_freq; /* source clock frequency */
430 unsigned char timing;
431 bool vqmmc_enabled;
432 u32 latch_ck;
433 u32 hs400_ds_delay;
434 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
435 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
436 bool hs400_cmd_resp_sel_rising;
437 /* cmd response sample selection for HS400 */
438 bool hs400_mode; /* current eMMC will run at hs400 mode */
439 bool internal_cd; /* Use internal card-detect logic */
440 bool cqhci; /* support eMMC hw cmdq */
441 struct msdc_save_para save_para; /* used when gate HCLK */
442 struct msdc_tune_para def_tune_para; /* default tune setting */
443 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
444 struct cqhci_host *cq_host;
445 };
446
447 static const struct mtk_mmc_compatible mt8135_compat = {
448 .clk_div_bits = 8,
449 .recheck_sdio_irq = true,
450 .hs400_tune = false,
451 .pad_tune_reg = MSDC_PAD_TUNE,
452 .async_fifo = false,
453 .data_tune = false,
454 .busy_check = false,
455 .stop_clk_fix = false,
456 .enhance_rx = false,
457 .support_64g = false,
458 };
459
460 static const struct mtk_mmc_compatible mt8173_compat = {
461 .clk_div_bits = 8,
462 .recheck_sdio_irq = true,
463 .hs400_tune = true,
464 .pad_tune_reg = MSDC_PAD_TUNE,
465 .async_fifo = false,
466 .data_tune = false,
467 .busy_check = false,
468 .stop_clk_fix = false,
469 .enhance_rx = false,
470 .support_64g = false,
471 };
472
473 static const struct mtk_mmc_compatible mt8183_compat = {
474 .clk_div_bits = 12,
475 .recheck_sdio_irq = false,
476 .hs400_tune = false,
477 .pad_tune_reg = MSDC_PAD_TUNE0,
478 .async_fifo = true,
479 .data_tune = true,
480 .busy_check = true,
481 .stop_clk_fix = true,
482 .enhance_rx = true,
483 .support_64g = true,
484 };
485
486 static const struct mtk_mmc_compatible mt2701_compat = {
487 .clk_div_bits = 12,
488 .recheck_sdio_irq = true,
489 .hs400_tune = false,
490 .pad_tune_reg = MSDC_PAD_TUNE0,
491 .async_fifo = true,
492 .data_tune = true,
493 .busy_check = false,
494 .stop_clk_fix = false,
495 .enhance_rx = false,
496 .support_64g = false,
497 };
498
499 static const struct mtk_mmc_compatible mt2712_compat = {
500 .clk_div_bits = 12,
501 .recheck_sdio_irq = false,
502 .hs400_tune = false,
503 .pad_tune_reg = MSDC_PAD_TUNE0,
504 .async_fifo = true,
505 .data_tune = true,
506 .busy_check = true,
507 .stop_clk_fix = true,
508 .enhance_rx = true,
509 .support_64g = true,
510 };
511
512 static const struct mtk_mmc_compatible mt7622_compat = {
513 .clk_div_bits = 12,
514 .recheck_sdio_irq = true,
515 .hs400_tune = false,
516 .pad_tune_reg = MSDC_PAD_TUNE0,
517 .async_fifo = true,
518 .data_tune = true,
519 .busy_check = true,
520 .stop_clk_fix = true,
521 .enhance_rx = true,
522 .support_64g = false,
523 };
524
525 static const struct mtk_mmc_compatible mt8516_compat = {
526 .clk_div_bits = 12,
527 .recheck_sdio_irq = true,
528 .hs400_tune = false,
529 .pad_tune_reg = MSDC_PAD_TUNE0,
530 .async_fifo = true,
531 .data_tune = true,
532 .busy_check = true,
533 .stop_clk_fix = true,
534 };
535
536 static const struct mtk_mmc_compatible mt7620_compat = {
537 .clk_div_bits = 8,
538 .recheck_sdio_irq = true,
539 .hs400_tune = false,
540 .pad_tune_reg = MSDC_PAD_TUNE,
541 .async_fifo = false,
542 .data_tune = false,
543 .busy_check = false,
544 .stop_clk_fix = false,
545 .enhance_rx = false,
546 .use_internal_cd = true,
547 };
548
549 static const struct mtk_mmc_compatible mt6779_compat = {
550 .clk_div_bits = 12,
551 .recheck_sdio_irq = false,
552 .hs400_tune = false,
553 .pad_tune_reg = MSDC_PAD_TUNE0,
554 .async_fifo = true,
555 .data_tune = true,
556 .busy_check = true,
557 .stop_clk_fix = true,
558 .enhance_rx = true,
559 .support_64g = true,
560 };
561
562 static const struct of_device_id msdc_of_ids[] = {
563 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
564 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
565 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
566 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
567 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
568 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
569 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
570 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
571 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
572 {}
573 };
574 MODULE_DEVICE_TABLE(of, msdc_of_ids);
575
sdr_set_bits(void __iomem * reg,u32 bs)576 static void sdr_set_bits(void __iomem *reg, u32 bs)
577 {
578 u32 val = readl(reg);
579
580 val |= bs;
581 writel(val, reg);
582 }
583
sdr_clr_bits(void __iomem * reg,u32 bs)584 static void sdr_clr_bits(void __iomem *reg, u32 bs)
585 {
586 u32 val = readl(reg);
587
588 val &= ~bs;
589 writel(val, reg);
590 }
591
sdr_set_field(void __iomem * reg,u32 field,u32 val)592 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
593 {
594 unsigned int tv = readl(reg);
595
596 tv &= ~field;
597 tv |= ((val) << (ffs((unsigned int)field) - 1));
598 writel(tv, reg);
599 }
600
sdr_get_field(void __iomem * reg,u32 field,u32 * val)601 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
602 {
603 unsigned int tv = readl(reg);
604
605 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
606 }
607
msdc_reset_hw(struct msdc_host * host)608 static void msdc_reset_hw(struct msdc_host *host)
609 {
610 u32 val;
611
612 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
613 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
614 cpu_relax();
615
616 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
617 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
618 cpu_relax();
619
620 val = readl(host->base + MSDC_INT);
621 writel(val, host->base + MSDC_INT);
622 }
623
624 static void msdc_cmd_next(struct msdc_host *host,
625 struct mmc_request *mrq, struct mmc_command *cmd);
626 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
627
628 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
629 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
630 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
631 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
632 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
633 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
634
msdc_dma_calcs(u8 * buf,u32 len)635 static u8 msdc_dma_calcs(u8 *buf, u32 len)
636 {
637 u32 i, sum = 0;
638
639 for (i = 0; i < len; i++)
640 sum += buf[i];
641 return 0xff - (u8) sum;
642 }
643
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)644 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
645 struct mmc_data *data)
646 {
647 unsigned int j, dma_len;
648 dma_addr_t dma_address;
649 u32 dma_ctrl;
650 struct scatterlist *sg;
651 struct mt_gpdma_desc *gpd;
652 struct mt_bdma_desc *bd;
653
654 sg = data->sg;
655
656 gpd = dma->gpd;
657 bd = dma->bd;
658
659 /* modify gpd */
660 gpd->gpd_info |= GPDMA_DESC_HWO;
661 gpd->gpd_info |= GPDMA_DESC_BDP;
662 /* need to clear first. use these bits to calc checksum */
663 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
664 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
665
666 /* modify bd */
667 for_each_sg(data->sg, sg, data->sg_count, j) {
668 dma_address = sg_dma_address(sg);
669 dma_len = sg_dma_len(sg);
670
671 /* init bd */
672 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
673 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
674 bd[j].ptr = lower_32_bits(dma_address);
675 if (host->dev_comp->support_64g) {
676 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
677 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
678 << 28;
679 }
680
681 if (host->dev_comp->support_64g) {
682 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
683 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
684 } else {
685 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
686 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
687 }
688
689 if (j == data->sg_count - 1) /* the last bd */
690 bd[j].bd_info |= BDMA_DESC_EOL;
691 else
692 bd[j].bd_info &= ~BDMA_DESC_EOL;
693
694 /* checksume need to clear first */
695 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
696 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
697 }
698
699 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
700 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
701 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
702 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
703 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
704 if (host->dev_comp->support_64g)
705 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
706 upper_32_bits(dma->gpd_addr) & 0xf);
707 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
708 }
709
msdc_prepare_data(struct msdc_host * host,struct mmc_request * mrq)710 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
711 {
712 struct mmc_data *data = mrq->data;
713
714 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
715 data->host_cookie |= MSDC_PREPARE_FLAG;
716 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
717 mmc_get_dma_dir(data));
718 }
719 }
720
msdc_unprepare_data(struct msdc_host * host,struct mmc_request * mrq)721 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
722 {
723 struct mmc_data *data = mrq->data;
724
725 if (data->host_cookie & MSDC_ASYNC_FLAG)
726 return;
727
728 if (data->host_cookie & MSDC_PREPARE_FLAG) {
729 dma_unmap_sg(host->dev, data->sg, data->sg_len,
730 mmc_get_dma_dir(data));
731 data->host_cookie &= ~MSDC_PREPARE_FLAG;
732 }
733 }
734
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)735 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
736 {
737 struct mmc_host *mmc = mmc_from_priv(host);
738 u64 timeout, clk_ns;
739 u32 mode = 0;
740
741 if (mmc->actual_clock == 0) {
742 timeout = 0;
743 } else {
744 clk_ns = 1000000000ULL;
745 do_div(clk_ns, mmc->actual_clock);
746 timeout = ns + clk_ns - 1;
747 do_div(timeout, clk_ns);
748 timeout += clks;
749 /* in 1048576 sclk cycle unit */
750 timeout = DIV_ROUND_UP(timeout, (0x1 << 20));
751 if (host->dev_comp->clk_div_bits == 8)
752 sdr_get_field(host->base + MSDC_CFG,
753 MSDC_CFG_CKMOD, &mode);
754 else
755 sdr_get_field(host->base + MSDC_CFG,
756 MSDC_CFG_CKMOD_EXTRA, &mode);
757 /*DDR mode will double the clk cycles for data timeout */
758 timeout = mode >= 2 ? timeout * 2 : timeout;
759 timeout = timeout > 1 ? timeout - 1 : 0;
760 }
761 return timeout;
762 }
763
764 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)765 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
766 {
767 u64 timeout;
768
769 host->timeout_ns = ns;
770 host->timeout_clks = clks;
771
772 timeout = msdc_timeout_cal(host, ns, clks);
773 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
774 (u32)(timeout > 255 ? 255 : timeout));
775 }
776
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)777 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
778 {
779 u64 timeout;
780
781 timeout = msdc_timeout_cal(host, ns, clks);
782 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
783 (u32)(timeout > 8191 ? 8191 : timeout));
784 }
785
msdc_gate_clock(struct msdc_host * host)786 static void msdc_gate_clock(struct msdc_host *host)
787 {
788 clk_disable_unprepare(host->src_clk_cg);
789 clk_disable_unprepare(host->src_clk);
790 clk_disable_unprepare(host->bus_clk);
791 clk_disable_unprepare(host->h_clk);
792 }
793
msdc_ungate_clock(struct msdc_host * host)794 static void msdc_ungate_clock(struct msdc_host *host)
795 {
796 clk_prepare_enable(host->h_clk);
797 clk_prepare_enable(host->bus_clk);
798 clk_prepare_enable(host->src_clk);
799 clk_prepare_enable(host->src_clk_cg);
800 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
801 cpu_relax();
802 }
803
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)804 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
805 {
806 struct mmc_host *mmc = mmc_from_priv(host);
807 u32 mode;
808 u32 flags;
809 u32 div;
810 u32 sclk;
811 u32 tune_reg = host->dev_comp->pad_tune_reg;
812
813 if (!hz) {
814 dev_dbg(host->dev, "set mclk to 0\n");
815 host->mclk = 0;
816 mmc->actual_clock = 0;
817 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
818 return;
819 }
820
821 flags = readl(host->base + MSDC_INTEN);
822 sdr_clr_bits(host->base + MSDC_INTEN, flags);
823 if (host->dev_comp->clk_div_bits == 8)
824 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
825 else
826 sdr_clr_bits(host->base + MSDC_CFG,
827 MSDC_CFG_HS400_CK_MODE_EXTRA);
828 if (timing == MMC_TIMING_UHS_DDR50 ||
829 timing == MMC_TIMING_MMC_DDR52 ||
830 timing == MMC_TIMING_MMC_HS400) {
831 if (timing == MMC_TIMING_MMC_HS400)
832 mode = 0x3;
833 else
834 mode = 0x2; /* ddr mode and use divisor */
835
836 if (hz >= (host->src_clk_freq >> 2)) {
837 div = 0; /* mean div = 1/4 */
838 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
839 } else {
840 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
841 sclk = (host->src_clk_freq >> 2) / div;
842 div = (div >> 1);
843 }
844
845 if (timing == MMC_TIMING_MMC_HS400 &&
846 hz >= (host->src_clk_freq >> 1)) {
847 if (host->dev_comp->clk_div_bits == 8)
848 sdr_set_bits(host->base + MSDC_CFG,
849 MSDC_CFG_HS400_CK_MODE);
850 else
851 sdr_set_bits(host->base + MSDC_CFG,
852 MSDC_CFG_HS400_CK_MODE_EXTRA);
853 sclk = host->src_clk_freq >> 1;
854 div = 0; /* div is ignore when bit18 is set */
855 }
856 } else if (hz >= host->src_clk_freq) {
857 mode = 0x1; /* no divisor */
858 div = 0;
859 sclk = host->src_clk_freq;
860 } else {
861 mode = 0x0; /* use divisor */
862 if (hz >= (host->src_clk_freq >> 1)) {
863 div = 0; /* mean div = 1/2 */
864 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
865 } else {
866 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
867 sclk = (host->src_clk_freq >> 2) / div;
868 }
869 }
870 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
871 /*
872 * As src_clk/HCLK use the same bit to gate/ungate,
873 * So if want to only gate src_clk, need gate its parent(mux).
874 */
875 if (host->src_clk_cg)
876 clk_disable_unprepare(host->src_clk_cg);
877 else
878 clk_disable_unprepare(clk_get_parent(host->src_clk));
879 if (host->dev_comp->clk_div_bits == 8)
880 sdr_set_field(host->base + MSDC_CFG,
881 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
882 (mode << 8) | div);
883 else
884 sdr_set_field(host->base + MSDC_CFG,
885 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
886 (mode << 12) | div);
887 if (host->src_clk_cg)
888 clk_prepare_enable(host->src_clk_cg);
889 else
890 clk_prepare_enable(clk_get_parent(host->src_clk));
891
892 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
893 cpu_relax();
894 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
895 mmc->actual_clock = sclk;
896 host->mclk = hz;
897 host->timing = timing;
898 /* need because clk changed. */
899 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
900 sdr_set_bits(host->base + MSDC_INTEN, flags);
901
902 /*
903 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
904 * tune result of hs200/200Mhz is not suitable for 50Mhz
905 */
906 if (mmc->actual_clock <= 52000000) {
907 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
908 if (host->top_base) {
909 writel(host->def_tune_para.emmc_top_control,
910 host->top_base + EMMC_TOP_CONTROL);
911 writel(host->def_tune_para.emmc_top_cmd,
912 host->top_base + EMMC_TOP_CMD);
913 } else {
914 writel(host->def_tune_para.pad_tune,
915 host->base + tune_reg);
916 }
917 } else {
918 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
919 writel(host->saved_tune_para.pad_cmd_tune,
920 host->base + PAD_CMD_TUNE);
921 if (host->top_base) {
922 writel(host->saved_tune_para.emmc_top_control,
923 host->top_base + EMMC_TOP_CONTROL);
924 writel(host->saved_tune_para.emmc_top_cmd,
925 host->top_base + EMMC_TOP_CMD);
926 } else {
927 writel(host->saved_tune_para.pad_tune,
928 host->base + tune_reg);
929 }
930 }
931
932 if (timing == MMC_TIMING_MMC_HS400 &&
933 host->dev_comp->hs400_tune)
934 sdr_set_field(host->base + tune_reg,
935 MSDC_PAD_TUNE_CMDRRDLY,
936 host->hs400_cmd_int_delay);
937 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
938 timing);
939 }
940
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)941 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
942 struct mmc_request *mrq, struct mmc_command *cmd)
943 {
944 u32 resp;
945
946 switch (mmc_resp_type(cmd)) {
947 /* Actually, R1, R5, R6, R7 are the same */
948 case MMC_RSP_R1:
949 resp = 0x1;
950 break;
951 case MMC_RSP_R1B:
952 resp = 0x7;
953 break;
954 case MMC_RSP_R2:
955 resp = 0x2;
956 break;
957 case MMC_RSP_R3:
958 resp = 0x3;
959 break;
960 case MMC_RSP_NONE:
961 default:
962 resp = 0x0;
963 break;
964 }
965
966 return resp;
967 }
968
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)969 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
970 struct mmc_request *mrq, struct mmc_command *cmd)
971 {
972 struct mmc_host *mmc = mmc_from_priv(host);
973 /* rawcmd :
974 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
975 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
976 */
977 u32 opcode = cmd->opcode;
978 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
979 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
980
981 host->cmd_rsp = resp;
982
983 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
984 opcode == MMC_STOP_TRANSMISSION)
985 rawcmd |= (0x1 << 14);
986 else if (opcode == SD_SWITCH_VOLTAGE)
987 rawcmd |= (0x1 << 30);
988 else if (opcode == SD_APP_SEND_SCR ||
989 opcode == SD_APP_SEND_NUM_WR_BLKS ||
990 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
991 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
992 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
993 rawcmd |= (0x1 << 11);
994
995 if (cmd->data) {
996 struct mmc_data *data = cmd->data;
997
998 if (mmc_op_multi(opcode)) {
999 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1000 !(mrq->sbc->arg & 0xFFFF0000))
1001 rawcmd |= 0x2 << 28; /* AutoCMD23 */
1002 }
1003
1004 rawcmd |= ((data->blksz & 0xFFF) << 16);
1005 if (data->flags & MMC_DATA_WRITE)
1006 rawcmd |= (0x1 << 13);
1007 if (data->blocks > 1)
1008 rawcmd |= (0x2 << 11);
1009 else
1010 rawcmd |= (0x1 << 11);
1011 /* Always use dma mode */
1012 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1013
1014 if (host->timeout_ns != data->timeout_ns ||
1015 host->timeout_clks != data->timeout_clks)
1016 msdc_set_timeout(host, data->timeout_ns,
1017 data->timeout_clks);
1018
1019 writel(data->blocks, host->base + SDC_BLK_NUM);
1020 }
1021 return rawcmd;
1022 }
1023
msdc_start_data(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd,struct mmc_data * data)1024 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
1025 struct mmc_command *cmd, struct mmc_data *data)
1026 {
1027 bool read;
1028
1029 WARN_ON(host->data);
1030 host->data = data;
1031 read = data->flags & MMC_DATA_READ;
1032
1033 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1034 msdc_dma_setup(host, &host->dma, data);
1035 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1036 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1037 dev_dbg(host->dev, "DMA start\n");
1038 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1039 __func__, cmd->opcode, data->blocks, read);
1040 }
1041
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1042 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1043 struct mmc_command *cmd)
1044 {
1045 u32 *rsp = cmd->resp;
1046
1047 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1048
1049 if (events & MSDC_INT_ACMDRDY) {
1050 cmd->error = 0;
1051 } else {
1052 msdc_reset_hw(host);
1053 if (events & MSDC_INT_ACMDCRCERR) {
1054 cmd->error = -EILSEQ;
1055 host->error |= REQ_STOP_EIO;
1056 } else if (events & MSDC_INT_ACMDTMO) {
1057 cmd->error = -ETIMEDOUT;
1058 host->error |= REQ_STOP_TMO;
1059 }
1060 dev_err(host->dev,
1061 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1062 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1063 }
1064 return cmd->error;
1065 }
1066
1067 /*
1068 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1069 *
1070 * Host controller may lost interrupt in some special case.
1071 * Add SDIO irq recheck mechanism to make sure all interrupts
1072 * can be processed immediately
1073 */
msdc_recheck_sdio_irq(struct msdc_host * host)1074 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1075 {
1076 struct mmc_host *mmc = mmc_from_priv(host);
1077 u32 reg_int, reg_inten, reg_ps;
1078
1079 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1080 reg_inten = readl(host->base + MSDC_INTEN);
1081 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1082 reg_int = readl(host->base + MSDC_INT);
1083 reg_ps = readl(host->base + MSDC_PS);
1084 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1085 reg_ps & MSDC_PS_DATA1)) {
1086 __msdc_enable_sdio_irq(host, 0);
1087 sdio_signal_irq(mmc);
1088 }
1089 }
1090 }
1091 }
1092
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1093 static void msdc_track_cmd_data(struct msdc_host *host,
1094 struct mmc_command *cmd, struct mmc_data *data)
1095 {
1096 if (host->error)
1097 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1098 __func__, cmd->opcode, cmd->arg, host->error);
1099 }
1100
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1101 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1102 {
1103 unsigned long flags;
1104 bool ret;
1105
1106 ret = cancel_delayed_work(&host->req_timeout);
1107 if (!ret) {
1108 /* delay work already running */
1109 return;
1110 }
1111 spin_lock_irqsave(&host->lock, flags);
1112 host->mrq = NULL;
1113 spin_unlock_irqrestore(&host->lock, flags);
1114
1115 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1116 if (mrq->data)
1117 msdc_unprepare_data(host, mrq);
1118 if (host->error)
1119 msdc_reset_hw(host);
1120 mmc_request_done(mmc_from_priv(host), mrq);
1121 if (host->dev_comp->recheck_sdio_irq)
1122 msdc_recheck_sdio_irq(host);
1123 }
1124
1125 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1126 static bool msdc_cmd_done(struct msdc_host *host, int events,
1127 struct mmc_request *mrq, struct mmc_command *cmd)
1128 {
1129 bool done = false;
1130 bool sbc_error;
1131 unsigned long flags;
1132 u32 *rsp = cmd->resp;
1133
1134 if (mrq->sbc && cmd == mrq->cmd &&
1135 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1136 | MSDC_INT_ACMDTMO)))
1137 msdc_auto_cmd_done(host, events, mrq->sbc);
1138
1139 sbc_error = mrq->sbc && mrq->sbc->error;
1140
1141 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1142 | MSDC_INT_RSPCRCERR
1143 | MSDC_INT_CMDTMO)))
1144 return done;
1145
1146 spin_lock_irqsave(&host->lock, flags);
1147 done = !host->cmd;
1148 host->cmd = NULL;
1149 spin_unlock_irqrestore(&host->lock, flags);
1150
1151 if (done)
1152 return true;
1153
1154 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1155
1156 if (cmd->flags & MMC_RSP_PRESENT) {
1157 if (cmd->flags & MMC_RSP_136) {
1158 rsp[0] = readl(host->base + SDC_RESP3);
1159 rsp[1] = readl(host->base + SDC_RESP2);
1160 rsp[2] = readl(host->base + SDC_RESP1);
1161 rsp[3] = readl(host->base + SDC_RESP0);
1162 } else {
1163 rsp[0] = readl(host->base + SDC_RESP0);
1164 }
1165 }
1166
1167 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1168 if (events & MSDC_INT_CMDTMO ||
1169 (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1170 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1171 /*
1172 * should not clear fifo/interrupt as the tune data
1173 * may have alreay come when cmd19/cmd21 gets response
1174 * CRC error.
1175 */
1176 msdc_reset_hw(host);
1177 if (events & MSDC_INT_RSPCRCERR) {
1178 cmd->error = -EILSEQ;
1179 host->error |= REQ_CMD_EIO;
1180 } else if (events & MSDC_INT_CMDTMO) {
1181 cmd->error = -ETIMEDOUT;
1182 host->error |= REQ_CMD_TMO;
1183 }
1184 }
1185 if (cmd->error)
1186 dev_dbg(host->dev,
1187 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1188 __func__, cmd->opcode, cmd->arg, rsp[0],
1189 cmd->error);
1190
1191 msdc_cmd_next(host, mrq, cmd);
1192 return true;
1193 }
1194
1195 /* It is the core layer's responsibility to ensure card status
1196 * is correct before issue a request. but host design do below
1197 * checks recommended.
1198 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1199 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1200 struct mmc_request *mrq, struct mmc_command *cmd)
1201 {
1202 /* The max busy time we can endure is 20ms */
1203 unsigned long tmo = jiffies + msecs_to_jiffies(20);
1204
1205 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1206 time_before(jiffies, tmo))
1207 cpu_relax();
1208 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1209 dev_err(host->dev, "CMD bus busy detected\n");
1210 host->error |= REQ_CMD_BUSY;
1211 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1212 return false;
1213 }
1214
1215 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1216 tmo = jiffies + msecs_to_jiffies(20);
1217 /* R1B or with data, should check SDCBUSY */
1218 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1219 time_before(jiffies, tmo))
1220 cpu_relax();
1221 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1222 dev_err(host->dev, "Controller busy detected\n");
1223 host->error |= REQ_CMD_BUSY;
1224 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1225 return false;
1226 }
1227 }
1228 return true;
1229 }
1230
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1231 static void msdc_start_command(struct msdc_host *host,
1232 struct mmc_request *mrq, struct mmc_command *cmd)
1233 {
1234 u32 rawcmd;
1235 unsigned long flags;
1236
1237 WARN_ON(host->cmd);
1238 host->cmd = cmd;
1239
1240 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1241 if (!msdc_cmd_is_ready(host, mrq, cmd))
1242 return;
1243
1244 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1245 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1246 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1247 msdc_reset_hw(host);
1248 }
1249
1250 cmd->error = 0;
1251 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1252
1253 spin_lock_irqsave(&host->lock, flags);
1254 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1255 spin_unlock_irqrestore(&host->lock, flags);
1256
1257 writel(cmd->arg, host->base + SDC_ARG);
1258 writel(rawcmd, host->base + SDC_CMD);
1259 }
1260
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1261 static void msdc_cmd_next(struct msdc_host *host,
1262 struct mmc_request *mrq, struct mmc_command *cmd)
1263 {
1264 if ((cmd->error &&
1265 !(cmd->error == -EILSEQ &&
1266 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1267 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1268 (mrq->sbc && mrq->sbc->error))
1269 msdc_request_done(host, mrq);
1270 else if (cmd == mrq->sbc)
1271 msdc_start_command(host, mrq, mrq->cmd);
1272 else if (!cmd->data)
1273 msdc_request_done(host, mrq);
1274 else
1275 msdc_start_data(host, mrq, cmd, cmd->data);
1276 }
1277
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1278 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1279 {
1280 struct msdc_host *host = mmc_priv(mmc);
1281
1282 host->error = 0;
1283 WARN_ON(host->mrq);
1284 host->mrq = mrq;
1285
1286 if (mrq->data)
1287 msdc_prepare_data(host, mrq);
1288
1289 /* if SBC is required, we have HW option and SW option.
1290 * if HW option is enabled, and SBC does not have "special" flags,
1291 * use HW option, otherwise use SW option
1292 */
1293 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1294 (mrq->sbc->arg & 0xFFFF0000)))
1295 msdc_start_command(host, mrq, mrq->sbc);
1296 else
1297 msdc_start_command(host, mrq, mrq->cmd);
1298 }
1299
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1300 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1301 {
1302 struct msdc_host *host = mmc_priv(mmc);
1303 struct mmc_data *data = mrq->data;
1304
1305 if (!data)
1306 return;
1307
1308 msdc_prepare_data(host, mrq);
1309 data->host_cookie |= MSDC_ASYNC_FLAG;
1310 }
1311
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1312 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1313 int err)
1314 {
1315 struct msdc_host *host = mmc_priv(mmc);
1316 struct mmc_data *data;
1317
1318 data = mrq->data;
1319 if (!data)
1320 return;
1321 if (data->host_cookie) {
1322 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1323 msdc_unprepare_data(host, mrq);
1324 }
1325 }
1326
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_data * data)1327 static void msdc_data_xfer_next(struct msdc_host *host,
1328 struct mmc_request *mrq, struct mmc_data *data)
1329 {
1330 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1331 !mrq->sbc)
1332 msdc_start_command(host, mrq, mrq->stop);
1333 else
1334 msdc_request_done(host, mrq);
1335 }
1336
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1337 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1338 struct mmc_request *mrq, struct mmc_data *data)
1339 {
1340 struct mmc_command *stop = data->stop;
1341 unsigned long flags;
1342 bool done;
1343 unsigned int check_data = events &
1344 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1345 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1346 | MSDC_INT_DMA_PROTECT);
1347
1348 spin_lock_irqsave(&host->lock, flags);
1349 done = !host->data;
1350 if (check_data)
1351 host->data = NULL;
1352 spin_unlock_irqrestore(&host->lock, flags);
1353
1354 if (done)
1355 return true;
1356
1357 if (check_data || (stop && stop->error)) {
1358 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1359 readl(host->base + MSDC_DMA_CFG));
1360 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1361 1);
1362 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1363 cpu_relax();
1364 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1365 dev_dbg(host->dev, "DMA stop\n");
1366
1367 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1368 data->bytes_xfered = data->blocks * data->blksz;
1369 } else {
1370 dev_dbg(host->dev, "interrupt events: %x\n", events);
1371 msdc_reset_hw(host);
1372 host->error |= REQ_DAT_ERR;
1373 data->bytes_xfered = 0;
1374
1375 if (events & MSDC_INT_DATTMO)
1376 data->error = -ETIMEDOUT;
1377 else if (events & MSDC_INT_DATCRCERR)
1378 data->error = -EILSEQ;
1379
1380 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1381 __func__, mrq->cmd->opcode, data->blocks);
1382 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1383 (int)data->error, data->bytes_xfered);
1384 }
1385
1386 msdc_data_xfer_next(host, mrq, data);
1387 done = true;
1388 }
1389 return done;
1390 }
1391
msdc_set_buswidth(struct msdc_host * host,u32 width)1392 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1393 {
1394 u32 val = readl(host->base + SDC_CFG);
1395
1396 val &= ~SDC_CFG_BUSWIDTH;
1397
1398 switch (width) {
1399 default:
1400 case MMC_BUS_WIDTH_1:
1401 val |= (MSDC_BUS_1BITS << 16);
1402 break;
1403 case MMC_BUS_WIDTH_4:
1404 val |= (MSDC_BUS_4BITS << 16);
1405 break;
1406 case MMC_BUS_WIDTH_8:
1407 val |= (MSDC_BUS_8BITS << 16);
1408 break;
1409 }
1410
1411 writel(val, host->base + SDC_CFG);
1412 dev_dbg(host->dev, "Bus Width = %d", width);
1413 }
1414
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1415 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1416 {
1417 struct msdc_host *host = mmc_priv(mmc);
1418 int ret;
1419
1420 if (!IS_ERR(mmc->supply.vqmmc)) {
1421 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1422 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1423 dev_err(host->dev, "Unsupported signal voltage!\n");
1424 return -EINVAL;
1425 }
1426
1427 ret = mmc_regulator_set_vqmmc(mmc, ios);
1428 if (ret < 0) {
1429 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1430 ret, ios->signal_voltage);
1431 return ret;
1432 }
1433
1434 /* Apply different pinctrl settings for different signal voltage */
1435 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1436 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1437 else
1438 pinctrl_select_state(host->pinctrl, host->pins_default);
1439 }
1440 return 0;
1441 }
1442
msdc_card_busy(struct mmc_host * mmc)1443 static int msdc_card_busy(struct mmc_host *mmc)
1444 {
1445 struct msdc_host *host = mmc_priv(mmc);
1446 u32 status = readl(host->base + MSDC_PS);
1447
1448 /* only check if data0 is low */
1449 return !(status & BIT(16));
1450 }
1451
msdc_request_timeout(struct work_struct * work)1452 static void msdc_request_timeout(struct work_struct *work)
1453 {
1454 struct msdc_host *host = container_of(work, struct msdc_host,
1455 req_timeout.work);
1456
1457 /* simulate HW timeout status */
1458 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1459 if (host->mrq) {
1460 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1461 host->mrq, host->mrq->cmd->opcode);
1462 if (host->cmd) {
1463 dev_err(host->dev, "%s: aborting cmd=%d\n",
1464 __func__, host->cmd->opcode);
1465 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1466 host->cmd);
1467 } else if (host->data) {
1468 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1469 __func__, host->mrq->cmd->opcode,
1470 host->data->blocks);
1471 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1472 host->data);
1473 }
1474 }
1475 }
1476
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1477 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1478 {
1479 if (enb) {
1480 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1481 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1482 if (host->dev_comp->recheck_sdio_irq)
1483 msdc_recheck_sdio_irq(host);
1484 } else {
1485 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1486 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1487 }
1488 }
1489
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1490 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1491 {
1492 unsigned long flags;
1493 struct msdc_host *host = mmc_priv(mmc);
1494
1495 spin_lock_irqsave(&host->lock, flags);
1496 __msdc_enable_sdio_irq(host, enb);
1497 spin_unlock_irqrestore(&host->lock, flags);
1498
1499 if (enb)
1500 pm_runtime_get_noresume(host->dev);
1501 else
1502 pm_runtime_put_noidle(host->dev);
1503 }
1504
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1505 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1506 {
1507 struct mmc_host *mmc = mmc_from_priv(host);
1508 int cmd_err = 0, dat_err = 0;
1509
1510 if (intsts & MSDC_INT_RSPCRCERR) {
1511 cmd_err = -EILSEQ;
1512 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1513 } else if (intsts & MSDC_INT_CMDTMO) {
1514 cmd_err = -ETIMEDOUT;
1515 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1516 }
1517
1518 if (intsts & MSDC_INT_DATCRCERR) {
1519 dat_err = -EILSEQ;
1520 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1521 } else if (intsts & MSDC_INT_DATTMO) {
1522 dat_err = -ETIMEDOUT;
1523 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1524 }
1525
1526 if (cmd_err || dat_err) {
1527 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1528 cmd_err, dat_err, intsts);
1529 }
1530
1531 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1532 }
1533
msdc_irq(int irq,void * dev_id)1534 static irqreturn_t msdc_irq(int irq, void *dev_id)
1535 {
1536 struct msdc_host *host = (struct msdc_host *) dev_id;
1537 struct mmc_host *mmc = mmc_from_priv(host);
1538
1539 while (true) {
1540 unsigned long flags;
1541 struct mmc_request *mrq;
1542 struct mmc_command *cmd;
1543 struct mmc_data *data;
1544 u32 events, event_mask;
1545
1546 spin_lock_irqsave(&host->lock, flags);
1547 events = readl(host->base + MSDC_INT);
1548 event_mask = readl(host->base + MSDC_INTEN);
1549 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1550 __msdc_enable_sdio_irq(host, 0);
1551 /* clear interrupts */
1552 writel(events & event_mask, host->base + MSDC_INT);
1553
1554 mrq = host->mrq;
1555 cmd = host->cmd;
1556 data = host->data;
1557 spin_unlock_irqrestore(&host->lock, flags);
1558
1559 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1560 sdio_signal_irq(mmc);
1561
1562 if ((events & event_mask) & MSDC_INT_CDSC) {
1563 if (host->internal_cd)
1564 mmc_detect_change(mmc, msecs_to_jiffies(20));
1565 events &= ~MSDC_INT_CDSC;
1566 }
1567
1568 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1569 break;
1570
1571 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1572 (events & MSDC_INT_CMDQ)) {
1573 msdc_cmdq_irq(host, events);
1574 /* clear interrupts */
1575 writel(events, host->base + MSDC_INT);
1576 return IRQ_HANDLED;
1577 }
1578
1579 if (!mrq) {
1580 dev_err(host->dev,
1581 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1582 __func__, events, event_mask);
1583 WARN_ON(1);
1584 break;
1585 }
1586
1587 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1588
1589 if (cmd)
1590 msdc_cmd_done(host, events, mrq, cmd);
1591 else if (data)
1592 msdc_data_xfer_done(host, events, mrq, data);
1593 }
1594
1595 return IRQ_HANDLED;
1596 }
1597
msdc_init_hw(struct msdc_host * host)1598 static void msdc_init_hw(struct msdc_host *host)
1599 {
1600 u32 val;
1601 u32 tune_reg = host->dev_comp->pad_tune_reg;
1602
1603 if (host->reset) {
1604 reset_control_assert(host->reset);
1605 usleep_range(10, 50);
1606 reset_control_deassert(host->reset);
1607 }
1608
1609 /* Configure to MMC/SD mode, clock free running */
1610 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1611
1612 /* Reset */
1613 msdc_reset_hw(host);
1614
1615 /* Disable and clear all interrupts */
1616 writel(0, host->base + MSDC_INTEN);
1617 val = readl(host->base + MSDC_INT);
1618 writel(val, host->base + MSDC_INT);
1619
1620 /* Configure card detection */
1621 if (host->internal_cd) {
1622 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1623 DEFAULT_DEBOUNCE);
1624 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1625 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1626 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1627 } else {
1628 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1629 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1630 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1631 }
1632
1633 if (host->top_base) {
1634 writel(0, host->top_base + EMMC_TOP_CONTROL);
1635 writel(0, host->top_base + EMMC_TOP_CMD);
1636 } else {
1637 writel(0, host->base + tune_reg);
1638 }
1639 writel(0, host->base + MSDC_IOCON);
1640 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1641 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1642 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1643 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1644 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1645
1646 if (host->dev_comp->stop_clk_fix) {
1647 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1648 MSDC_PATCH_BIT1_STOP_DLY, 3);
1649 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1650 SDC_FIFO_CFG_WRVALIDSEL);
1651 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1652 SDC_FIFO_CFG_RDVALIDSEL);
1653 }
1654
1655 if (host->dev_comp->busy_check)
1656 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1657
1658 if (host->dev_comp->async_fifo) {
1659 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1660 MSDC_PB2_RESPWAIT, 3);
1661 if (host->dev_comp->enhance_rx) {
1662 if (host->top_base)
1663 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1664 SDC_RX_ENH_EN);
1665 else
1666 sdr_set_bits(host->base + SDC_ADV_CFG0,
1667 SDC_RX_ENHANCE_EN);
1668 } else {
1669 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1670 MSDC_PB2_RESPSTSENSEL, 2);
1671 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1672 MSDC_PB2_CRCSTSENSEL, 2);
1673 }
1674 /* use async fifo, then no need tune internal delay */
1675 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1676 MSDC_PATCH_BIT2_CFGRESP);
1677 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1678 MSDC_PATCH_BIT2_CFGCRCSTS);
1679 }
1680
1681 if (host->dev_comp->support_64g)
1682 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1683 MSDC_PB2_SUPPORT_64G);
1684 if (host->dev_comp->data_tune) {
1685 if (host->top_base) {
1686 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1687 PAD_DAT_RD_RXDLY_SEL);
1688 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1689 DATA_K_VALUE_SEL);
1690 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1691 PAD_CMD_RD_RXDLY_SEL);
1692 } else {
1693 sdr_set_bits(host->base + tune_reg,
1694 MSDC_PAD_TUNE_RD_SEL |
1695 MSDC_PAD_TUNE_CMD_SEL);
1696 }
1697 } else {
1698 /* choose clock tune */
1699 if (host->top_base)
1700 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1701 PAD_RXDLY_SEL);
1702 else
1703 sdr_set_bits(host->base + tune_reg,
1704 MSDC_PAD_TUNE_RXDLYSEL);
1705 }
1706
1707 /* Configure to enable SDIO mode.
1708 * it's must otherwise sdio cmd5 failed
1709 */
1710 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1711
1712 /* Config SDIO device detect interrupt function */
1713 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1714 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1715
1716 /* Configure to default data timeout */
1717 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1718
1719 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1720 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1721 if (host->top_base) {
1722 host->def_tune_para.emmc_top_control =
1723 readl(host->top_base + EMMC_TOP_CONTROL);
1724 host->def_tune_para.emmc_top_cmd =
1725 readl(host->top_base + EMMC_TOP_CMD);
1726 host->saved_tune_para.emmc_top_control =
1727 readl(host->top_base + EMMC_TOP_CONTROL);
1728 host->saved_tune_para.emmc_top_cmd =
1729 readl(host->top_base + EMMC_TOP_CMD);
1730 } else {
1731 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1732 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1733 }
1734 dev_dbg(host->dev, "init hardware done!");
1735 }
1736
msdc_deinit_hw(struct msdc_host * host)1737 static void msdc_deinit_hw(struct msdc_host *host)
1738 {
1739 u32 val;
1740
1741 if (host->internal_cd) {
1742 /* Disabled card-detect */
1743 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1744 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1745 }
1746
1747 /* Disable and clear all interrupts */
1748 writel(0, host->base + MSDC_INTEN);
1749
1750 val = readl(host->base + MSDC_INT);
1751 writel(val, host->base + MSDC_INT);
1752 }
1753
1754 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1755 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1756 {
1757 struct mt_gpdma_desc *gpd = dma->gpd;
1758 struct mt_bdma_desc *bd = dma->bd;
1759 dma_addr_t dma_addr;
1760 int i;
1761
1762 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1763
1764 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1765 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1766 /* gpd->next is must set for desc DMA
1767 * That's why must alloc 2 gpd structure.
1768 */
1769 gpd->next = lower_32_bits(dma_addr);
1770 if (host->dev_comp->support_64g)
1771 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1772
1773 dma_addr = dma->bd_addr;
1774 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1775 if (host->dev_comp->support_64g)
1776 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1777
1778 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1779 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1780 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1781 bd[i].next = lower_32_bits(dma_addr);
1782 if (host->dev_comp->support_64g)
1783 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1784 }
1785 }
1786
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1787 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1788 {
1789 struct msdc_host *host = mmc_priv(mmc);
1790 int ret;
1791
1792 msdc_set_buswidth(host, ios->bus_width);
1793
1794 /* Suspend/Resume will do power off/on */
1795 switch (ios->power_mode) {
1796 case MMC_POWER_UP:
1797 if (!IS_ERR(mmc->supply.vmmc)) {
1798 msdc_init_hw(host);
1799 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1800 ios->vdd);
1801 if (ret) {
1802 dev_err(host->dev, "Failed to set vmmc power!\n");
1803 return;
1804 }
1805 }
1806 break;
1807 case MMC_POWER_ON:
1808 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1809 ret = regulator_enable(mmc->supply.vqmmc);
1810 if (ret)
1811 dev_err(host->dev, "Failed to set vqmmc power!\n");
1812 else
1813 host->vqmmc_enabled = true;
1814 }
1815 break;
1816 case MMC_POWER_OFF:
1817 if (!IS_ERR(mmc->supply.vmmc))
1818 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1819
1820 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1821 regulator_disable(mmc->supply.vqmmc);
1822 host->vqmmc_enabled = false;
1823 }
1824 break;
1825 default:
1826 break;
1827 }
1828
1829 if (host->mclk != ios->clock || host->timing != ios->timing)
1830 msdc_set_mclk(host, ios->timing, ios->clock);
1831 }
1832
test_delay_bit(u32 delay,u32 bit)1833 static u32 test_delay_bit(u32 delay, u32 bit)
1834 {
1835 bit %= PAD_DELAY_MAX;
1836 return delay & (1 << bit);
1837 }
1838
get_delay_len(u32 delay,u32 start_bit)1839 static int get_delay_len(u32 delay, u32 start_bit)
1840 {
1841 int i;
1842
1843 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1844 if (test_delay_bit(delay, start_bit + i) == 0)
1845 return i;
1846 }
1847 return PAD_DELAY_MAX - start_bit;
1848 }
1849
get_best_delay(struct msdc_host * host,u32 delay)1850 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1851 {
1852 int start = 0, len = 0;
1853 int start_final = 0, len_final = 0;
1854 u8 final_phase = 0xff;
1855 struct msdc_delay_phase delay_phase = { 0, };
1856
1857 if (delay == 0) {
1858 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1859 delay_phase.final_phase = final_phase;
1860 return delay_phase;
1861 }
1862
1863 while (start < PAD_DELAY_MAX) {
1864 len = get_delay_len(delay, start);
1865 if (len_final < len) {
1866 start_final = start;
1867 len_final = len;
1868 }
1869 start += len ? len : 1;
1870 if (len >= 12 && start_final < 4)
1871 break;
1872 }
1873
1874 /* The rule is that to find the smallest delay cell */
1875 if (start_final == 0)
1876 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1877 else
1878 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1879 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1880 delay, len_final, final_phase);
1881
1882 delay_phase.maxlen = len_final;
1883 delay_phase.start = start_final;
1884 delay_phase.final_phase = final_phase;
1885 return delay_phase;
1886 }
1887
msdc_set_cmd_delay(struct msdc_host * host,u32 value)1888 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1889 {
1890 u32 tune_reg = host->dev_comp->pad_tune_reg;
1891
1892 if (host->top_base)
1893 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1894 value);
1895 else
1896 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1897 value);
1898 }
1899
msdc_set_data_delay(struct msdc_host * host,u32 value)1900 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1901 {
1902 u32 tune_reg = host->dev_comp->pad_tune_reg;
1903
1904 if (host->top_base)
1905 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1906 PAD_DAT_RD_RXDLY, value);
1907 else
1908 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1909 value);
1910 }
1911
msdc_tune_response(struct mmc_host * mmc,u32 opcode)1912 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1913 {
1914 struct msdc_host *host = mmc_priv(mmc);
1915 u32 rise_delay = 0, fall_delay = 0;
1916 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1917 struct msdc_delay_phase internal_delay_phase;
1918 u8 final_delay, final_maxlen;
1919 u32 internal_delay = 0;
1920 u32 tune_reg = host->dev_comp->pad_tune_reg;
1921 int cmd_err;
1922 int i, j;
1923
1924 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1925 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1926 sdr_set_field(host->base + tune_reg,
1927 MSDC_PAD_TUNE_CMDRRDLY,
1928 host->hs200_cmd_int_delay);
1929
1930 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1931 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1932 msdc_set_cmd_delay(host, i);
1933 /*
1934 * Using the same parameters, it may sometimes pass the test,
1935 * but sometimes it may fail. To make sure the parameters are
1936 * more stable, we test each set of parameters 3 times.
1937 */
1938 for (j = 0; j < 3; j++) {
1939 mmc_send_tuning(mmc, opcode, &cmd_err);
1940 if (!cmd_err) {
1941 rise_delay |= (1 << i);
1942 } else {
1943 rise_delay &= ~(1 << i);
1944 break;
1945 }
1946 }
1947 }
1948 final_rise_delay = get_best_delay(host, rise_delay);
1949 /* if rising edge has enough margin, then do not scan falling edge */
1950 if (final_rise_delay.maxlen >= 12 ||
1951 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1952 goto skip_fall;
1953
1954 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1955 for (i = 0; i < PAD_DELAY_MAX; i++) {
1956 msdc_set_cmd_delay(host, i);
1957 /*
1958 * Using the same parameters, it may sometimes pass the test,
1959 * but sometimes it may fail. To make sure the parameters are
1960 * more stable, we test each set of parameters 3 times.
1961 */
1962 for (j = 0; j < 3; j++) {
1963 mmc_send_tuning(mmc, opcode, &cmd_err);
1964 if (!cmd_err) {
1965 fall_delay |= (1 << i);
1966 } else {
1967 fall_delay &= ~(1 << i);
1968 break;
1969 }
1970 }
1971 }
1972 final_fall_delay = get_best_delay(host, fall_delay);
1973
1974 skip_fall:
1975 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1976 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1977 final_maxlen = final_fall_delay.maxlen;
1978 if (final_maxlen == final_rise_delay.maxlen) {
1979 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1980 final_delay = final_rise_delay.final_phase;
1981 } else {
1982 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1983 final_delay = final_fall_delay.final_phase;
1984 }
1985 msdc_set_cmd_delay(host, final_delay);
1986
1987 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1988 goto skip_internal;
1989
1990 for (i = 0; i < PAD_DELAY_MAX; i++) {
1991 sdr_set_field(host->base + tune_reg,
1992 MSDC_PAD_TUNE_CMDRRDLY, i);
1993 mmc_send_tuning(mmc, opcode, &cmd_err);
1994 if (!cmd_err)
1995 internal_delay |= (1 << i);
1996 }
1997 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1998 internal_delay_phase = get_best_delay(host, internal_delay);
1999 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2000 internal_delay_phase.final_phase);
2001 skip_internal:
2002 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2003 return final_delay == 0xff ? -EIO : 0;
2004 }
2005
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2006 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2007 {
2008 struct msdc_host *host = mmc_priv(mmc);
2009 u32 cmd_delay = 0;
2010 struct msdc_delay_phase final_cmd_delay = { 0,};
2011 u8 final_delay;
2012 int cmd_err;
2013 int i, j;
2014
2015 /* select EMMC50 PAD CMD tune */
2016 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2017 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2018
2019 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2020 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2021 sdr_set_field(host->base + MSDC_PAD_TUNE,
2022 MSDC_PAD_TUNE_CMDRRDLY,
2023 host->hs200_cmd_int_delay);
2024
2025 if (host->hs400_cmd_resp_sel_rising)
2026 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2027 else
2028 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2029 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2030 sdr_set_field(host->base + PAD_CMD_TUNE,
2031 PAD_CMD_TUNE_RX_DLY3, i);
2032 /*
2033 * Using the same parameters, it may sometimes pass the test,
2034 * but sometimes it may fail. To make sure the parameters are
2035 * more stable, we test each set of parameters 3 times.
2036 */
2037 for (j = 0; j < 3; j++) {
2038 mmc_send_tuning(mmc, opcode, &cmd_err);
2039 if (!cmd_err) {
2040 cmd_delay |= (1 << i);
2041 } else {
2042 cmd_delay &= ~(1 << i);
2043 break;
2044 }
2045 }
2046 }
2047 final_cmd_delay = get_best_delay(host, cmd_delay);
2048 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2049 final_cmd_delay.final_phase);
2050 final_delay = final_cmd_delay.final_phase;
2051
2052 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2053 return final_delay == 0xff ? -EIO : 0;
2054 }
2055
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2056 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2057 {
2058 struct msdc_host *host = mmc_priv(mmc);
2059 u32 rise_delay = 0, fall_delay = 0;
2060 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2061 u8 final_delay, final_maxlen;
2062 int i, ret;
2063
2064 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2065 host->latch_ck);
2066 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2067 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2068 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2069 msdc_set_data_delay(host, i);
2070 ret = mmc_send_tuning(mmc, opcode, NULL);
2071 if (!ret)
2072 rise_delay |= (1 << i);
2073 }
2074 final_rise_delay = get_best_delay(host, rise_delay);
2075 /* if rising edge has enough margin, then do not scan falling edge */
2076 if (final_rise_delay.maxlen >= 12 ||
2077 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2078 goto skip_fall;
2079
2080 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2081 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2082 for (i = 0; i < PAD_DELAY_MAX; i++) {
2083 msdc_set_data_delay(host, i);
2084 ret = mmc_send_tuning(mmc, opcode, NULL);
2085 if (!ret)
2086 fall_delay |= (1 << i);
2087 }
2088 final_fall_delay = get_best_delay(host, fall_delay);
2089
2090 skip_fall:
2091 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2092 if (final_maxlen == final_rise_delay.maxlen) {
2093 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2094 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2095 final_delay = final_rise_delay.final_phase;
2096 } else {
2097 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2098 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2099 final_delay = final_fall_delay.final_phase;
2100 }
2101 msdc_set_data_delay(host, final_delay);
2102
2103 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2104 return final_delay == 0xff ? -EIO : 0;
2105 }
2106
2107 /*
2108 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2109 * together, which can save the tuning time.
2110 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2111 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2112 {
2113 struct msdc_host *host = mmc_priv(mmc);
2114 u32 rise_delay = 0, fall_delay = 0;
2115 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2116 u8 final_delay, final_maxlen;
2117 int i, ret;
2118
2119 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2120 host->latch_ck);
2121
2122 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2123 sdr_clr_bits(host->base + MSDC_IOCON,
2124 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2125 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2126 msdc_set_cmd_delay(host, i);
2127 msdc_set_data_delay(host, i);
2128 ret = mmc_send_tuning(mmc, opcode, NULL);
2129 if (!ret)
2130 rise_delay |= (1 << i);
2131 }
2132 final_rise_delay = get_best_delay(host, rise_delay);
2133 /* if rising edge has enough margin, then do not scan falling edge */
2134 if (final_rise_delay.maxlen >= 12 ||
2135 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2136 goto skip_fall;
2137
2138 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2139 sdr_set_bits(host->base + MSDC_IOCON,
2140 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2141 for (i = 0; i < PAD_DELAY_MAX; i++) {
2142 msdc_set_cmd_delay(host, i);
2143 msdc_set_data_delay(host, i);
2144 ret = mmc_send_tuning(mmc, opcode, NULL);
2145 if (!ret)
2146 fall_delay |= (1 << i);
2147 }
2148 final_fall_delay = get_best_delay(host, fall_delay);
2149
2150 skip_fall:
2151 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2152 if (final_maxlen == final_rise_delay.maxlen) {
2153 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2154 sdr_clr_bits(host->base + MSDC_IOCON,
2155 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2156 final_delay = final_rise_delay.final_phase;
2157 } else {
2158 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2159 sdr_set_bits(host->base + MSDC_IOCON,
2160 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2161 final_delay = final_fall_delay.final_phase;
2162 }
2163
2164 msdc_set_cmd_delay(host, final_delay);
2165 msdc_set_data_delay(host, final_delay);
2166
2167 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2168 return final_delay == 0xff ? -EIO : 0;
2169 }
2170
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2171 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2172 {
2173 struct msdc_host *host = mmc_priv(mmc);
2174 int ret;
2175 u32 tune_reg = host->dev_comp->pad_tune_reg;
2176
2177 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2178 ret = msdc_tune_together(mmc, opcode);
2179 if (host->hs400_mode) {
2180 sdr_clr_bits(host->base + MSDC_IOCON,
2181 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2182 msdc_set_data_delay(host, 0);
2183 }
2184 goto tune_done;
2185 }
2186 if (host->hs400_mode &&
2187 host->dev_comp->hs400_tune)
2188 ret = hs400_tune_response(mmc, opcode);
2189 else
2190 ret = msdc_tune_response(mmc, opcode);
2191 if (ret == -EIO) {
2192 dev_err(host->dev, "Tune response fail!\n");
2193 return ret;
2194 }
2195 if (host->hs400_mode == false) {
2196 ret = msdc_tune_data(mmc, opcode);
2197 if (ret == -EIO)
2198 dev_err(host->dev, "Tune data fail!\n");
2199 }
2200
2201 tune_done:
2202 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2203 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2204 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2205 if (host->top_base) {
2206 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2207 EMMC_TOP_CONTROL);
2208 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2209 EMMC_TOP_CMD);
2210 }
2211 return ret;
2212 }
2213
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2214 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2215 {
2216 struct msdc_host *host = mmc_priv(mmc);
2217 host->hs400_mode = true;
2218
2219 if (host->top_base)
2220 writel(host->hs400_ds_delay,
2221 host->top_base + EMMC50_PAD_DS_TUNE);
2222 else
2223 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2224 /* hs400 mode must set it to 0 */
2225 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2226 /* to improve read performance, set outstanding to 2 */
2227 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2228
2229 return 0;
2230 }
2231
msdc_hw_reset(struct mmc_host * mmc)2232 static void msdc_hw_reset(struct mmc_host *mmc)
2233 {
2234 struct msdc_host *host = mmc_priv(mmc);
2235
2236 sdr_set_bits(host->base + EMMC_IOCON, 1);
2237 udelay(10); /* 10us is enough */
2238 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2239 }
2240
msdc_ack_sdio_irq(struct mmc_host * mmc)2241 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2242 {
2243 unsigned long flags;
2244 struct msdc_host *host = mmc_priv(mmc);
2245
2246 spin_lock_irqsave(&host->lock, flags);
2247 __msdc_enable_sdio_irq(host, 1);
2248 spin_unlock_irqrestore(&host->lock, flags);
2249 }
2250
msdc_get_cd(struct mmc_host * mmc)2251 static int msdc_get_cd(struct mmc_host *mmc)
2252 {
2253 struct msdc_host *host = mmc_priv(mmc);
2254 int val;
2255
2256 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2257 return 1;
2258
2259 if (!host->internal_cd)
2260 return mmc_gpio_get_cd(mmc);
2261
2262 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2263 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2264 return !!val;
2265 else
2266 return !val;
2267 }
2268
msdc_cqe_enable(struct mmc_host * mmc)2269 static void msdc_cqe_enable(struct mmc_host *mmc)
2270 {
2271 struct msdc_host *host = mmc_priv(mmc);
2272
2273 /* enable cmdq irq */
2274 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2275 /* enable busy check */
2276 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2277 /* default write data / busy timeout 20s */
2278 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2279 /* default read data timeout 1s */
2280 msdc_set_timeout(host, 1000000000ULL, 0);
2281 }
2282
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2283 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2284 {
2285 struct msdc_host *host = mmc_priv(mmc);
2286
2287 /* disable cmdq irq */
2288 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2289 /* disable busy check */
2290 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2291
2292 if (recovery) {
2293 sdr_set_field(host->base + MSDC_DMA_CTRL,
2294 MSDC_DMA_CTRL_STOP, 1);
2295 msdc_reset_hw(host);
2296 }
2297 }
2298
msdc_cqe_pre_enable(struct mmc_host * mmc)2299 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2300 {
2301 struct cqhci_host *cq_host = mmc->cqe_private;
2302 u32 reg;
2303
2304 reg = cqhci_readl(cq_host, CQHCI_CFG);
2305 reg |= CQHCI_ENABLE;
2306 cqhci_writel(cq_host, reg, CQHCI_CFG);
2307 }
2308
msdc_cqe_post_disable(struct mmc_host * mmc)2309 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2310 {
2311 struct cqhci_host *cq_host = mmc->cqe_private;
2312 u32 reg;
2313
2314 reg = cqhci_readl(cq_host, CQHCI_CFG);
2315 reg &= ~CQHCI_ENABLE;
2316 cqhci_writel(cq_host, reg, CQHCI_CFG);
2317 }
2318
2319 static const struct mmc_host_ops mt_msdc_ops = {
2320 .post_req = msdc_post_req,
2321 .pre_req = msdc_pre_req,
2322 .request = msdc_ops_request,
2323 .set_ios = msdc_ops_set_ios,
2324 .get_ro = mmc_gpio_get_ro,
2325 .get_cd = msdc_get_cd,
2326 .enable_sdio_irq = msdc_enable_sdio_irq,
2327 .ack_sdio_irq = msdc_ack_sdio_irq,
2328 .start_signal_voltage_switch = msdc_ops_switch_volt,
2329 .card_busy = msdc_card_busy,
2330 .execute_tuning = msdc_execute_tuning,
2331 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2332 .hw_reset = msdc_hw_reset,
2333 };
2334
2335 static const struct cqhci_host_ops msdc_cmdq_ops = {
2336 .enable = msdc_cqe_enable,
2337 .disable = msdc_cqe_disable,
2338 .pre_enable = msdc_cqe_pre_enable,
2339 .post_disable = msdc_cqe_post_disable,
2340 };
2341
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2342 static void msdc_of_property_parse(struct platform_device *pdev,
2343 struct msdc_host *host)
2344 {
2345 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2346 &host->latch_ck);
2347
2348 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2349 &host->hs400_ds_delay);
2350
2351 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2352 &host->hs200_cmd_int_delay);
2353
2354 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2355 &host->hs400_cmd_int_delay);
2356
2357 if (of_property_read_bool(pdev->dev.of_node,
2358 "mediatek,hs400-cmd-resp-sel-rising"))
2359 host->hs400_cmd_resp_sel_rising = true;
2360 else
2361 host->hs400_cmd_resp_sel_rising = false;
2362
2363 if (of_property_read_bool(pdev->dev.of_node,
2364 "supports-cqe"))
2365 host->cqhci = true;
2366 else
2367 host->cqhci = false;
2368 }
2369
msdc_drv_probe(struct platform_device * pdev)2370 static int msdc_drv_probe(struct platform_device *pdev)
2371 {
2372 struct mmc_host *mmc;
2373 struct msdc_host *host;
2374 struct resource *res;
2375 int ret;
2376
2377 if (!pdev->dev.of_node) {
2378 dev_err(&pdev->dev, "No DT found\n");
2379 return -EINVAL;
2380 }
2381
2382 /* Allocate MMC host for this device */
2383 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2384 if (!mmc)
2385 return -ENOMEM;
2386
2387 host = mmc_priv(mmc);
2388 ret = mmc_of_parse(mmc);
2389 if (ret)
2390 goto host_free;
2391
2392 host->base = devm_platform_ioremap_resource(pdev, 0);
2393 if (IS_ERR(host->base)) {
2394 ret = PTR_ERR(host->base);
2395 goto host_free;
2396 }
2397
2398 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2399 if (res) {
2400 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2401 if (IS_ERR(host->top_base))
2402 host->top_base = NULL;
2403 }
2404
2405 ret = mmc_regulator_get_supply(mmc);
2406 if (ret)
2407 goto host_free;
2408
2409 host->src_clk = devm_clk_get(&pdev->dev, "source");
2410 if (IS_ERR(host->src_clk)) {
2411 ret = PTR_ERR(host->src_clk);
2412 goto host_free;
2413 }
2414
2415 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2416 if (IS_ERR(host->h_clk)) {
2417 ret = PTR_ERR(host->h_clk);
2418 goto host_free;
2419 }
2420
2421 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
2422 if (IS_ERR(host->bus_clk))
2423 host->bus_clk = NULL;
2424 /*source clock control gate is optional clock*/
2425 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
2426 if (IS_ERR(host->src_clk_cg))
2427 host->src_clk_cg = NULL;
2428
2429 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2430 "hrst");
2431 if (IS_ERR(host->reset))
2432 return PTR_ERR(host->reset);
2433
2434 host->irq = platform_get_irq(pdev, 0);
2435 if (host->irq < 0) {
2436 ret = -EINVAL;
2437 goto host_free;
2438 }
2439
2440 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2441 if (IS_ERR(host->pinctrl)) {
2442 ret = PTR_ERR(host->pinctrl);
2443 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2444 goto host_free;
2445 }
2446
2447 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2448 if (IS_ERR(host->pins_default)) {
2449 ret = PTR_ERR(host->pins_default);
2450 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2451 goto host_free;
2452 }
2453
2454 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2455 if (IS_ERR(host->pins_uhs)) {
2456 ret = PTR_ERR(host->pins_uhs);
2457 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2458 goto host_free;
2459 }
2460
2461 msdc_of_property_parse(pdev, host);
2462
2463 host->dev = &pdev->dev;
2464 host->dev_comp = of_device_get_match_data(&pdev->dev);
2465 host->src_clk_freq = clk_get_rate(host->src_clk);
2466 /* Set host parameters to mmc */
2467 mmc->ops = &mt_msdc_ops;
2468 if (host->dev_comp->clk_div_bits == 8)
2469 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2470 else
2471 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2472
2473 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2474 !mmc_can_gpio_cd(mmc) &&
2475 host->dev_comp->use_internal_cd) {
2476 /*
2477 * Is removable but no GPIO declared, so
2478 * use internal functionality.
2479 */
2480 host->internal_cd = true;
2481 }
2482
2483 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2484 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2485
2486 mmc->caps |= MMC_CAP_CMD23;
2487 if (host->cqhci)
2488 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2489 /* MMC core transfer sizes tunable parameters */
2490 mmc->max_segs = MAX_BD_NUM;
2491 if (host->dev_comp->support_64g)
2492 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2493 else
2494 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2495 mmc->max_blk_size = 2048;
2496 mmc->max_req_size = 512 * 1024;
2497 mmc->max_blk_count = mmc->max_req_size / 512;
2498 if (host->dev_comp->support_64g)
2499 host->dma_mask = DMA_BIT_MASK(36);
2500 else
2501 host->dma_mask = DMA_BIT_MASK(32);
2502 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2503
2504 if (mmc->caps2 & MMC_CAP2_CQE) {
2505 host->cq_host = devm_kzalloc(mmc->parent,
2506 sizeof(*host->cq_host),
2507 GFP_KERNEL);
2508 if (!host->cq_host) {
2509 ret = -ENOMEM;
2510 goto host_free;
2511 }
2512 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2513 host->cq_host->mmio = host->base + 0x800;
2514 host->cq_host->ops = &msdc_cmdq_ops;
2515 ret = cqhci_init(host->cq_host, mmc, true);
2516 if (ret)
2517 goto host_free;
2518 mmc->max_segs = 128;
2519 /* cqhci 16bit length */
2520 /* 0 size, means 65536 so we don't have to -1 here */
2521 mmc->max_seg_size = 64 * 1024;
2522 }
2523
2524 host->timeout_clks = 3 * 1048576;
2525 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2526 2 * sizeof(struct mt_gpdma_desc),
2527 &host->dma.gpd_addr, GFP_KERNEL);
2528 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2529 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2530 &host->dma.bd_addr, GFP_KERNEL);
2531 if (!host->dma.gpd || !host->dma.bd) {
2532 ret = -ENOMEM;
2533 goto release_mem;
2534 }
2535 msdc_init_gpd_bd(host, &host->dma);
2536 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2537 spin_lock_init(&host->lock);
2538
2539 platform_set_drvdata(pdev, mmc);
2540 msdc_ungate_clock(host);
2541 msdc_init_hw(host);
2542
2543 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2544 IRQF_TRIGGER_NONE, pdev->name, host);
2545 if (ret)
2546 goto release;
2547
2548 pm_runtime_set_active(host->dev);
2549 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2550 pm_runtime_use_autosuspend(host->dev);
2551 pm_runtime_enable(host->dev);
2552 ret = mmc_add_host(mmc);
2553
2554 if (ret)
2555 goto end;
2556
2557 return 0;
2558 end:
2559 pm_runtime_disable(host->dev);
2560 release:
2561 platform_set_drvdata(pdev, NULL);
2562 msdc_deinit_hw(host);
2563 msdc_gate_clock(host);
2564 release_mem:
2565 if (host->dma.gpd)
2566 dma_free_coherent(&pdev->dev,
2567 2 * sizeof(struct mt_gpdma_desc),
2568 host->dma.gpd, host->dma.gpd_addr);
2569 if (host->dma.bd)
2570 dma_free_coherent(&pdev->dev,
2571 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2572 host->dma.bd, host->dma.bd_addr);
2573 host_free:
2574 mmc_free_host(mmc);
2575
2576 return ret;
2577 }
2578
msdc_drv_remove(struct platform_device * pdev)2579 static int msdc_drv_remove(struct platform_device *pdev)
2580 {
2581 struct mmc_host *mmc;
2582 struct msdc_host *host;
2583
2584 mmc = platform_get_drvdata(pdev);
2585 host = mmc_priv(mmc);
2586
2587 pm_runtime_get_sync(host->dev);
2588
2589 platform_set_drvdata(pdev, NULL);
2590 mmc_remove_host(mmc);
2591 msdc_deinit_hw(host);
2592 msdc_gate_clock(host);
2593
2594 pm_runtime_disable(host->dev);
2595 pm_runtime_put_noidle(host->dev);
2596 dma_free_coherent(&pdev->dev,
2597 2 * sizeof(struct mt_gpdma_desc),
2598 host->dma.gpd, host->dma.gpd_addr);
2599 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2600 host->dma.bd, host->dma.bd_addr);
2601
2602 mmc_free_host(mmc);
2603
2604 return 0;
2605 }
2606
msdc_save_reg(struct msdc_host * host)2607 static void msdc_save_reg(struct msdc_host *host)
2608 {
2609 u32 tune_reg = host->dev_comp->pad_tune_reg;
2610
2611 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2612 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2613 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2614 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2615 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2616 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2617 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2618 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2619 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2620 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2621 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2622 if (host->top_base) {
2623 host->save_para.emmc_top_control =
2624 readl(host->top_base + EMMC_TOP_CONTROL);
2625 host->save_para.emmc_top_cmd =
2626 readl(host->top_base + EMMC_TOP_CMD);
2627 host->save_para.emmc50_pad_ds_tune =
2628 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2629 } else {
2630 host->save_para.pad_tune = readl(host->base + tune_reg);
2631 }
2632 }
2633
msdc_restore_reg(struct msdc_host * host)2634 static void msdc_restore_reg(struct msdc_host *host)
2635 {
2636 struct mmc_host *mmc = mmc_from_priv(host);
2637 u32 tune_reg = host->dev_comp->pad_tune_reg;
2638
2639 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2640 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2641 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2642 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2643 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2644 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2645 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2646 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2647 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2648 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2649 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2650 if (host->top_base) {
2651 writel(host->save_para.emmc_top_control,
2652 host->top_base + EMMC_TOP_CONTROL);
2653 writel(host->save_para.emmc_top_cmd,
2654 host->top_base + EMMC_TOP_CMD);
2655 writel(host->save_para.emmc50_pad_ds_tune,
2656 host->top_base + EMMC50_PAD_DS_TUNE);
2657 } else {
2658 writel(host->save_para.pad_tune, host->base + tune_reg);
2659 }
2660
2661 if (sdio_irq_claimed(mmc))
2662 __msdc_enable_sdio_irq(host, 1);
2663 }
2664
msdc_runtime_suspend(struct device * dev)2665 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2666 {
2667 struct mmc_host *mmc = dev_get_drvdata(dev);
2668 struct msdc_host *host = mmc_priv(mmc);
2669
2670 msdc_save_reg(host);
2671 msdc_gate_clock(host);
2672 return 0;
2673 }
2674
msdc_runtime_resume(struct device * dev)2675 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2676 {
2677 struct mmc_host *mmc = dev_get_drvdata(dev);
2678 struct msdc_host *host = mmc_priv(mmc);
2679
2680 msdc_ungate_clock(host);
2681 msdc_restore_reg(host);
2682 return 0;
2683 }
2684
msdc_suspend(struct device * dev)2685 static int __maybe_unused msdc_suspend(struct device *dev)
2686 {
2687 struct mmc_host *mmc = dev_get_drvdata(dev);
2688 int ret;
2689
2690 if (mmc->caps2 & MMC_CAP2_CQE) {
2691 ret = cqhci_suspend(mmc);
2692 if (ret)
2693 return ret;
2694 }
2695
2696 return pm_runtime_force_suspend(dev);
2697 }
2698
msdc_resume(struct device * dev)2699 static int __maybe_unused msdc_resume(struct device *dev)
2700 {
2701 return pm_runtime_force_resume(dev);
2702 }
2703
2704 static const struct dev_pm_ops msdc_dev_pm_ops = {
2705 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
2706 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2707 };
2708
2709 static struct platform_driver mt_msdc_driver = {
2710 .probe = msdc_drv_probe,
2711 .remove = msdc_drv_remove,
2712 .driver = {
2713 .name = "mtk-msdc",
2714 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2715 .of_match_table = msdc_of_ids,
2716 .pm = &msdc_dev_pm_ops,
2717 },
2718 };
2719
2720 module_platform_driver(mt_msdc_driver);
2721 MODULE_LICENSE("GPL v2");
2722 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
2723