1 // SPDX-License-Identifier: MIT
2
3 #include <drm/drm_debugfs.h>
4 #include <drm/drm_dp_mst_helper.h>
5 #include <drm/drm_fb_helper.h>
6 #include <drm/drm_file.h>
7 #include <drm/drm_probe_helper.h>
8
9 #include "atom.h"
10 #include "ni_reg.h"
11 #include "radeon.h"
12
13 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
14
radeon_atom_set_enc_offset(int id)15 static int radeon_atom_set_enc_offset(int id)
16 {
17 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
18 EVERGREEN_CRTC1_REGISTER_OFFSET,
19 EVERGREEN_CRTC2_REGISTER_OFFSET,
20 EVERGREEN_CRTC3_REGISTER_OFFSET,
21 EVERGREEN_CRTC4_REGISTER_OFFSET,
22 EVERGREEN_CRTC5_REGISTER_OFFSET,
23 0x13830 - 0x7030 };
24
25 return offsets[id];
26 }
27
radeon_dp_mst_set_be_cntl(struct radeon_encoder * primary,struct radeon_encoder_mst * mst_enc,enum radeon_hpd_id hpd,bool enable)28 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
29 struct radeon_encoder_mst *mst_enc,
30 enum radeon_hpd_id hpd, bool enable)
31 {
32 struct drm_device *dev = primary->base.dev;
33 struct radeon_device *rdev = dev->dev_private;
34 uint32_t reg;
35 int retries = 0;
36 uint32_t temp;
37
38 reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
39
40 /* set MST mode */
41 reg &= ~NI_DIG_FE_DIG_MODE(7);
42 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
43
44 if (enable)
45 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
46 else
47 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
48
49 reg |= NI_DIG_HPD_SELECT(hpd);
50 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
51 WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
52
53 if (enable) {
54 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
55
56 do {
57 temp = RREG32(NI_DIG_FE_CNTL + offset);
58 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
59 if (retries == 10000)
60 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
61 }
62 return 0;
63 }
64
radeon_dp_mst_set_stream_attrib(struct radeon_encoder * primary,int stream_number,int fe,int slots)65 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
66 int stream_number,
67 int fe,
68 int slots)
69 {
70 struct drm_device *dev = primary->base.dev;
71 struct radeon_device *rdev = dev->dev_private;
72 u32 temp, val;
73 int retries = 0;
74 int satreg, satidx;
75
76 satreg = stream_number >> 1;
77 satidx = stream_number & 1;
78
79 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
80
81 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
82
83 val <<= (16 * satidx);
84
85 temp &= ~(0xffff << (16 * satidx));
86
87 temp |= val;
88
89 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
90 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
91
92 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
93
94 do {
95 unsigned value1, value2;
96 udelay(10);
97 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
98
99 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
100 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
101
102 if (!value1 && !value2)
103 break;
104 } while (retries++ < 50);
105
106 if (retries == 10000)
107 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
108
109 /* MTP 16 ? */
110 return 0;
111 }
112
radeon_dp_mst_update_stream_attribs(struct radeon_connector * mst_conn,struct radeon_encoder * primary)113 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
114 struct radeon_encoder *primary)
115 {
116 struct drm_device *dev = mst_conn->base.dev;
117 struct stream_attribs new_attribs[6];
118 int i;
119 int idx = 0;
120 struct radeon_connector *radeon_connector;
121 struct drm_connector *connector;
122
123 memset(new_attribs, 0, sizeof(new_attribs));
124 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
125 struct radeon_encoder *subenc;
126 struct radeon_encoder_mst *mst_enc;
127
128 radeon_connector = to_radeon_connector(connector);
129 if (!radeon_connector->is_mst_connector)
130 continue;
131
132 if (radeon_connector->mst_port != mst_conn)
133 continue;
134
135 subenc = radeon_connector->mst_encoder;
136 mst_enc = subenc->enc_priv;
137
138 if (!mst_enc->enc_active)
139 continue;
140
141 new_attribs[idx].fe = mst_enc->fe;
142 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
143 idx++;
144 }
145
146 for (i = 0; i < idx; i++) {
147 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
148 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
149 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
150 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
151 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
152 }
153 }
154
155 for (i = idx; i < mst_conn->enabled_attribs; i++) {
156 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
157 mst_conn->cur_stream_attribs[i].fe = 0;
158 mst_conn->cur_stream_attribs[i].slots = 0;
159 }
160 mst_conn->enabled_attribs = idx;
161 return 0;
162 }
163
radeon_dp_mst_set_vcp_size(struct radeon_encoder * mst,s64 avg_time_slots_per_mtp)164 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
165 {
166 struct drm_device *dev = mst->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168 struct radeon_encoder_mst *mst_enc = mst->enc_priv;
169 uint32_t val, temp;
170 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
171 int retries = 0;
172 uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
173 uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
174
175 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
176
177 WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
178
179 do {
180 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
181 udelay(10);
182 } while ((temp & 0x1) && (retries++ < 10000));
183
184 if (retries >= 10000)
185 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
186 return 0;
187 }
188
radeon_dp_mst_get_ddc_modes(struct drm_connector * connector)189 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
190 {
191 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
192 struct radeon_connector *master = radeon_connector->mst_port;
193 struct edid *edid;
194 int ret = 0;
195
196 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
197 radeon_connector->edid = edid;
198 DRM_DEBUG_KMS("edid retrieved %p\n", edid);
199 if (radeon_connector->edid) {
200 drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
201 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
202 return ret;
203 }
204 drm_connector_update_edid_property(&radeon_connector->base, NULL);
205
206 return ret;
207 }
208
radeon_dp_mst_get_modes(struct drm_connector * connector)209 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
210 {
211 return radeon_dp_mst_get_ddc_modes(connector);
212 }
213
214 static enum drm_mode_status
radeon_dp_mst_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)215 radeon_dp_mst_mode_valid(struct drm_connector *connector,
216 struct drm_display_mode *mode)
217 {
218 /* TODO - validate mode against available PBN for link */
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
221
222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
224
225 return MODE_OK;
226 }
227
228 static struct
radeon_mst_best_encoder(struct drm_connector * connector)229 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
230 {
231 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
232
233 return &radeon_connector->mst_encoder->base;
234 }
235
236 static int
radeon_dp_mst_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)237 radeon_dp_mst_detect(struct drm_connector *connector,
238 struct drm_modeset_acquire_ctx *ctx,
239 bool force)
240 {
241 struct radeon_connector *radeon_connector =
242 to_radeon_connector(connector);
243 struct radeon_connector *master = radeon_connector->mst_port;
244
245 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
246 radeon_connector->port);
247 }
248
249 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
250 .get_modes = radeon_dp_mst_get_modes,
251 .mode_valid = radeon_dp_mst_mode_valid,
252 .best_encoder = radeon_mst_best_encoder,
253 .detect_ctx = radeon_dp_mst_detect,
254 };
255
256 static void
radeon_dp_mst_connector_destroy(struct drm_connector * connector)257 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
258 {
259 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
260 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
261
262 drm_encoder_cleanup(&radeon_encoder->base);
263 kfree(radeon_encoder);
264 drm_connector_cleanup(connector);
265 kfree(radeon_connector);
266 }
267
268 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
269 .dpms = drm_helper_connector_dpms,
270 .fill_modes = drm_helper_probe_single_connector_modes,
271 .destroy = radeon_dp_mst_connector_destroy,
272 };
273
radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr * mgr,struct drm_dp_mst_port * port,const char * pathprop)274 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
275 struct drm_dp_mst_port *port,
276 const char *pathprop)
277 {
278 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
279 struct drm_device *dev = master->base.dev;
280 struct radeon_connector *radeon_connector;
281 struct drm_connector *connector;
282
283 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
284 if (!radeon_connector)
285 return NULL;
286
287 radeon_connector->is_mst_connector = true;
288 connector = &radeon_connector->base;
289 radeon_connector->port = port;
290 radeon_connector->mst_port = master;
291 DRM_DEBUG_KMS("\n");
292
293 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
294 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
295 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
296
297 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
298 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
299 drm_connector_set_path_property(connector, pathprop);
300
301 return connector;
302 }
303
304 static const struct drm_dp_mst_topology_cbs mst_cbs = {
305 .add_connector = radeon_dp_add_mst_connector,
306 };
307
308 static struct
radeon_mst_find_connector(struct drm_encoder * encoder)309 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
310 {
311 struct drm_device *dev = encoder->dev;
312 struct drm_connector *connector;
313
314 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
315 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
316 if (!connector->encoder)
317 continue;
318 if (!radeon_connector->is_mst_connector)
319 continue;
320
321 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
322 if (connector->encoder == encoder)
323 return radeon_connector;
324 }
325 return NULL;
326 }
327
radeon_dp_mst_prepare_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)328 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
329 {
330 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
331 struct drm_device *dev = crtc->dev;
332 struct radeon_device *rdev = dev->dev_private;
333 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
334 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
335 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
336 int dp_clock;
337 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
338
339 if (radeon_connector) {
340 radeon_connector->pixelclock_for_modeset = mode->clock;
341 if (radeon_connector->base.display_info.bpc)
342 radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
343 else
344 radeon_crtc->bpc = 8;
345 }
346
347 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
348 dp_clock = dig_connector->dp_clock;
349 radeon_crtc->ss_enabled =
350 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
351 ASIC_INTERNAL_SS_ON_DP,
352 dp_clock);
353 }
354
355 static void
radeon_mst_encoder_dpms(struct drm_encoder * encoder,int mode)356 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
357 {
358 struct drm_device *dev = encoder->dev;
359 struct radeon_device *rdev = dev->dev_private;
360 struct radeon_encoder *radeon_encoder, *primary;
361 struct radeon_encoder_mst *mst_enc;
362 struct radeon_encoder_atom_dig *dig_enc;
363 struct radeon_connector *radeon_connector;
364 struct drm_crtc *crtc;
365 struct radeon_crtc *radeon_crtc;
366 int ret, slots;
367 s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
368 if (!ASIC_IS_DCE5(rdev)) {
369 DRM_ERROR("got mst dpms on non-DCE5\n");
370 return;
371 }
372
373 radeon_connector = radeon_mst_find_connector(encoder);
374 if (!radeon_connector)
375 return;
376
377 radeon_encoder = to_radeon_encoder(encoder);
378
379 mst_enc = radeon_encoder->enc_priv;
380
381 primary = mst_enc->primary;
382
383 dig_enc = primary->enc_priv;
384
385 crtc = encoder->crtc;
386 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
387
388 switch (mode) {
389 case DRM_MODE_DPMS_ON:
390 dig_enc->active_mst_links++;
391
392 radeon_crtc = to_radeon_crtc(crtc);
393
394 if (dig_enc->active_mst_links == 1) {
395 mst_enc->fe = dig_enc->dig_encoder;
396 mst_enc->fe_from_be = true;
397 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
398
399 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
400 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
401 0, 0, dig_enc->dig_encoder);
402
403 if (radeon_dp_needs_link_train(mst_enc->connector) ||
404 dig_enc->active_mst_links == 1) {
405 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
406 }
407
408 } else {
409 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
410 if (mst_enc->fe == -1)
411 DRM_ERROR("failed to get frontend for dig encoder\n");
412 mst_enc->fe_from_be = false;
413 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
414 }
415
416 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
417 dig_enc->linkb, radeon_crtc->crtc_id);
418
419 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
420 mst_enc->pbn);
421 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
422 radeon_connector->port,
423 mst_enc->pbn, slots);
424 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
425
426 radeon_dp_mst_set_be_cntl(primary, mst_enc,
427 radeon_connector->mst_port->hpd.hpd, true);
428
429 mst_enc->enc_active = true;
430 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
431
432 fixed_pbn = drm_int2fixp(mst_enc->pbn);
433 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
434 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
435 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
436
437 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
438 mst_enc->fe);
439 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
440
441 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
442
443 break;
444 case DRM_MODE_DPMS_STANDBY:
445 case DRM_MODE_DPMS_SUSPEND:
446 case DRM_MODE_DPMS_OFF:
447 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
448
449 if (!mst_enc->enc_active)
450 return;
451
452 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
453 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
454
455 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
456 /* and this can also fail */
457 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
458
459 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
460
461 mst_enc->enc_active = false;
462 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
463
464 radeon_dp_mst_set_be_cntl(primary, mst_enc,
465 radeon_connector->mst_port->hpd.hpd, false);
466 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
467 mst_enc->fe);
468
469 if (!mst_enc->fe_from_be)
470 radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
471
472 mst_enc->fe_from_be = false;
473 dig_enc->active_mst_links--;
474 if (dig_enc->active_mst_links == 0) {
475 /* drop link */
476 }
477
478 break;
479 }
480
481 }
482
radeon_mst_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)483 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
484 const struct drm_display_mode *mode,
485 struct drm_display_mode *adjusted_mode)
486 {
487 struct radeon_encoder_mst *mst_enc;
488 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
489 struct radeon_connector_atom_dig *dig_connector;
490 int bpp = 24;
491
492 mst_enc = radeon_encoder->enc_priv;
493
494 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false);
495
496 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
497 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
498 mst_enc->primary->active_device, mst_enc->primary->devices,
499 mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
500
501
502 drm_mode_set_crtcinfo(adjusted_mode, 0);
503 dig_connector = mst_enc->connector->con_priv;
504 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
505 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
506 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
507 dig_connector->dp_lane_count, dig_connector->dp_clock);
508 return true;
509 }
510
radeon_mst_encoder_prepare(struct drm_encoder * encoder)511 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
512 {
513 struct radeon_connector *radeon_connector;
514 struct radeon_encoder *radeon_encoder, *primary;
515 struct radeon_encoder_mst *mst_enc;
516 struct radeon_encoder_atom_dig *dig_enc;
517
518 radeon_connector = radeon_mst_find_connector(encoder);
519 if (!radeon_connector) {
520 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
521 return;
522 }
523 radeon_encoder = to_radeon_encoder(encoder);
524
525 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
526
527 mst_enc = radeon_encoder->enc_priv;
528
529 primary = mst_enc->primary;
530
531 dig_enc = primary->enc_priv;
532
533 mst_enc->port = radeon_connector->port;
534
535 if (dig_enc->dig_encoder == -1) {
536 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
537 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
538 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
539
540
541 }
542 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
543 }
544
545 static void
radeon_mst_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)546 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
547 struct drm_display_mode *mode,
548 struct drm_display_mode *adjusted_mode)
549 {
550 DRM_DEBUG_KMS("\n");
551 }
552
radeon_mst_encoder_commit(struct drm_encoder * encoder)553 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
554 {
555 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
556 DRM_DEBUG_KMS("\n");
557 }
558
559 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
560 .dpms = radeon_mst_encoder_dpms,
561 .mode_fixup = radeon_mst_mode_fixup,
562 .prepare = radeon_mst_encoder_prepare,
563 .mode_set = radeon_mst_encoder_mode_set,
564 .commit = radeon_mst_encoder_commit,
565 };
566
radeon_dp_mst_encoder_destroy(struct drm_encoder * encoder)567 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
568 {
569 drm_encoder_cleanup(encoder);
570 kfree(encoder);
571 }
572
573 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
574 .destroy = radeon_dp_mst_encoder_destroy,
575 };
576
577 static struct radeon_encoder *
radeon_dp_create_fake_mst_encoder(struct radeon_connector * connector)578 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
579 {
580 struct drm_device *dev = connector->base.dev;
581 struct radeon_device *rdev = dev->dev_private;
582 struct radeon_encoder *radeon_encoder;
583 struct radeon_encoder_mst *mst_enc;
584 struct drm_encoder *encoder;
585 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
586 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
587
588 DRM_DEBUG_KMS("enc master is %p\n", enc_master);
589 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
590 if (!radeon_encoder)
591 return NULL;
592
593 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
594 if (!radeon_encoder->enc_priv) {
595 kfree(radeon_encoder);
596 return NULL;
597 }
598 encoder = &radeon_encoder->base;
599 switch (rdev->num_crtc) {
600 case 1:
601 encoder->possible_crtcs = 0x1;
602 break;
603 case 2:
604 default:
605 encoder->possible_crtcs = 0x3;
606 break;
607 case 4:
608 encoder->possible_crtcs = 0xf;
609 break;
610 case 6:
611 encoder->possible_crtcs = 0x3f;
612 break;
613 }
614
615 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
616 DRM_MODE_ENCODER_DPMST, NULL);
617 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
618
619 mst_enc = radeon_encoder->enc_priv;
620 mst_enc->connector = connector;
621 mst_enc->primary = to_radeon_encoder(enc_master);
622 radeon_encoder->is_mst_encoder = true;
623 return radeon_encoder;
624 }
625
626 int
radeon_dp_mst_init(struct radeon_connector * radeon_connector)627 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
628 {
629 struct drm_device *dev = radeon_connector->base.dev;
630
631 if (!radeon_connector->ddc_bus->has_aux)
632 return 0;
633
634 radeon_connector->mst_mgr.cbs = &mst_cbs;
635 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
636 &radeon_connector->ddc_bus->aux, 16, 6,
637 radeon_connector->base.base.id);
638 }
639
640 int
radeon_dp_mst_probe(struct radeon_connector * radeon_connector)641 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
642 {
643 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
644 struct drm_device *dev = radeon_connector->base.dev;
645 struct radeon_device *rdev = dev->dev_private;
646 int ret;
647 u8 msg[1];
648
649 if (!radeon_mst)
650 return 0;
651
652 if (!ASIC_IS_DCE5(rdev))
653 return 0;
654
655 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
656 return 0;
657
658 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
659 1);
660 if (ret) {
661 if (msg[0] & DP_MST_CAP) {
662 DRM_DEBUG_KMS("Sink is MST capable\n");
663 dig_connector->is_mst = true;
664 } else {
665 DRM_DEBUG_KMS("Sink is not MST capable\n");
666 dig_connector->is_mst = false;
667 }
668
669 }
670 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
671 dig_connector->is_mst);
672 return dig_connector->is_mst;
673 }
674
675 int
radeon_dp_mst_check_status(struct radeon_connector * radeon_connector)676 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
677 {
678 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
679 int retry;
680
681 if (dig_connector->is_mst) {
682 u8 esi[16] = { 0 };
683 int dret;
684 int ret = 0;
685 bool handled;
686
687 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
688 DP_SINK_COUNT_ESI, esi, 8);
689 go_again:
690 if (dret == 8) {
691 DRM_DEBUG_KMS("got esi %3ph\n", esi);
692 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
693
694 if (handled) {
695 for (retry = 0; retry < 3; retry++) {
696 int wret;
697 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
698 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
699 if (wret == 3)
700 break;
701 }
702
703 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
704 DP_SINK_COUNT_ESI, esi, 8);
705 if (dret == 8) {
706 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
707 goto go_again;
708 }
709 } else
710 ret = 0;
711
712 return ret;
713 } else {
714 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
715 dig_connector->is_mst = false;
716 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
717 dig_connector->is_mst);
718 /* send a hotplug event */
719 }
720 }
721 return -EINVAL;
722 }
723
724 #if defined(CONFIG_DEBUG_FS)
725
radeon_debugfs_mst_info(struct seq_file * m,void * data)726 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
727 {
728 struct drm_info_node *node = (struct drm_info_node *)m->private;
729 struct drm_device *dev = node->minor->dev;
730 struct drm_connector *connector;
731 struct radeon_connector *radeon_connector;
732 struct radeon_connector_atom_dig *dig_connector;
733 int i;
734
735 drm_modeset_lock_all(dev);
736 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
737 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
738 continue;
739
740 radeon_connector = to_radeon_connector(connector);
741 dig_connector = radeon_connector->con_priv;
742 if (radeon_connector->is_mst_connector)
743 continue;
744 if (!dig_connector->is_mst)
745 continue;
746 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
747
748 for (i = 0; i < radeon_connector->enabled_attribs; i++)
749 seq_printf(m, "attrib %d: %d %d\n", i,
750 radeon_connector->cur_stream_attribs[i].fe,
751 radeon_connector->cur_stream_attribs[i].slots);
752 }
753 drm_modeset_unlock_all(dev);
754 return 0;
755 }
756
757 static struct drm_info_list radeon_debugfs_mst_list[] = {
758 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
759 };
760 #endif
761
radeon_mst_debugfs_init(struct radeon_device * rdev)762 int radeon_mst_debugfs_init(struct radeon_device *rdev)
763 {
764 #if defined(CONFIG_DEBUG_FS)
765 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);
766 #endif
767 return 0;
768 }
769