11bbe92f5SDave Martin /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 260021220SAndre Przywara #ifndef _ASM_X86_KVM_H 360021220SAndre Przywara #define _ASM_X86_KVM_H 460021220SAndre Przywara 560021220SAndre Przywara /* 660021220SAndre Przywara * KVM x86 specific structures and definitions 760021220SAndre Przywara * 860021220SAndre Przywara */ 960021220SAndre Przywara 1085aaadf6SAnup Patel #include <linux/const.h> 1185aaadf6SAnup Patel #include <linux/bits.h> 1260021220SAndre Przywara #include <linux/types.h> 1360021220SAndre Przywara #include <linux/ioctl.h> 14be986824SAnup Patel #include <linux/stddef.h> 1560021220SAndre Przywara 161bbe92f5SDave Martin #define KVM_PIO_PAGE_OFFSET 1 171bbe92f5SDave Martin #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 185968b5ffSAnup Patel #define KVM_DIRTY_LOG_PAGE_OFFSET 64 191bbe92f5SDave Martin 2060021220SAndre Przywara #define DE_VECTOR 0 2160021220SAndre Przywara #define DB_VECTOR 1 2260021220SAndre Przywara #define BP_VECTOR 3 2360021220SAndre Przywara #define OF_VECTOR 4 2460021220SAndre Przywara #define BR_VECTOR 5 2560021220SAndre Przywara #define UD_VECTOR 6 2660021220SAndre Przywara #define NM_VECTOR 7 2760021220SAndre Przywara #define DF_VECTOR 8 2860021220SAndre Przywara #define TS_VECTOR 10 2960021220SAndre Przywara #define NP_VECTOR 11 3060021220SAndre Przywara #define SS_VECTOR 12 3160021220SAndre Przywara #define GP_VECTOR 13 3260021220SAndre Przywara #define PF_VECTOR 14 3360021220SAndre Przywara #define MF_VECTOR 16 3460021220SAndre Przywara #define AC_VECTOR 17 3560021220SAndre Przywara #define MC_VECTOR 18 3660021220SAndre Przywara #define XM_VECTOR 19 3760021220SAndre Przywara #define VE_VECTOR 20 3860021220SAndre Przywara 3960021220SAndre Przywara /* Select x86 specific features in <linux/kvm.h> */ 4060021220SAndre Przywara #define __KVM_HAVE_PIT 4160021220SAndre Przywara #define __KVM_HAVE_IOAPIC 4260021220SAndre Przywara #define __KVM_HAVE_IRQ_LINE 4360021220SAndre Przywara #define __KVM_HAVE_MSI 4460021220SAndre Przywara #define __KVM_HAVE_USER_NMI 4560021220SAndre Przywara #define __KVM_HAVE_MSIX 4660021220SAndre Przywara #define __KVM_HAVE_MCE 4760021220SAndre Przywara #define __KVM_HAVE_PIT_STATE2 4860021220SAndre Przywara #define __KVM_HAVE_XEN_HVM 4960021220SAndre Przywara #define __KVM_HAVE_VCPU_EVENTS 5060021220SAndre Przywara #define __KVM_HAVE_DEBUGREGS 5160021220SAndre Przywara #define __KVM_HAVE_XSAVE 5260021220SAndre Przywara #define __KVM_HAVE_XCRS 5360021220SAndre Przywara 5460021220SAndre Przywara /* Architectural interrupt line count. */ 5560021220SAndre Przywara #define KVM_NR_INTERRUPTS 256 5660021220SAndre Przywara 5760021220SAndre Przywara /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ 5860021220SAndre Przywara struct kvm_pic_state { 5960021220SAndre Przywara __u8 last_irr; /* edge detection */ 6060021220SAndre Przywara __u8 irr; /* interrupt request register */ 6160021220SAndre Przywara __u8 imr; /* interrupt mask register */ 6260021220SAndre Przywara __u8 isr; /* interrupt service register */ 6360021220SAndre Przywara __u8 priority_add; /* highest irq priority */ 6460021220SAndre Przywara __u8 irq_base; 6560021220SAndre Przywara __u8 read_reg_select; 6660021220SAndre Przywara __u8 poll; 6760021220SAndre Przywara __u8 special_mask; 6860021220SAndre Przywara __u8 init_state; 6960021220SAndre Przywara __u8 auto_eoi; 7060021220SAndre Przywara __u8 rotate_on_auto_eoi; 7160021220SAndre Przywara __u8 special_fully_nested_mode; 7260021220SAndre Przywara __u8 init4; /* true if 4 byte init */ 7360021220SAndre Przywara __u8 elcr; /* PIIX edge/trigger selection */ 7460021220SAndre Przywara __u8 elcr_mask; 7560021220SAndre Przywara }; 7660021220SAndre Przywara 7760021220SAndre Przywara #define KVM_IOAPIC_NUM_PINS 24 7860021220SAndre Przywara struct kvm_ioapic_state { 7960021220SAndre Przywara __u64 base_address; 8060021220SAndre Przywara __u32 ioregsel; 8160021220SAndre Przywara __u32 id; 8260021220SAndre Przywara __u32 irr; 8360021220SAndre Przywara __u32 pad; 8460021220SAndre Przywara union { 8560021220SAndre Przywara __u64 bits; 8660021220SAndre Przywara struct { 8760021220SAndre Przywara __u8 vector; 8860021220SAndre Przywara __u8 delivery_mode:3; 8960021220SAndre Przywara __u8 dest_mode:1; 9060021220SAndre Przywara __u8 delivery_status:1; 9160021220SAndre Przywara __u8 polarity:1; 9260021220SAndre Przywara __u8 remote_irr:1; 9360021220SAndre Przywara __u8 trig_mode:1; 9460021220SAndre Przywara __u8 mask:1; 9560021220SAndre Przywara __u8 reserve:7; 9660021220SAndre Przywara __u8 reserved[4]; 9760021220SAndre Przywara __u8 dest_id; 9860021220SAndre Przywara } fields; 9960021220SAndre Przywara } redirtbl[KVM_IOAPIC_NUM_PINS]; 10060021220SAndre Przywara }; 10160021220SAndre Przywara 10260021220SAndre Przywara #define KVM_IRQCHIP_PIC_MASTER 0 10360021220SAndre Przywara #define KVM_IRQCHIP_PIC_SLAVE 1 10460021220SAndre Przywara #define KVM_IRQCHIP_IOAPIC 2 10560021220SAndre Przywara #define KVM_NR_IRQCHIPS 3 10660021220SAndre Przywara 107b37ed70eSAndre Przywara #define KVM_RUN_X86_SMM (1 << 0) 1085968b5ffSAnup Patel #define KVM_RUN_X86_BUS_LOCK (1 << 1) 109b37ed70eSAndre Przywara 11060021220SAndre Przywara /* for KVM_GET_REGS and KVM_SET_REGS */ 11160021220SAndre Przywara struct kvm_regs { 11260021220SAndre Przywara /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 11360021220SAndre Przywara __u64 rax, rbx, rcx, rdx; 11460021220SAndre Przywara __u64 rsi, rdi, rsp, rbp; 11560021220SAndre Przywara __u64 r8, r9, r10, r11; 11660021220SAndre Przywara __u64 r12, r13, r14, r15; 11760021220SAndre Przywara __u64 rip, rflags; 11860021220SAndre Przywara }; 11960021220SAndre Przywara 12060021220SAndre Przywara /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ 12160021220SAndre Przywara #define KVM_APIC_REG_SIZE 0x400 12260021220SAndre Przywara struct kvm_lapic_state { 12360021220SAndre Przywara char regs[KVM_APIC_REG_SIZE]; 12460021220SAndre Przywara }; 12560021220SAndre Przywara 12660021220SAndre Przywara struct kvm_segment { 12760021220SAndre Przywara __u64 base; 12860021220SAndre Przywara __u32 limit; 12960021220SAndre Przywara __u16 selector; 13060021220SAndre Przywara __u8 type; 13160021220SAndre Przywara __u8 present, dpl, db, s, l, g, avl; 13260021220SAndre Przywara __u8 unusable; 13360021220SAndre Przywara __u8 padding; 13460021220SAndre Przywara }; 13560021220SAndre Przywara 13660021220SAndre Przywara struct kvm_dtable { 13760021220SAndre Przywara __u64 base; 13860021220SAndre Przywara __u16 limit; 13960021220SAndre Przywara __u16 padding[3]; 14060021220SAndre Przywara }; 14160021220SAndre Przywara 14260021220SAndre Przywara 14360021220SAndre Przywara /* for KVM_GET_SREGS and KVM_SET_SREGS */ 14460021220SAndre Przywara struct kvm_sregs { 14560021220SAndre Przywara /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ 14660021220SAndre Przywara struct kvm_segment cs, ds, es, fs, gs, ss; 14760021220SAndre Przywara struct kvm_segment tr, ldt; 14860021220SAndre Przywara struct kvm_dtable gdt, idt; 14960021220SAndre Przywara __u64 cr0, cr2, cr3, cr4, cr8; 15060021220SAndre Przywara __u64 efer; 15160021220SAndre Przywara __u64 apic_base; 15260021220SAndre Przywara __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 15360021220SAndre Przywara }; 15460021220SAndre Przywara 1555968b5ffSAnup Patel struct kvm_sregs2 { 1565968b5ffSAnup Patel /* out (KVM_GET_SREGS2) / in (KVM_SET_SREGS2) */ 1575968b5ffSAnup Patel struct kvm_segment cs, ds, es, fs, gs, ss; 1585968b5ffSAnup Patel struct kvm_segment tr, ldt; 1595968b5ffSAnup Patel struct kvm_dtable gdt, idt; 1605968b5ffSAnup Patel __u64 cr0, cr2, cr3, cr4, cr8; 1615968b5ffSAnup Patel __u64 efer; 1625968b5ffSAnup Patel __u64 apic_base; 1635968b5ffSAnup Patel __u64 flags; 1645968b5ffSAnup Patel __u64 pdptrs[4]; 1655968b5ffSAnup Patel }; 1665968b5ffSAnup Patel #define KVM_SREGS2_FLAGS_PDPTRS_VALID 1 1675968b5ffSAnup Patel 16860021220SAndre Przywara /* for KVM_GET_FPU and KVM_SET_FPU */ 16960021220SAndre Przywara struct kvm_fpu { 17060021220SAndre Przywara __u8 fpr[8][16]; 17160021220SAndre Przywara __u16 fcw; 17260021220SAndre Przywara __u16 fsw; 17360021220SAndre Przywara __u8 ftwx; /* in fxsave format */ 17460021220SAndre Przywara __u8 pad1; 17560021220SAndre Przywara __u16 last_opcode; 17660021220SAndre Przywara __u64 last_ip; 17760021220SAndre Przywara __u64 last_dp; 17860021220SAndre Przywara __u8 xmm[16][16]; 17960021220SAndre Przywara __u32 mxcsr; 18060021220SAndre Przywara __u32 pad2; 18160021220SAndre Przywara }; 18260021220SAndre Przywara 18360021220SAndre Przywara struct kvm_msr_entry { 18460021220SAndre Przywara __u32 index; 18560021220SAndre Przywara __u32 reserved; 18660021220SAndre Przywara __u64 data; 18760021220SAndre Przywara }; 18860021220SAndre Przywara 18960021220SAndre Przywara /* for KVM_GET_MSRS and KVM_SET_MSRS */ 19060021220SAndre Przywara struct kvm_msrs { 19160021220SAndre Przywara __u32 nmsrs; /* number of msrs in entries */ 19260021220SAndre Przywara __u32 pad; 19360021220SAndre Przywara 1948d0facecSAnup Patel struct kvm_msr_entry entries[]; 19560021220SAndre Przywara }; 19660021220SAndre Przywara 19760021220SAndre Przywara /* for KVM_GET_MSR_INDEX_LIST */ 19860021220SAndre Przywara struct kvm_msr_list { 19960021220SAndre Przywara __u32 nmsrs; /* number of msrs in entries */ 2008d0facecSAnup Patel __u32 indices[]; 20160021220SAndre Przywara }; 20260021220SAndre Przywara 2035968b5ffSAnup Patel /* Maximum size of any access bitmap in bytes */ 2045968b5ffSAnup Patel #define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600 2055968b5ffSAnup Patel 2065968b5ffSAnup Patel /* for KVM_X86_SET_MSR_FILTER */ 2075968b5ffSAnup Patel struct kvm_msr_filter_range { 2085968b5ffSAnup Patel #define KVM_MSR_FILTER_READ (1 << 0) 2095968b5ffSAnup Patel #define KVM_MSR_FILTER_WRITE (1 << 1) 210be986824SAnup Patel #define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ | \ 211be986824SAnup Patel KVM_MSR_FILTER_WRITE) 2125968b5ffSAnup Patel __u32 flags; 2135968b5ffSAnup Patel __u32 nmsrs; /* number of msrs in bitmap */ 2145968b5ffSAnup Patel __u32 base; /* MSR index the bitmap starts at */ 2155968b5ffSAnup Patel __u8 *bitmap; /* a 1 bit allows the operations in flags, 0 denies */ 2165968b5ffSAnup Patel }; 2175968b5ffSAnup Patel 2185968b5ffSAnup Patel #define KVM_MSR_FILTER_MAX_RANGES 16 2195968b5ffSAnup Patel struct kvm_msr_filter { 220be986824SAnup Patel #ifndef __KERNEL__ 2215968b5ffSAnup Patel #define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0) 222be986824SAnup Patel #endif 2235968b5ffSAnup Patel #define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0) 224be986824SAnup Patel #define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY) 2255968b5ffSAnup Patel __u32 flags; 2265968b5ffSAnup Patel struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES]; 2275968b5ffSAnup Patel }; 22860021220SAndre Przywara 22960021220SAndre Przywara struct kvm_cpuid_entry { 23060021220SAndre Przywara __u32 function; 23160021220SAndre Przywara __u32 eax; 23260021220SAndre Przywara __u32 ebx; 23360021220SAndre Przywara __u32 ecx; 23460021220SAndre Przywara __u32 edx; 23560021220SAndre Przywara __u32 padding; 23660021220SAndre Przywara }; 23760021220SAndre Przywara 23860021220SAndre Przywara /* for KVM_SET_CPUID */ 23960021220SAndre Przywara struct kvm_cpuid { 24060021220SAndre Przywara __u32 nent; 24160021220SAndre Przywara __u32 padding; 2428d0facecSAnup Patel struct kvm_cpuid_entry entries[]; 24360021220SAndre Przywara }; 24460021220SAndre Przywara 24560021220SAndre Przywara struct kvm_cpuid_entry2 { 24660021220SAndre Przywara __u32 function; 24760021220SAndre Przywara __u32 index; 24860021220SAndre Przywara __u32 flags; 24960021220SAndre Przywara __u32 eax; 25060021220SAndre Przywara __u32 ebx; 25160021220SAndre Przywara __u32 ecx; 25260021220SAndre Przywara __u32 edx; 25360021220SAndre Przywara __u32 padding[3]; 25460021220SAndre Przywara }; 25560021220SAndre Przywara 256764dfba1SAndre Przywara #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) 257764dfba1SAndre Przywara #define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) 258764dfba1SAndre Przywara #define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) 25960021220SAndre Przywara 26060021220SAndre Przywara /* for KVM_SET_CPUID2 */ 26160021220SAndre Przywara struct kvm_cpuid2 { 26260021220SAndre Przywara __u32 nent; 26360021220SAndre Przywara __u32 padding; 2648d0facecSAnup Patel struct kvm_cpuid_entry2 entries[]; 26560021220SAndre Przywara }; 26660021220SAndre Przywara 26760021220SAndre Przywara /* for KVM_GET_PIT and KVM_SET_PIT */ 26860021220SAndre Przywara struct kvm_pit_channel_state { 26960021220SAndre Przywara __u32 count; /* can be 65536 */ 27060021220SAndre Przywara __u16 latched_count; 27160021220SAndre Przywara __u8 count_latched; 27260021220SAndre Przywara __u8 status_latched; 27360021220SAndre Przywara __u8 status; 27460021220SAndre Przywara __u8 read_state; 27560021220SAndre Przywara __u8 write_state; 27660021220SAndre Przywara __u8 write_latch; 27760021220SAndre Przywara __u8 rw_mode; 27860021220SAndre Przywara __u8 mode; 27960021220SAndre Przywara __u8 bcd; 28060021220SAndre Przywara __u8 gate; 28160021220SAndre Przywara __s64 count_load_time; 28260021220SAndre Przywara }; 28360021220SAndre Przywara 28460021220SAndre Przywara struct kvm_debug_exit_arch { 28560021220SAndre Przywara __u32 exception; 28660021220SAndre Przywara __u32 pad; 28760021220SAndre Przywara __u64 pc; 28860021220SAndre Przywara __u64 dr6; 28960021220SAndre Przywara __u64 dr7; 29060021220SAndre Przywara }; 29160021220SAndre Przywara 29260021220SAndre Przywara #define KVM_GUESTDBG_USE_SW_BP 0x00010000 29360021220SAndre Przywara #define KVM_GUESTDBG_USE_HW_BP 0x00020000 29460021220SAndre Przywara #define KVM_GUESTDBG_INJECT_DB 0x00040000 29560021220SAndre Przywara #define KVM_GUESTDBG_INJECT_BP 0x00080000 2965968b5ffSAnup Patel #define KVM_GUESTDBG_BLOCKIRQ 0x00100000 29760021220SAndre Przywara 29860021220SAndre Przywara /* for KVM_SET_GUEST_DEBUG */ 29960021220SAndre Przywara struct kvm_guest_debug_arch { 30060021220SAndre Przywara __u64 debugreg[8]; 30160021220SAndre Przywara }; 30260021220SAndre Przywara 30360021220SAndre Przywara struct kvm_pit_state { 30460021220SAndre Przywara struct kvm_pit_channel_state channels[3]; 30560021220SAndre Przywara }; 30660021220SAndre Przywara 30760021220SAndre Przywara #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 3088d0facecSAnup Patel #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002 30960021220SAndre Przywara 31060021220SAndre Przywara struct kvm_pit_state2 { 31160021220SAndre Przywara struct kvm_pit_channel_state channels[3]; 31260021220SAndre Przywara __u32 flags; 31360021220SAndre Przywara __u32 reserved[9]; 31460021220SAndre Przywara }; 31560021220SAndre Przywara 31660021220SAndre Przywara struct kvm_reinject_control { 31760021220SAndre Przywara __u8 pit_reinject; 31860021220SAndre Przywara __u8 reserved[31]; 31960021220SAndre Przywara }; 32060021220SAndre Przywara 32160021220SAndre Przywara /* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ 32260021220SAndre Przywara #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 32360021220SAndre Przywara #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 32460021220SAndre Przywara #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 325b37ed70eSAndre Przywara #define KVM_VCPUEVENT_VALID_SMM 0x00000008 3261bbe92f5SDave Martin #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010 3278d0facecSAnup Patel #define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020 32860021220SAndre Przywara 32960021220SAndre Przywara /* Interrupt shadow states */ 33060021220SAndre Przywara #define KVM_X86_SHADOW_INT_MOV_SS 0x01 33160021220SAndre Przywara #define KVM_X86_SHADOW_INT_STI 0x02 33260021220SAndre Przywara 33360021220SAndre Przywara /* for KVM_GET/SET_VCPU_EVENTS */ 33460021220SAndre Przywara struct kvm_vcpu_events { 33560021220SAndre Przywara struct { 33660021220SAndre Przywara __u8 injected; 33760021220SAndre Przywara __u8 nr; 33860021220SAndre Przywara __u8 has_error_code; 3391bbe92f5SDave Martin __u8 pending; 34060021220SAndre Przywara __u32 error_code; 34160021220SAndre Przywara } exception; 34260021220SAndre Przywara struct { 34360021220SAndre Przywara __u8 injected; 34460021220SAndre Przywara __u8 nr; 34560021220SAndre Przywara __u8 soft; 34660021220SAndre Przywara __u8 shadow; 34760021220SAndre Przywara } interrupt; 34860021220SAndre Przywara struct { 34960021220SAndre Przywara __u8 injected; 35060021220SAndre Przywara __u8 pending; 35160021220SAndre Przywara __u8 masked; 35260021220SAndre Przywara __u8 pad; 35360021220SAndre Przywara } nmi; 35460021220SAndre Przywara __u32 sipi_vector; 35560021220SAndre Przywara __u32 flags; 356b37ed70eSAndre Przywara struct { 357b37ed70eSAndre Przywara __u8 smm; 358b37ed70eSAndre Przywara __u8 pending; 359b37ed70eSAndre Przywara __u8 smm_inside_nmi; 360b37ed70eSAndre Przywara __u8 latched_init; 361b37ed70eSAndre Przywara } smi; 3628d0facecSAnup Patel struct { 3638d0facecSAnup Patel __u8 pending; 3648d0facecSAnup Patel } triple_fault; 3658d0facecSAnup Patel __u8 reserved[26]; 3661bbe92f5SDave Martin __u8 exception_has_payload; 3671bbe92f5SDave Martin __u64 exception_payload; 36860021220SAndre Przywara }; 36960021220SAndre Przywara 37060021220SAndre Przywara /* for KVM_GET/SET_DEBUGREGS */ 37160021220SAndre Przywara struct kvm_debugregs { 37260021220SAndre Przywara __u64 db[4]; 37360021220SAndre Przywara __u64 dr6; 37460021220SAndre Przywara __u64 dr7; 37560021220SAndre Przywara __u64 flags; 37660021220SAndre Przywara __u64 reserved[9]; 37760021220SAndre Przywara }; 37860021220SAndre Przywara 379af1b793cSAlexandru Elisei /* for KVM_CAP_XSAVE and KVM_CAP_XSAVE2 */ 38060021220SAndre Przywara struct kvm_xsave { 381af1b793cSAlexandru Elisei /* 382af1b793cSAlexandru Elisei * KVM_GET_XSAVE2 and KVM_SET_XSAVE write and read as many bytes 383af1b793cSAlexandru Elisei * as are returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) 384af1b793cSAlexandru Elisei * respectively, when invoked on the vm file descriptor. 385af1b793cSAlexandru Elisei * 386af1b793cSAlexandru Elisei * The size value returned by KVM_CHECK_EXTENSION(KVM_CAP_XSAVE2) 387af1b793cSAlexandru Elisei * will always be at least 4096. Currently, it is only greater 388af1b793cSAlexandru Elisei * than 4096 if a dynamic feature has been enabled with 389af1b793cSAlexandru Elisei * ``arch_prctl()``, but this may change in the future. 390af1b793cSAlexandru Elisei * 391af1b793cSAlexandru Elisei * The offsets of the state save areas in struct kvm_xsave follow 392af1b793cSAlexandru Elisei * the contents of CPUID leaf 0xD on the host. 393af1b793cSAlexandru Elisei */ 39460021220SAndre Przywara __u32 region[1024]; 3958d0facecSAnup Patel __u32 extra[]; 39660021220SAndre Przywara }; 39760021220SAndre Przywara 39860021220SAndre Przywara #define KVM_MAX_XCRS 16 39960021220SAndre Przywara 40060021220SAndre Przywara struct kvm_xcr { 40160021220SAndre Przywara __u32 xcr; 40260021220SAndre Przywara __u32 reserved; 40360021220SAndre Przywara __u64 value; 40460021220SAndre Przywara }; 40560021220SAndre Przywara 40660021220SAndre Przywara struct kvm_xcrs { 40760021220SAndre Przywara __u32 nr_xcrs; 40860021220SAndre Przywara __u32 flags; 40960021220SAndre Przywara struct kvm_xcr xcrs[KVM_MAX_XCRS]; 41060021220SAndre Przywara __u64 padding[16]; 41160021220SAndre Przywara }; 41260021220SAndre Przywara 4131bbe92f5SDave Martin #define KVM_SYNC_X86_REGS (1UL << 0) 4141bbe92f5SDave Martin #define KVM_SYNC_X86_SREGS (1UL << 1) 4151bbe92f5SDave Martin #define KVM_SYNC_X86_EVENTS (1UL << 2) 4161bbe92f5SDave Martin 4171bbe92f5SDave Martin #define KVM_SYNC_X86_VALID_FIELDS \ 4181bbe92f5SDave Martin (KVM_SYNC_X86_REGS| \ 4191bbe92f5SDave Martin KVM_SYNC_X86_SREGS| \ 4201bbe92f5SDave Martin KVM_SYNC_X86_EVENTS) 4211bbe92f5SDave Martin 4221bbe92f5SDave Martin /* kvm_sync_regs struct included by kvm_run struct */ 42360021220SAndre Przywara struct kvm_sync_regs { 4241bbe92f5SDave Martin /* Members of this structure are potentially malicious. 4251bbe92f5SDave Martin * Care must be taken by code reading, esp. interpreting, 4261bbe92f5SDave Martin * data fields from them inside KVM to prevent TOCTOU and 4271bbe92f5SDave Martin * double-fetch types of vulnerabilities. 4281bbe92f5SDave Martin */ 4291bbe92f5SDave Martin struct kvm_regs regs; 4301bbe92f5SDave Martin struct kvm_sregs sregs; 4311bbe92f5SDave Martin struct kvm_vcpu_events events; 43260021220SAndre Przywara }; 43360021220SAndre Przywara 434b37ed70eSAndre Przywara #define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) 435b37ed70eSAndre Przywara #define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) 4361bbe92f5SDave Martin #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) 43766b24a33SWill Deacon #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) 43866b24a33SWill Deacon #define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) 4398d0facecSAnup Patel #define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5) 4408d0facecSAnup Patel #define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6) 44166b24a33SWill Deacon 44266b24a33SWill Deacon #define KVM_STATE_NESTED_FORMAT_VMX 0 4435968b5ffSAnup Patel #define KVM_STATE_NESTED_FORMAT_SVM 1 4441bbe92f5SDave Martin 4451bbe92f5SDave Martin #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 4461bbe92f5SDave Martin #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 4471bbe92f5SDave Martin #define KVM_STATE_NESTED_EVMCS 0x00000004 4485968b5ffSAnup Patel #define KVM_STATE_NESTED_MTF_PENDING 0x00000008 4495968b5ffSAnup Patel #define KVM_STATE_NESTED_GIF_SET 0x00000100 4501bbe92f5SDave Martin 4511bbe92f5SDave Martin #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 4521bbe92f5SDave Martin #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 4531bbe92f5SDave Martin 45466b24a33SWill Deacon #define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 45566b24a33SWill Deacon 4565968b5ffSAnup Patel #define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000 4575968b5ffSAnup Patel 4585968b5ffSAnup Patel #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 4595968b5ffSAnup Patel 460*01171537SAnup Patel /* vendor-independent attributes for system fd (group 0) */ 461*01171537SAnup Patel #define KVM_X86_GRP_SYSTEM 0 462af1b793cSAlexandru Elisei # define KVM_X86_XCOMP_GUEST_SUPP 0 463af1b793cSAlexandru Elisei 464*01171537SAnup Patel /* vendor-specific groups and attributes for system fd */ 465*01171537SAnup Patel #define KVM_X86_GRP_SEV 1 466*01171537SAnup Patel # define KVM_X86_SEV_VMSA_FEATURES 0 467*01171537SAnup Patel 46866b24a33SWill Deacon struct kvm_vmx_nested_state_data { 46966b24a33SWill Deacon __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; 47066b24a33SWill Deacon __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; 47166b24a33SWill Deacon }; 47266b24a33SWill Deacon 47366b24a33SWill Deacon struct kvm_vmx_nested_state_hdr { 4741bbe92f5SDave Martin __u64 vmxon_pa; 47566b24a33SWill Deacon __u64 vmcs12_pa; 4761bbe92f5SDave Martin 4771bbe92f5SDave Martin struct { 4781bbe92f5SDave Martin __u16 flags; 4791bbe92f5SDave Martin } smm; 4805968b5ffSAnup Patel 4815968b5ffSAnup Patel __u16 pad; 4825968b5ffSAnup Patel 4835968b5ffSAnup Patel __u32 flags; 4845968b5ffSAnup Patel __u64 preemption_timer_deadline; 4855968b5ffSAnup Patel }; 4865968b5ffSAnup Patel 4875968b5ffSAnup Patel struct kvm_svm_nested_state_data { 4885968b5ffSAnup Patel /* Save area only used if KVM_STATE_NESTED_RUN_PENDING. */ 4895968b5ffSAnup Patel __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE]; 4905968b5ffSAnup Patel }; 4915968b5ffSAnup Patel 4925968b5ffSAnup Patel struct kvm_svm_nested_state_hdr { 4935968b5ffSAnup Patel __u64 vmcb_pa; 4941bbe92f5SDave Martin }; 4951bbe92f5SDave Martin 4961bbe92f5SDave Martin /* for KVM_CAP_NESTED_STATE */ 4971bbe92f5SDave Martin struct kvm_nested_state { 4981bbe92f5SDave Martin __u16 flags; 4991bbe92f5SDave Martin __u16 format; 5001bbe92f5SDave Martin __u32 size; 5011bbe92f5SDave Martin 5021bbe92f5SDave Martin union { 50366b24a33SWill Deacon struct kvm_vmx_nested_state_hdr vmx; 5045968b5ffSAnup Patel struct kvm_svm_nested_state_hdr svm; 5051bbe92f5SDave Martin 5061bbe92f5SDave Martin /* Pad the header to 128 bytes. */ 5071bbe92f5SDave Martin __u8 pad[120]; 50866b24a33SWill Deacon } hdr; 50966b24a33SWill Deacon 51066b24a33SWill Deacon /* 51166b24a33SWill Deacon * Define data region as 0 bytes to preserve backwards-compatability 51266b24a33SWill Deacon * to old definition of kvm_nested_state in order to avoid changing 51366b24a33SWill Deacon * KVM_{GET,PUT}_NESTED_STATE ioctl values. 51466b24a33SWill Deacon */ 51566b24a33SWill Deacon union { 516be986824SAnup Patel __DECLARE_FLEX_ARRAY(struct kvm_vmx_nested_state_data, vmx); 517be986824SAnup Patel __DECLARE_FLEX_ARRAY(struct kvm_svm_nested_state_data, svm); 51866b24a33SWill Deacon } data; 5191bbe92f5SDave Martin }; 5201bbe92f5SDave Martin 52166b24a33SWill Deacon /* for KVM_CAP_PMU_EVENT_FILTER */ 52266b24a33SWill Deacon struct kvm_pmu_event_filter { 52366b24a33SWill Deacon __u32 action; 52466b24a33SWill Deacon __u32 nevents; 52566b24a33SWill Deacon __u32 fixed_counter_bitmap; 52666b24a33SWill Deacon __u32 flags; 52766b24a33SWill Deacon __u32 pad[4]; 5288d0facecSAnup Patel __u64 events[]; 5291bbe92f5SDave Martin }; 530b37ed70eSAndre Przywara 53166b24a33SWill Deacon #define KVM_PMU_EVENT_ALLOW 0 53266b24a33SWill Deacon #define KVM_PMU_EVENT_DENY 1 53366b24a33SWill Deacon 53485aaadf6SAnup Patel #define KVM_PMU_EVENT_FLAG_MASKED_EVENTS _BITUL(0) 535be986824SAnup Patel #define KVM_PMU_EVENT_FLAGS_VALID_MASK (KVM_PMU_EVENT_FLAG_MASKED_EVENTS) 536be986824SAnup Patel 53785aaadf6SAnup Patel /* for KVM_CAP_MCE */ 53885aaadf6SAnup Patel struct kvm_x86_mce { 53985aaadf6SAnup Patel __u64 status; 54085aaadf6SAnup Patel __u64 addr; 54185aaadf6SAnup Patel __u64 misc; 54285aaadf6SAnup Patel __u64 mcg_status; 54385aaadf6SAnup Patel __u8 bank; 54485aaadf6SAnup Patel __u8 pad1[7]; 54585aaadf6SAnup Patel __u64 pad2[3]; 54685aaadf6SAnup Patel }; 54785aaadf6SAnup Patel 54885aaadf6SAnup Patel /* for KVM_CAP_XEN_HVM */ 54985aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_HYPERCALL_MSR (1 << 0) 55085aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL (1 << 1) 55185aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_SHARED_INFO (1 << 2) 55285aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_RUNSTATE (1 << 3) 55385aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL (1 << 4) 55485aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_EVTCHN_SEND (1 << 5) 55585aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG (1 << 6) 55685aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE (1 << 7) 55785aaadf6SAnup Patel #define KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA (1 << 8) 55885aaadf6SAnup Patel 55985aaadf6SAnup Patel struct kvm_xen_hvm_config { 56085aaadf6SAnup Patel __u32 flags; 56185aaadf6SAnup Patel __u32 msr; 56285aaadf6SAnup Patel __u64 blob_addr_32; 56385aaadf6SAnup Patel __u64 blob_addr_64; 56485aaadf6SAnup Patel __u8 blob_size_32; 56585aaadf6SAnup Patel __u8 blob_size_64; 56685aaadf6SAnup Patel __u8 pad2[30]; 56785aaadf6SAnup Patel }; 56885aaadf6SAnup Patel 56985aaadf6SAnup Patel struct kvm_xen_hvm_attr { 57085aaadf6SAnup Patel __u16 type; 57185aaadf6SAnup Patel __u16 pad[3]; 57285aaadf6SAnup Patel union { 57385aaadf6SAnup Patel __u8 long_mode; 57485aaadf6SAnup Patel __u8 vector; 57585aaadf6SAnup Patel __u8 runstate_update_flag; 57685aaadf6SAnup Patel union { 57785aaadf6SAnup Patel __u64 gfn; 57885aaadf6SAnup Patel #define KVM_XEN_INVALID_GFN ((__u64)-1) 57985aaadf6SAnup Patel __u64 hva; 58085aaadf6SAnup Patel } shared_info; 58185aaadf6SAnup Patel struct { 58285aaadf6SAnup Patel __u32 send_port; 58385aaadf6SAnup Patel __u32 type; /* EVTCHNSTAT_ipi / EVTCHNSTAT_interdomain */ 58485aaadf6SAnup Patel __u32 flags; 58585aaadf6SAnup Patel #define KVM_XEN_EVTCHN_DEASSIGN (1 << 0) 58685aaadf6SAnup Patel #define KVM_XEN_EVTCHN_UPDATE (1 << 1) 58785aaadf6SAnup Patel #define KVM_XEN_EVTCHN_RESET (1 << 2) 58885aaadf6SAnup Patel /* 58985aaadf6SAnup Patel * Events sent by the guest are either looped back to 59085aaadf6SAnup Patel * the guest itself (potentially on a different port#) 59185aaadf6SAnup Patel * or signalled via an eventfd. 59285aaadf6SAnup Patel */ 59385aaadf6SAnup Patel union { 59485aaadf6SAnup Patel struct { 59585aaadf6SAnup Patel __u32 port; 59685aaadf6SAnup Patel __u32 vcpu; 59785aaadf6SAnup Patel __u32 priority; 59885aaadf6SAnup Patel } port; 59985aaadf6SAnup Patel struct { 60085aaadf6SAnup Patel __u32 port; /* Zero for eventfd */ 60185aaadf6SAnup Patel __s32 fd; 60285aaadf6SAnup Patel } eventfd; 60385aaadf6SAnup Patel __u32 padding[4]; 60485aaadf6SAnup Patel } deliver; 60585aaadf6SAnup Patel } evtchn; 60685aaadf6SAnup Patel __u32 xen_version; 60785aaadf6SAnup Patel __u64 pad[8]; 60885aaadf6SAnup Patel } u; 60985aaadf6SAnup Patel }; 61085aaadf6SAnup Patel 61185aaadf6SAnup Patel 61285aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO */ 61385aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_LONG_MODE 0x0 61485aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_SHARED_INFO 0x1 61585aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_UPCALL_VECTOR 0x2 61685aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */ 61785aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_EVTCHN 0x3 61885aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_XEN_VERSION 0x4 61985aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG */ 62085aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_RUNSTATE_UPDATE_FLAG 0x5 62185aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA */ 62285aaadf6SAnup Patel #define KVM_XEN_ATTR_TYPE_SHARED_INFO_HVA 0x6 62385aaadf6SAnup Patel 62485aaadf6SAnup Patel struct kvm_xen_vcpu_attr { 62585aaadf6SAnup Patel __u16 type; 62685aaadf6SAnup Patel __u16 pad[3]; 62785aaadf6SAnup Patel union { 62885aaadf6SAnup Patel __u64 gpa; 62985aaadf6SAnup Patel #define KVM_XEN_INVALID_GPA ((__u64)-1) 63085aaadf6SAnup Patel __u64 hva; 63185aaadf6SAnup Patel __u64 pad[8]; 63285aaadf6SAnup Patel struct { 63385aaadf6SAnup Patel __u64 state; 63485aaadf6SAnup Patel __u64 state_entry_time; 63585aaadf6SAnup Patel __u64 time_running; 63685aaadf6SAnup Patel __u64 time_runnable; 63785aaadf6SAnup Patel __u64 time_blocked; 63885aaadf6SAnup Patel __u64 time_offline; 63985aaadf6SAnup Patel } runstate; 64085aaadf6SAnup Patel __u32 vcpu_id; 64185aaadf6SAnup Patel struct { 64285aaadf6SAnup Patel __u32 port; 64385aaadf6SAnup Patel __u32 priority; 64485aaadf6SAnup Patel __u64 expires_ns; 64585aaadf6SAnup Patel } timer; 64685aaadf6SAnup Patel __u8 vector; 64785aaadf6SAnup Patel } u; 64885aaadf6SAnup Patel }; 64985aaadf6SAnup Patel 65085aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO */ 65185aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO 0x0 65285aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO 0x1 65385aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADDR 0x2 65485aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_CURRENT 0x3 65585aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_DATA 0x4 65685aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST 0x5 65785aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_EVTCHN_SEND */ 65885aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_ID 0x6 65985aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_TIMER 0x7 66085aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_UPCALL_VECTOR 0x8 66185aaadf6SAnup Patel /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA */ 66285aaadf6SAnup Patel #define KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA 0x9 66385aaadf6SAnup Patel 66485aaadf6SAnup Patel /* Secure Encrypted Virtualization command */ 66585aaadf6SAnup Patel enum sev_cmd_id { 66685aaadf6SAnup Patel /* Guest initialization commands */ 66785aaadf6SAnup Patel KVM_SEV_INIT = 0, 66885aaadf6SAnup Patel KVM_SEV_ES_INIT, 66985aaadf6SAnup Patel /* Guest launch commands */ 67085aaadf6SAnup Patel KVM_SEV_LAUNCH_START, 67185aaadf6SAnup Patel KVM_SEV_LAUNCH_UPDATE_DATA, 67285aaadf6SAnup Patel KVM_SEV_LAUNCH_UPDATE_VMSA, 67385aaadf6SAnup Patel KVM_SEV_LAUNCH_SECRET, 67485aaadf6SAnup Patel KVM_SEV_LAUNCH_MEASURE, 67585aaadf6SAnup Patel KVM_SEV_LAUNCH_FINISH, 67685aaadf6SAnup Patel /* Guest migration commands (outgoing) */ 67785aaadf6SAnup Patel KVM_SEV_SEND_START, 67885aaadf6SAnup Patel KVM_SEV_SEND_UPDATE_DATA, 67985aaadf6SAnup Patel KVM_SEV_SEND_UPDATE_VMSA, 68085aaadf6SAnup Patel KVM_SEV_SEND_FINISH, 68185aaadf6SAnup Patel /* Guest migration commands (incoming) */ 68285aaadf6SAnup Patel KVM_SEV_RECEIVE_START, 68385aaadf6SAnup Patel KVM_SEV_RECEIVE_UPDATE_DATA, 68485aaadf6SAnup Patel KVM_SEV_RECEIVE_UPDATE_VMSA, 68585aaadf6SAnup Patel KVM_SEV_RECEIVE_FINISH, 68685aaadf6SAnup Patel /* Guest status and debug commands */ 68785aaadf6SAnup Patel KVM_SEV_GUEST_STATUS, 68885aaadf6SAnup Patel KVM_SEV_DBG_DECRYPT, 68985aaadf6SAnup Patel KVM_SEV_DBG_ENCRYPT, 69085aaadf6SAnup Patel /* Guest certificates commands */ 69185aaadf6SAnup Patel KVM_SEV_CERT_EXPORT, 69285aaadf6SAnup Patel /* Attestation report */ 69385aaadf6SAnup Patel KVM_SEV_GET_ATTESTATION_REPORT, 69485aaadf6SAnup Patel /* Guest Migration Extension */ 69585aaadf6SAnup Patel KVM_SEV_SEND_CANCEL, 69685aaadf6SAnup Patel 697*01171537SAnup Patel /* Second time is the charm; improved versions of the above ioctls. */ 698*01171537SAnup Patel KVM_SEV_INIT2, 699*01171537SAnup Patel 70085aaadf6SAnup Patel KVM_SEV_NR_MAX, 70185aaadf6SAnup Patel }; 70285aaadf6SAnup Patel 70385aaadf6SAnup Patel struct kvm_sev_cmd { 70485aaadf6SAnup Patel __u32 id; 70585aaadf6SAnup Patel __u32 pad0; 70685aaadf6SAnup Patel __u64 data; 70785aaadf6SAnup Patel __u32 error; 70885aaadf6SAnup Patel __u32 sev_fd; 70985aaadf6SAnup Patel }; 71085aaadf6SAnup Patel 711*01171537SAnup Patel struct kvm_sev_init { 712*01171537SAnup Patel __u64 vmsa_features; 713*01171537SAnup Patel __u32 flags; 714*01171537SAnup Patel __u16 ghcb_version; 715*01171537SAnup Patel __u16 pad1; 716*01171537SAnup Patel __u32 pad2[8]; 717*01171537SAnup Patel }; 718*01171537SAnup Patel 71985aaadf6SAnup Patel struct kvm_sev_launch_start { 72085aaadf6SAnup Patel __u32 handle; 72185aaadf6SAnup Patel __u32 policy; 72285aaadf6SAnup Patel __u64 dh_uaddr; 72385aaadf6SAnup Patel __u32 dh_len; 72485aaadf6SAnup Patel __u32 pad0; 72585aaadf6SAnup Patel __u64 session_uaddr; 72685aaadf6SAnup Patel __u32 session_len; 72785aaadf6SAnup Patel __u32 pad1; 72885aaadf6SAnup Patel }; 72985aaadf6SAnup Patel 73085aaadf6SAnup Patel struct kvm_sev_launch_update_data { 73185aaadf6SAnup Patel __u64 uaddr; 73285aaadf6SAnup Patel __u32 len; 73385aaadf6SAnup Patel __u32 pad0; 73485aaadf6SAnup Patel }; 73585aaadf6SAnup Patel 73685aaadf6SAnup Patel 73785aaadf6SAnup Patel struct kvm_sev_launch_secret { 73885aaadf6SAnup Patel __u64 hdr_uaddr; 73985aaadf6SAnup Patel __u32 hdr_len; 74085aaadf6SAnup Patel __u32 pad0; 74185aaadf6SAnup Patel __u64 guest_uaddr; 74285aaadf6SAnup Patel __u32 guest_len; 74385aaadf6SAnup Patel __u32 pad1; 74485aaadf6SAnup Patel __u64 trans_uaddr; 74585aaadf6SAnup Patel __u32 trans_len; 74685aaadf6SAnup Patel __u32 pad2; 74785aaadf6SAnup Patel }; 74885aaadf6SAnup Patel 74985aaadf6SAnup Patel struct kvm_sev_launch_measure { 75085aaadf6SAnup Patel __u64 uaddr; 75185aaadf6SAnup Patel __u32 len; 75285aaadf6SAnup Patel __u32 pad0; 75385aaadf6SAnup Patel }; 75485aaadf6SAnup Patel 75585aaadf6SAnup Patel struct kvm_sev_guest_status { 75685aaadf6SAnup Patel __u32 handle; 75785aaadf6SAnup Patel __u32 policy; 75885aaadf6SAnup Patel __u32 state; 75985aaadf6SAnup Patel }; 76085aaadf6SAnup Patel 76185aaadf6SAnup Patel struct kvm_sev_dbg { 76285aaadf6SAnup Patel __u64 src_uaddr; 76385aaadf6SAnup Patel __u64 dst_uaddr; 76485aaadf6SAnup Patel __u32 len; 76585aaadf6SAnup Patel __u32 pad0; 76685aaadf6SAnup Patel }; 76785aaadf6SAnup Patel 76885aaadf6SAnup Patel struct kvm_sev_attestation_report { 76985aaadf6SAnup Patel __u8 mnonce[16]; 77085aaadf6SAnup Patel __u64 uaddr; 77185aaadf6SAnup Patel __u32 len; 77285aaadf6SAnup Patel __u32 pad0; 77385aaadf6SAnup Patel }; 77485aaadf6SAnup Patel 77585aaadf6SAnup Patel struct kvm_sev_send_start { 77685aaadf6SAnup Patel __u32 policy; 77785aaadf6SAnup Patel __u32 pad0; 77885aaadf6SAnup Patel __u64 pdh_cert_uaddr; 77985aaadf6SAnup Patel __u32 pdh_cert_len; 78085aaadf6SAnup Patel __u32 pad1; 78185aaadf6SAnup Patel __u64 plat_certs_uaddr; 78285aaadf6SAnup Patel __u32 plat_certs_len; 78385aaadf6SAnup Patel __u32 pad2; 78485aaadf6SAnup Patel __u64 amd_certs_uaddr; 78585aaadf6SAnup Patel __u32 amd_certs_len; 78685aaadf6SAnup Patel __u32 pad3; 78785aaadf6SAnup Patel __u64 session_uaddr; 78885aaadf6SAnup Patel __u32 session_len; 78985aaadf6SAnup Patel __u32 pad4; 79085aaadf6SAnup Patel }; 79185aaadf6SAnup Patel 79285aaadf6SAnup Patel struct kvm_sev_send_update_data { 79385aaadf6SAnup Patel __u64 hdr_uaddr; 79485aaadf6SAnup Patel __u32 hdr_len; 79585aaadf6SAnup Patel __u32 pad0; 79685aaadf6SAnup Patel __u64 guest_uaddr; 79785aaadf6SAnup Patel __u32 guest_len; 79885aaadf6SAnup Patel __u32 pad1; 79985aaadf6SAnup Patel __u64 trans_uaddr; 80085aaadf6SAnup Patel __u32 trans_len; 80185aaadf6SAnup Patel __u32 pad2; 80285aaadf6SAnup Patel }; 80385aaadf6SAnup Patel 80485aaadf6SAnup Patel struct kvm_sev_receive_start { 80585aaadf6SAnup Patel __u32 handle; 80685aaadf6SAnup Patel __u32 policy; 80785aaadf6SAnup Patel __u64 pdh_uaddr; 80885aaadf6SAnup Patel __u32 pdh_len; 80985aaadf6SAnup Patel __u32 pad0; 81085aaadf6SAnup Patel __u64 session_uaddr; 81185aaadf6SAnup Patel __u32 session_len; 81285aaadf6SAnup Patel __u32 pad1; 81385aaadf6SAnup Patel }; 81485aaadf6SAnup Patel 81585aaadf6SAnup Patel struct kvm_sev_receive_update_data { 81685aaadf6SAnup Patel __u64 hdr_uaddr; 81785aaadf6SAnup Patel __u32 hdr_len; 81885aaadf6SAnup Patel __u32 pad0; 81985aaadf6SAnup Patel __u64 guest_uaddr; 82085aaadf6SAnup Patel __u32 guest_len; 82185aaadf6SAnup Patel __u32 pad1; 82285aaadf6SAnup Patel __u64 trans_uaddr; 82385aaadf6SAnup Patel __u32 trans_len; 82485aaadf6SAnup Patel __u32 pad2; 82585aaadf6SAnup Patel }; 82685aaadf6SAnup Patel 82785aaadf6SAnup Patel #define KVM_X2APIC_API_USE_32BIT_IDS (1ULL << 0) 82885aaadf6SAnup Patel #define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK (1ULL << 1) 82985aaadf6SAnup Patel 83085aaadf6SAnup Patel struct kvm_hyperv_eventfd { 83185aaadf6SAnup Patel __u32 conn_id; 83285aaadf6SAnup Patel __s32 fd; 83385aaadf6SAnup Patel __u32 flags; 83485aaadf6SAnup Patel __u32 padding[3]; 83585aaadf6SAnup Patel }; 83685aaadf6SAnup Patel 83785aaadf6SAnup Patel #define KVM_HYPERV_CONN_ID_MASK 0x00ffffff 83885aaadf6SAnup Patel #define KVM_HYPERV_EVENTFD_DEASSIGN (1 << 0) 83985aaadf6SAnup Patel 840be986824SAnup Patel /* 841be986824SAnup Patel * Masked event layout. 842be986824SAnup Patel * Bits Description 843be986824SAnup Patel * ---- ----------- 844be986824SAnup Patel * 7:0 event select (low bits) 845be986824SAnup Patel * 15:8 umask match 846be986824SAnup Patel * 31:16 unused 847be986824SAnup Patel * 35:32 event select (high bits) 848be986824SAnup Patel * 36:54 unused 849be986824SAnup Patel * 55 exclude bit 850be986824SAnup Patel * 63:56 umask mask 851be986824SAnup Patel */ 852be986824SAnup Patel 853be986824SAnup Patel #define KVM_PMU_ENCODE_MASKED_ENTRY(event_select, mask, match, exclude) \ 854be986824SAnup Patel (((event_select) & 0xFFULL) | (((event_select) & 0XF00ULL) << 24) | \ 855be986824SAnup Patel (((mask) & 0xFFULL) << 56) | \ 856be986824SAnup Patel (((match) & 0xFFULL) << 8) | \ 857be986824SAnup Patel ((__u64)(!!(exclude)) << 55)) 858be986824SAnup Patel 859be986824SAnup Patel #define KVM_PMU_MASKED_ENTRY_EVENT_SELECT \ 86085aaadf6SAnup Patel (__GENMASK_ULL(7, 0) | __GENMASK_ULL(35, 32)) 86185aaadf6SAnup Patel #define KVM_PMU_MASKED_ENTRY_UMASK_MASK (__GENMASK_ULL(63, 56)) 86285aaadf6SAnup Patel #define KVM_PMU_MASKED_ENTRY_UMASK_MATCH (__GENMASK_ULL(15, 8)) 86385aaadf6SAnup Patel #define KVM_PMU_MASKED_ENTRY_EXCLUDE (_BITULL(55)) 864be986824SAnup Patel #define KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT (56) 865be986824SAnup Patel 8665968b5ffSAnup Patel /* for KVM_{GET,SET,HAS}_DEVICE_ATTR */ 8675968b5ffSAnup Patel #define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */ 8685968b5ffSAnup Patel #define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */ 8695968b5ffSAnup Patel 870be986824SAnup Patel /* x86-specific KVM_EXIT_HYPERCALL flags. */ 87185aaadf6SAnup Patel #define KVM_EXIT_HYPERCALL_LONG_MODE _BITULL(0) 872be986824SAnup Patel 87399684681SAnup Patel #define KVM_X86_DEFAULT_VM 0 87499684681SAnup Patel #define KVM_X86_SW_PROTECTED_VM 1 875*01171537SAnup Patel #define KVM_X86_SEV_VM 2 876*01171537SAnup Patel #define KVM_X86_SEV_ES_VM 3 87799684681SAnup Patel 87860021220SAndre Przywara #endif /* _ASM_X86_KVM_H */ 879