1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/kvm-cpu.h" 6 #include "kvm/virtio-pci-dev.h" 7 #include "kvm/irq.h" 8 #include "kvm/virtio.h" 9 #include "kvm/ioeventfd.h" 10 #include "kvm/util.h" 11 12 #include <sys/ioctl.h> 13 #include <linux/virtio_pci.h> 14 #include <linux/byteorder.h> 15 #include <assert.h> 16 #include <string.h> 17 18 #define ALIGN_UP(x, s) ALIGN((x) + (s) - 1, (s)) 19 #define VIRTIO_NR_MSIX (VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG) 20 #define VIRTIO_MSIX_TABLE_SIZE (VIRTIO_NR_MSIX * 16) 21 #define VIRTIO_MSIX_PBA_SIZE (ALIGN_UP(VIRTIO_MSIX_TABLE_SIZE, 64) / 8) 22 #define VIRTIO_MSIX_BAR_SIZE (1UL << fls_long(VIRTIO_MSIX_TABLE_SIZE + \ 23 VIRTIO_MSIX_PBA_SIZE)) 24 25 static u16 virtio_pci__port_addr(struct virtio_pci *vpci) 26 { 27 return pci__bar_address(&vpci->pci_hdr, 0); 28 } 29 30 static u32 virtio_pci__mmio_addr(struct virtio_pci *vpci) 31 { 32 return pci__bar_address(&vpci->pci_hdr, 1); 33 } 34 35 static u32 virtio_pci__msix_io_addr(struct virtio_pci *vpci) 36 { 37 return pci__bar_address(&vpci->pci_hdr, 2); 38 } 39 40 static int virtio_pci__add_msix_route(struct virtio_pci *vpci, u32 vec) 41 { 42 int gsi; 43 struct msi_msg *msg; 44 45 if (vec == VIRTIO_MSI_NO_VECTOR) 46 return -EINVAL; 47 48 msg = &vpci->msix_table[vec].msg; 49 gsi = irq__add_msix_route(vpci->kvm, msg, vpci->dev_hdr.dev_num << 3); 50 /* 51 * We don't need IRQ routing if we can use 52 * MSI injection via the KVM_SIGNAL_MSI ioctl. 53 */ 54 if (gsi == -ENXIO && vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 55 return gsi; 56 57 if (gsi < 0) 58 die("failed to configure MSIs"); 59 60 return gsi; 61 } 62 63 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 64 { 65 struct virtio_pci_ioevent_param *ioeventfd = param; 66 struct virtio_pci *vpci = ioeventfd->vdev->virtio; 67 68 ioeventfd->vdev->ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 69 } 70 71 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 72 { 73 struct ioevent ioevent; 74 struct virtio_pci *vpci = vdev->virtio; 75 u32 mmio_addr = virtio_pci__mmio_addr(vpci); 76 u16 port_addr = virtio_pci__port_addr(vpci); 77 int r, flags = 0; 78 int fd; 79 80 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 81 .vdev = vdev, 82 .vq = vq, 83 }; 84 85 ioevent = (struct ioevent) { 86 .fn = virtio_pci__ioevent_callback, 87 .fn_ptr = &vpci->ioeventfds[vq], 88 .datamatch = vq, 89 .fn_kvm = kvm, 90 }; 91 92 /* 93 * Vhost will poll the eventfd in host kernel side, otherwise we 94 * need to poll in userspace. 95 */ 96 if (!vdev->use_vhost) 97 flags |= IOEVENTFD_FLAG_USER_POLL; 98 99 /* ioport */ 100 ioevent.io_addr = port_addr + VIRTIO_PCI_QUEUE_NOTIFY; 101 ioevent.io_len = sizeof(u16); 102 ioevent.fd = fd = eventfd(0, 0); 103 r = ioeventfd__add_event(&ioevent, flags | IOEVENTFD_FLAG_PIO); 104 if (r) 105 return r; 106 107 /* mmio */ 108 ioevent.io_addr = mmio_addr + VIRTIO_PCI_QUEUE_NOTIFY; 109 ioevent.io_len = sizeof(u16); 110 ioevent.fd = eventfd(0, 0); 111 r = ioeventfd__add_event(&ioevent, flags); 112 if (r) 113 goto free_ioport_evt; 114 115 if (vdev->ops->notify_vq_eventfd) 116 vdev->ops->notify_vq_eventfd(kvm, vpci->dev, vq, fd); 117 return 0; 118 119 free_ioport_evt: 120 ioeventfd__del_event(port_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 121 return r; 122 } 123 124 static void virtio_pci_exit_vq(struct kvm *kvm, struct virtio_device *vdev, 125 int vq) 126 { 127 struct virtio_pci *vpci = vdev->virtio; 128 u32 mmio_addr = virtio_pci__mmio_addr(vpci); 129 u16 port_addr = virtio_pci__port_addr(vpci); 130 131 ioeventfd__del_event(mmio_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 132 ioeventfd__del_event(port_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 133 virtio_exit_vq(kvm, vdev, vpci->dev, vq); 134 } 135 136 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 137 { 138 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 139 } 140 141 static bool virtio_pci__specific_data_in(struct kvm *kvm, struct virtio_device *vdev, 142 void *data, u32 size, unsigned long offset) 143 { 144 u32 config_offset; 145 struct virtio_pci *vpci = vdev->virtio; 146 int type = virtio__get_dev_specific_field(offset - 20, 147 virtio_pci__msix_enabled(vpci), 148 &config_offset); 149 if (type == VIRTIO_PCI_O_MSIX) { 150 switch (offset) { 151 case VIRTIO_MSI_CONFIG_VECTOR: 152 ioport__write16(data, vpci->config_vector); 153 break; 154 case VIRTIO_MSI_QUEUE_VECTOR: 155 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 156 break; 157 }; 158 159 return true; 160 } else if (type == VIRTIO_PCI_O_CONFIG) { 161 return virtio_access_config(kvm, vdev, vpci->dev, config_offset, 162 data, size, false); 163 } 164 165 return false; 166 } 167 168 static bool virtio_pci__data_in(struct kvm_cpu *vcpu, struct virtio_device *vdev, 169 unsigned long offset, void *data, u32 size) 170 { 171 bool ret = true; 172 struct virtio_pci *vpci; 173 struct virt_queue *vq; 174 struct kvm *kvm; 175 u32 val; 176 177 kvm = vcpu->kvm; 178 vpci = vdev->virtio; 179 180 switch (offset) { 181 case VIRTIO_PCI_HOST_FEATURES: 182 val = vdev->ops->get_host_features(kvm, vpci->dev); 183 ioport__write32(data, val); 184 break; 185 case VIRTIO_PCI_QUEUE_PFN: 186 vq = vdev->ops->get_vq(kvm, vpci->dev, vpci->queue_selector); 187 ioport__write32(data, vq->vring_addr.pfn); 188 break; 189 case VIRTIO_PCI_QUEUE_NUM: 190 val = vdev->ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 191 ioport__write16(data, val); 192 break; 193 case VIRTIO_PCI_STATUS: 194 ioport__write8(data, vpci->status); 195 break; 196 case VIRTIO_PCI_ISR: 197 ioport__write8(data, vpci->isr); 198 kvm__irq_line(kvm, vpci->legacy_irq_line, VIRTIO_IRQ_LOW); 199 vpci->isr = VIRTIO_IRQ_LOW; 200 break; 201 default: 202 ret = virtio_pci__specific_data_in(kvm, vdev, data, size, offset); 203 break; 204 }; 205 206 return ret; 207 } 208 209 static void update_msix_map(struct virtio_pci *vpci, 210 struct msix_table *msix_entry, u32 vecnum) 211 { 212 u32 gsi, i; 213 214 /* Find the GSI number used for that vector */ 215 if (vecnum == vpci->config_vector) { 216 gsi = vpci->config_gsi; 217 } else { 218 for (i = 0; i < VIRTIO_PCI_MAX_VQ; i++) 219 if (vpci->vq_vector[i] == vecnum) 220 break; 221 if (i == VIRTIO_PCI_MAX_VQ) 222 return; 223 gsi = vpci->gsis[i]; 224 } 225 226 if (gsi == 0) 227 return; 228 229 msix_entry = &msix_entry[vecnum]; 230 irq__update_msix_route(vpci->kvm, gsi, &msix_entry->msg); 231 } 232 233 static bool virtio_pci__specific_data_out(struct kvm *kvm, struct virtio_device *vdev, 234 void *data, u32 size, unsigned long offset) 235 { 236 struct virtio_pci *vpci = vdev->virtio; 237 u32 config_offset, vec; 238 int gsi; 239 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 240 &config_offset); 241 if (type == VIRTIO_PCI_O_MSIX) { 242 switch (offset) { 243 case VIRTIO_MSI_CONFIG_VECTOR: 244 vec = vpci->config_vector = ioport__read16(data); 245 246 gsi = virtio_pci__add_msix_route(vpci, vec); 247 if (gsi < 0) 248 break; 249 250 vpci->config_gsi = gsi; 251 break; 252 case VIRTIO_MSI_QUEUE_VECTOR: 253 vec = ioport__read16(data); 254 vpci->vq_vector[vpci->queue_selector] = vec; 255 256 gsi = virtio_pci__add_msix_route(vpci, vec); 257 if (gsi < 0) 258 break; 259 260 vpci->gsis[vpci->queue_selector] = gsi; 261 if (vdev->ops->notify_vq_gsi) 262 vdev->ops->notify_vq_gsi(kvm, vpci->dev, 263 vpci->queue_selector, 264 gsi); 265 break; 266 }; 267 268 return true; 269 } else if (type == VIRTIO_PCI_O_CONFIG) { 270 return virtio_access_config(kvm, vdev, vpci->dev, config_offset, 271 data, size, true); 272 } 273 274 return false; 275 } 276 277 static bool virtio_pci__data_out(struct kvm_cpu *vcpu, struct virtio_device *vdev, 278 unsigned long offset, void *data, u32 size) 279 { 280 bool ret = true; 281 struct virtio_pci *vpci; 282 struct virt_queue *vq; 283 struct kvm *kvm; 284 u32 val; 285 unsigned int vq_count; 286 287 kvm = vcpu->kvm; 288 vpci = vdev->virtio; 289 vq_count = vdev->ops->get_vq_count(kvm, vpci->dev); 290 291 switch (offset) { 292 case VIRTIO_PCI_GUEST_FEATURES: 293 val = ioport__read32(data); 294 virtio_set_guest_features(kvm, vdev, vpci->dev, val); 295 break; 296 case VIRTIO_PCI_QUEUE_PFN: 297 val = ioport__read32(data); 298 if (val) { 299 vq = vdev->ops->get_vq(kvm, vpci->dev, 300 vpci->queue_selector); 301 vq->vring_addr = (struct vring_addr) { 302 .legacy = true, 303 .pfn = val, 304 .align = VIRTIO_PCI_VRING_ALIGN, 305 .pgsize = 1 << VIRTIO_PCI_QUEUE_ADDR_SHIFT, 306 }; 307 virtio_pci__init_ioeventfd(kvm, vdev, 308 vpci->queue_selector); 309 vdev->ops->init_vq(kvm, vpci->dev, 310 vpci->queue_selector); 311 } else { 312 virtio_pci_exit_vq(kvm, vdev, vpci->queue_selector); 313 } 314 break; 315 case VIRTIO_PCI_QUEUE_SEL: 316 val = ioport__read16(data); 317 if (val >= vq_count) { 318 WARN_ONCE(1, "QUEUE_SEL value (%u) is larger than VQ count (%u)\n", 319 val, vq_count); 320 return false; 321 } 322 vpci->queue_selector = val; 323 break; 324 case VIRTIO_PCI_QUEUE_NOTIFY: 325 val = ioport__read16(data); 326 if (val >= vq_count) { 327 WARN_ONCE(1, "QUEUE_SEL value (%u) is larger than VQ count (%u)\n", 328 val, vq_count); 329 return false; 330 } 331 vdev->ops->notify_vq(kvm, vpci->dev, val); 332 break; 333 case VIRTIO_PCI_STATUS: 334 vpci->status = ioport__read8(data); 335 if (!vpci->status) /* Sample endianness on reset */ 336 vdev->endian = kvm_cpu__get_endianness(vcpu); 337 virtio_notify_status(kvm, vdev, vpci->dev, vpci->status); 338 break; 339 default: 340 ret = virtio_pci__specific_data_out(kvm, vdev, data, size, offset); 341 break; 342 }; 343 344 return ret; 345 } 346 347 static void virtio_pci__msix_mmio_callback(struct kvm_cpu *vcpu, 348 u64 addr, u8 *data, u32 len, 349 u8 is_write, void *ptr) 350 { 351 struct virtio_device *vdev = ptr; 352 struct virtio_pci *vpci = vdev->virtio; 353 struct msix_table *table; 354 u32 msix_io_addr = virtio_pci__msix_io_addr(vpci); 355 u32 pba_offset; 356 int vecnum; 357 size_t offset; 358 359 BUILD_BUG_ON(VIRTIO_NR_MSIX > (sizeof(vpci->msix_pba) * 8)); 360 361 pba_offset = vpci->pci_hdr.msix.pba_offset & ~PCI_MSIX_TABLE_BIR; 362 if (addr >= msix_io_addr + pba_offset) { 363 /* Read access to PBA */ 364 if (is_write) 365 return; 366 offset = addr - (msix_io_addr + pba_offset); 367 if ((offset + len) > sizeof (vpci->msix_pba)) 368 return; 369 memcpy(data, (void *)&vpci->msix_pba + offset, len); 370 return; 371 } 372 373 table = vpci->msix_table; 374 offset = addr - msix_io_addr; 375 376 vecnum = offset / sizeof(struct msix_table); 377 offset = offset % sizeof(struct msix_table); 378 379 if (!is_write) { 380 memcpy(data, (void *)&table[vecnum] + offset, len); 381 return; 382 } 383 384 memcpy((void *)&table[vecnum] + offset, data, len); 385 386 /* Did we just update the address or payload? */ 387 if (offset < offsetof(struct msix_table, ctrl)) 388 update_msix_map(vpci, table, vecnum); 389 } 390 391 static void virtio_pci__signal_msi(struct kvm *kvm, struct virtio_pci *vpci, 392 int vec) 393 { 394 struct kvm_msi msi = { 395 .address_lo = vpci->msix_table[vec].msg.address_lo, 396 .address_hi = vpci->msix_table[vec].msg.address_hi, 397 .data = vpci->msix_table[vec].msg.data, 398 }; 399 400 if (kvm->msix_needs_devid) { 401 msi.flags = KVM_MSI_VALID_DEVID; 402 msi.devid = vpci->dev_hdr.dev_num << 3; 403 } 404 405 irq__signal_msi(kvm, &msi); 406 } 407 408 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 409 { 410 struct virtio_pci *vpci = vdev->virtio; 411 int tbl = vpci->vq_vector[vq]; 412 413 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 414 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 415 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 416 417 vpci->msix_pba |= 1 << tbl; 418 return 0; 419 } 420 421 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 422 virtio_pci__signal_msi(kvm, vpci, vpci->vq_vector[vq]); 423 else 424 kvm__irq_trigger(kvm, vpci->gsis[vq]); 425 } else { 426 vpci->isr = VIRTIO_IRQ_HIGH; 427 kvm__irq_line(kvm, vpci->legacy_irq_line, VIRTIO_IRQ_HIGH); 428 } 429 return 0; 430 } 431 432 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_device *vdev) 433 { 434 struct virtio_pci *vpci = vdev->virtio; 435 int tbl = vpci->config_vector; 436 437 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 438 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 439 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 440 441 vpci->msix_pba |= 1 << tbl; 442 return 0; 443 } 444 445 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 446 virtio_pci__signal_msi(kvm, vpci, tbl); 447 else 448 kvm__irq_trigger(kvm, vpci->config_gsi); 449 } else { 450 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 451 kvm__irq_trigger(kvm, vpci->legacy_irq_line); 452 } 453 454 return 0; 455 } 456 457 static void virtio_pci__io_mmio_callback(struct kvm_cpu *vcpu, 458 u64 addr, u8 *data, u32 len, 459 u8 is_write, void *ptr) 460 { 461 struct virtio_device *vdev = ptr; 462 struct virtio_pci *vpci = vdev->virtio; 463 u32 ioport_addr = virtio_pci__port_addr(vpci); 464 u32 base_addr; 465 466 if (addr >= ioport_addr && 467 addr < ioport_addr + pci__bar_size(&vpci->pci_hdr, 0)) 468 base_addr = ioport_addr; 469 else 470 base_addr = virtio_pci__mmio_addr(vpci); 471 472 if (!is_write) 473 virtio_pci__data_in(vcpu, vdev, addr - base_addr, data, len); 474 else 475 virtio_pci__data_out(vcpu, vdev, addr - base_addr, data, len); 476 } 477 478 static int virtio_pci__bar_activate(struct kvm *kvm, 479 struct pci_device_header *pci_hdr, 480 int bar_num, void *data) 481 { 482 struct virtio_device *vdev = data; 483 u32 bar_addr, bar_size; 484 int r = -EINVAL; 485 486 assert(bar_num <= 2); 487 488 bar_addr = pci__bar_address(pci_hdr, bar_num); 489 bar_size = pci__bar_size(pci_hdr, bar_num); 490 491 switch (bar_num) { 492 case 0: 493 r = kvm__register_pio(kvm, bar_addr, bar_size, 494 virtio_pci__io_mmio_callback, vdev); 495 break; 496 case 1: 497 r = kvm__register_mmio(kvm, bar_addr, bar_size, false, 498 virtio_pci__io_mmio_callback, vdev); 499 break; 500 case 2: 501 r = kvm__register_mmio(kvm, bar_addr, bar_size, false, 502 virtio_pci__msix_mmio_callback, vdev); 503 break; 504 } 505 506 return r; 507 } 508 509 static int virtio_pci__bar_deactivate(struct kvm *kvm, 510 struct pci_device_header *pci_hdr, 511 int bar_num, void *data) 512 { 513 u32 bar_addr; 514 bool success; 515 int r = -EINVAL; 516 517 assert(bar_num <= 2); 518 519 bar_addr = pci__bar_address(pci_hdr, bar_num); 520 521 switch (bar_num) { 522 case 0: 523 r = kvm__deregister_pio(kvm, bar_addr); 524 break; 525 case 1: 526 case 2: 527 success = kvm__deregister_mmio(kvm, bar_addr); 528 /* kvm__deregister_mmio fails when the region is not found. */ 529 r = (success ? 0 : -ENOENT); 530 break; 531 } 532 533 return r; 534 } 535 536 int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev, 537 int device_id, int subsys_id, int class) 538 { 539 struct virtio_pci *vpci = vdev->virtio; 540 u32 mmio_addr, msix_io_block; 541 u16 port_addr; 542 int r; 543 544 vpci->kvm = kvm; 545 vpci->dev = dev; 546 547 BUILD_BUG_ON(!is_power_of_two(PCI_IO_SIZE)); 548 549 port_addr = pci_get_io_port_block(PCI_IO_SIZE); 550 mmio_addr = pci_get_mmio_block(PCI_IO_SIZE); 551 msix_io_block = pci_get_mmio_block(VIRTIO_MSIX_BAR_SIZE); 552 553 vpci->pci_hdr = (struct pci_device_header) { 554 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 555 .device_id = cpu_to_le16(device_id), 556 .command = PCI_COMMAND_IO | PCI_COMMAND_MEMORY, 557 .header_type = PCI_HEADER_TYPE_NORMAL, 558 .revision_id = 0, 559 .class[0] = class & 0xff, 560 .class[1] = (class >> 8) & 0xff, 561 .class[2] = (class >> 16) & 0xff, 562 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 563 .subsys_id = cpu_to_le16(subsys_id), 564 .bar[0] = cpu_to_le32(port_addr 565 | PCI_BASE_ADDRESS_SPACE_IO), 566 .bar[1] = cpu_to_le32(mmio_addr 567 | PCI_BASE_ADDRESS_SPACE_MEMORY), 568 .bar[2] = cpu_to_le32(msix_io_block 569 | PCI_BASE_ADDRESS_SPACE_MEMORY), 570 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 571 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 572 .bar_size[0] = cpu_to_le32(PCI_IO_SIZE), 573 .bar_size[1] = cpu_to_le32(PCI_IO_SIZE), 574 .bar_size[2] = cpu_to_le32(VIRTIO_MSIX_BAR_SIZE), 575 }; 576 577 r = pci__register_bar_regions(kvm, &vpci->pci_hdr, 578 virtio_pci__bar_activate, 579 virtio_pci__bar_deactivate, vdev); 580 if (r < 0) 581 return r; 582 583 vpci->dev_hdr = (struct device_header) { 584 .bus_type = DEVICE_BUS_PCI, 585 .data = &vpci->pci_hdr, 586 }; 587 588 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 589 vpci->pci_hdr.msix.next = 0; 590 /* 591 * We at most have VIRTIO_NR_MSIX entries (VIRTIO_PCI_MAX_VQ 592 * entries for virt queue, VIRTIO_PCI_MAX_CONFIG entries for 593 * config). 594 * 595 * To quote the PCI spec: 596 * 597 * System software reads this field to determine the 598 * MSI-X Table Size N, which is encoded as N-1. 599 * For example, a returned value of "00000000011" 600 * indicates a table size of 4. 601 */ 602 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_NR_MSIX - 1); 603 604 /* Both table and PBA are mapped to the same BAR (2) */ 605 vpci->pci_hdr.msix.table_offset = cpu_to_le32(2); 606 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(2 | VIRTIO_MSIX_TABLE_SIZE); 607 vpci->config_vector = 0; 608 609 if (irq__can_signal_msi(kvm)) 610 vpci->features |= VIRTIO_PCI_F_SIGNAL_MSI; 611 612 vpci->legacy_irq_line = pci__assign_irq(&vpci->pci_hdr); 613 614 r = device__register(&vpci->dev_hdr); 615 if (r < 0) 616 return r; 617 618 return 0; 619 } 620 621 int virtio_pci__reset(struct kvm *kvm, struct virtio_device *vdev) 622 { 623 unsigned int vq; 624 struct virtio_pci *vpci = vdev->virtio; 625 626 for (vq = 0; vq < vdev->ops->get_vq_count(kvm, vpci->dev); vq++) 627 virtio_pci_exit_vq(kvm, vdev, vq); 628 629 return 0; 630 } 631 632 int virtio_pci__exit(struct kvm *kvm, struct virtio_device *vdev) 633 { 634 struct virtio_pci *vpci = vdev->virtio; 635 636 virtio_pci__reset(kvm, vdev); 637 kvm__deregister_mmio(kvm, virtio_pci__mmio_addr(vpci)); 638 kvm__deregister_mmio(kvm, virtio_pci__msix_io_addr(vpci)); 639 kvm__deregister_pio(kvm, virtio_pci__port_addr(vpci)); 640 641 return 0; 642 } 643