1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/virtio-pci-dev.h" 6 #include "kvm/irq.h" 7 #include "kvm/virtio.h" 8 #include "kvm/ioeventfd.h" 9 #include "kvm/virtio-trans.h" 10 11 #include <linux/virtio_pci.h> 12 #include <linux/byteorder.h> 13 #include <string.h> 14 15 struct virtio_trans_ops *virtio_pci__get_trans_ops(void) 16 { 17 static struct virtio_trans_ops virtio_pci_trans = (struct virtio_trans_ops) { 18 .signal_vq = virtio_pci__signal_vq, 19 .signal_config = virtio_pci__signal_config, 20 .init = virtio_pci__init, 21 }; 22 return &virtio_pci_trans; 23 }; 24 25 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 26 { 27 struct virtio_pci_ioevent_param *ioeventfd = param; 28 struct virtio_pci *vpci = ioeventfd->vtrans->virtio; 29 30 ioeventfd->vtrans->virtio_ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 31 } 32 33 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_trans *vtrans, u32 vq) 34 { 35 struct ioevent ioevent; 36 struct virtio_pci *vpci = vtrans->virtio; 37 int r; 38 39 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 40 .vtrans = vtrans, 41 .vq = vq, 42 }; 43 44 ioevent = (struct ioevent) { 45 .io_addr = vpci->base_addr + VIRTIO_PCI_QUEUE_NOTIFY, 46 .io_len = sizeof(u16), 47 .fn = virtio_pci__ioevent_callback, 48 .fn_ptr = &vpci->ioeventfds[vq], 49 .datamatch = vq, 50 .fn_kvm = kvm, 51 .fd = eventfd(0, 0), 52 }; 53 54 r = ioeventfd__add_event(&ioevent); 55 if (r) 56 return r; 57 58 if (vtrans->virtio_ops->notify_vq_eventfd) 59 vtrans->virtio_ops->notify_vq_eventfd(kvm, vpci->dev, vq, ioevent.fd); 60 61 return 0; 62 } 63 64 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 65 { 66 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 67 } 68 69 static bool virtio_pci__specific_io_in(struct kvm *kvm, struct virtio_trans *vtrans, u16 port, 70 void *data, int size, int offset) 71 { 72 u32 config_offset; 73 struct virtio_pci *vpci = vtrans->virtio; 74 int type = virtio__get_dev_specific_field(offset - 20, 75 virtio_pci__msix_enabled(vpci), 76 &config_offset); 77 if (type == VIRTIO_PCI_O_MSIX) { 78 switch (offset) { 79 case VIRTIO_MSI_CONFIG_VECTOR: 80 ioport__write16(data, vpci->config_vector); 81 break; 82 case VIRTIO_MSI_QUEUE_VECTOR: 83 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 84 break; 85 }; 86 87 return true; 88 } else if (type == VIRTIO_PCI_O_CONFIG) { 89 u8 cfg; 90 91 cfg = vtrans->virtio_ops->get_config(kvm, vpci->dev, config_offset); 92 ioport__write8(data, cfg); 93 return true; 94 } 95 96 return false; 97 } 98 99 static bool virtio_pci__io_in(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 100 { 101 unsigned long offset; 102 bool ret = true; 103 struct virtio_trans *vtrans; 104 struct virtio_pci *vpci; 105 u32 val; 106 107 vtrans = ioport->priv; 108 vpci = vtrans->virtio; 109 offset = port - vpci->base_addr; 110 111 switch (offset) { 112 case VIRTIO_PCI_HOST_FEATURES: 113 val = vtrans->virtio_ops->get_host_features(kvm, vpci->dev); 114 ioport__write32(data, val); 115 break; 116 case VIRTIO_PCI_QUEUE_PFN: 117 val = vtrans->virtio_ops->get_pfn_vq(kvm, vpci->dev, vpci->queue_selector); 118 ioport__write32(data, val); 119 break; 120 case VIRTIO_PCI_QUEUE_NUM: 121 val = vtrans->virtio_ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 122 ioport__write16(data, val); 123 break; 124 case VIRTIO_PCI_STATUS: 125 ioport__write8(data, vpci->status); 126 break; 127 case VIRTIO_PCI_ISR: 128 ioport__write8(data, vpci->isr); 129 kvm__irq_line(kvm, vpci->pci_hdr.irq_line, VIRTIO_IRQ_LOW); 130 vpci->isr = VIRTIO_IRQ_LOW; 131 break; 132 default: 133 ret = virtio_pci__specific_io_in(kvm, vtrans, port, data, size, offset); 134 break; 135 }; 136 137 return ret; 138 } 139 140 static bool virtio_pci__specific_io_out(struct kvm *kvm, struct virtio_trans *vtrans, u16 port, 141 void *data, int size, int offset) 142 { 143 struct virtio_pci *vpci = vtrans->virtio; 144 u32 config_offset, gsi, vec; 145 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 146 &config_offset); 147 if (type == VIRTIO_PCI_O_MSIX) { 148 switch (offset) { 149 case VIRTIO_MSI_CONFIG_VECTOR: 150 vec = vpci->config_vector = ioport__read16(data); 151 152 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 153 154 vpci->config_gsi = gsi; 155 break; 156 case VIRTIO_MSI_QUEUE_VECTOR: 157 vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); 158 159 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 160 vpci->gsis[vpci->queue_selector] = gsi; 161 if (vtrans->virtio_ops->notify_vq_gsi) 162 vtrans->virtio_ops->notify_vq_gsi(kvm, vpci->dev, 163 vpci->queue_selector, gsi); 164 break; 165 }; 166 167 return true; 168 } else if (type == VIRTIO_PCI_O_CONFIG) { 169 vtrans->virtio_ops->set_config(kvm, vpci->dev, *(u8 *)data, config_offset); 170 171 return true; 172 } 173 174 return false; 175 } 176 177 static bool virtio_pci__io_out(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 178 { 179 unsigned long offset; 180 bool ret = true; 181 struct virtio_trans *vtrans; 182 struct virtio_pci *vpci; 183 u32 val; 184 185 vtrans = ioport->priv; 186 vpci = vtrans->virtio; 187 offset = port - vpci->base_addr; 188 189 switch (offset) { 190 case VIRTIO_PCI_GUEST_FEATURES: 191 val = ioport__read32(data); 192 vtrans->virtio_ops->set_guest_features(kvm, vpci->dev, val); 193 break; 194 case VIRTIO_PCI_QUEUE_PFN: 195 val = ioport__read32(data); 196 virtio_pci__init_ioeventfd(kvm, vtrans, vpci->queue_selector); 197 vtrans->virtio_ops->init_vq(kvm, vpci->dev, vpci->queue_selector, val); 198 break; 199 case VIRTIO_PCI_QUEUE_SEL: 200 vpci->queue_selector = ioport__read16(data); 201 break; 202 case VIRTIO_PCI_QUEUE_NOTIFY: 203 val = ioport__read16(data); 204 vtrans->virtio_ops->notify_vq(kvm, vpci->dev, val); 205 break; 206 case VIRTIO_PCI_STATUS: 207 vpci->status = ioport__read8(data); 208 break; 209 default: 210 ret = virtio_pci__specific_io_out(kvm, vtrans, port, data, size, offset); 211 break; 212 }; 213 214 return ret; 215 } 216 217 static struct ioport_operations virtio_pci__io_ops = { 218 .io_in = virtio_pci__io_in, 219 .io_out = virtio_pci__io_out, 220 }; 221 222 static void callback_mmio_table(u64 addr, u8 *data, u32 len, u8 is_write, void *ptr) 223 { 224 struct virtio_pci *vpci = ptr; 225 void *table; 226 u32 offset; 227 228 if (addr > vpci->msix_io_block + PCI_IO_SIZE) { 229 table = &vpci->msix_pba; 230 offset = vpci->msix_io_block + PCI_IO_SIZE; 231 } else { 232 table = &vpci->msix_table; 233 offset = vpci->msix_io_block; 234 } 235 236 if (is_write) 237 memcpy(table + addr - offset, data, len); 238 else 239 memcpy(data, table + addr - offset, len); 240 } 241 242 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_trans *vtrans, u32 vq) 243 { 244 struct virtio_pci *vpci = vtrans->virtio; 245 int tbl = vpci->vq_vector[vq]; 246 247 if (virtio_pci__msix_enabled(vpci)) { 248 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 249 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 250 251 vpci->msix_pba |= 1 << tbl; 252 return 0; 253 } 254 255 kvm__irq_trigger(kvm, vpci->gsis[vq]); 256 } else { 257 vpci->isr = VIRTIO_IRQ_HIGH; 258 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 259 } 260 return 0; 261 } 262 263 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_trans *vtrans) 264 { 265 struct virtio_pci *vpci = vtrans->virtio; 266 int tbl = vpci->config_vector; 267 268 if (virtio_pci__msix_enabled(vpci)) { 269 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 270 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 271 272 vpci->msix_pba |= 1 << tbl; 273 return 0; 274 } 275 276 kvm__irq_trigger(kvm, vpci->config_gsi); 277 } else { 278 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 279 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 280 } 281 282 return 0; 283 } 284 285 int virtio_pci__init(struct kvm *kvm, struct virtio_trans *vtrans, void *dev, 286 int device_id, int subsys_id, int class) 287 { 288 struct virtio_pci *vpci = vtrans->virtio; 289 u8 pin, line, ndev; 290 int r; 291 292 vpci->dev = dev; 293 vpci->msix_io_block = pci_get_io_space_block(PCI_IO_SIZE * 2); 294 295 r = ioport__register(IOPORT_EMPTY, &virtio_pci__io_ops, IOPORT_SIZE, vtrans); 296 if (r < 0) 297 return r; 298 299 vpci->base_addr = (u16)r; 300 kvm__register_mmio(kvm, vpci->msix_io_block, PCI_IO_SIZE, false, callback_mmio_table, vpci); 301 302 vpci->pci_hdr = (struct pci_device_header) { 303 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 304 .device_id = cpu_to_le16(device_id), 305 .header_type = PCI_HEADER_TYPE_NORMAL, 306 .revision_id = 0, 307 .class[0] = class & 0xff, 308 .class[1] = (class >> 8) & 0xff, 309 .class[2] = (class >> 16) & 0xff, 310 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 311 .subsys_id = cpu_to_le16(subsys_id), 312 .bar[0] = cpu_to_le32(vpci->base_addr 313 | PCI_BASE_ADDRESS_SPACE_IO), 314 .bar[1] = cpu_to_le32(vpci->msix_io_block 315 | PCI_BASE_ADDRESS_SPACE_MEMORY), 316 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 317 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 318 .bar_size[0] = IOPORT_SIZE, 319 .bar_size[1] = PCI_IO_SIZE, 320 .bar_size[3] = PCI_IO_SIZE, 321 }; 322 323 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 324 vpci->pci_hdr.msix.next = 0; 325 /* 326 * We at most have VIRTIO_PCI_MAX_VQ entries for virt queue, 327 * VIRTIO_PCI_MAX_CONFIG entries for config. 328 * 329 * To quote the PCI spec: 330 * 331 * System software reads this field to determine the 332 * MSI-X Table Size N, which is encoded as N-1. 333 * For example, a returned value of "00000000011" 334 * indicates a table size of 4. 335 */ 336 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG - 1); 337 338 /* 339 * Both table and PBA could be mapped on the same BAR, but for now 340 * we're not in short of BARs 341 */ 342 vpci->pci_hdr.msix.table_offset = cpu_to_le32(1); /* Use BAR 1 */ 343 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(1 | PCI_IO_SIZE); /* Use BAR 3 */ 344 vpci->config_vector = 0; 345 346 if (irq__register_device(subsys_id, &ndev, &pin, &line) < 0) 347 return -1; 348 349 vpci->pci_hdr.irq_pin = pin; 350 vpci->pci_hdr.irq_line = line; 351 pci__register(&vpci->pci_hdr, ndev); 352 353 return 0; 354 } 355