1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/virtio-pci-dev.h" 6 #include "kvm/irq.h" 7 #include "kvm/virtio.h" 8 #include "kvm/ioeventfd.h" 9 #include "kvm/virtio-trans.h" 10 11 #include <linux/virtio_pci.h> 12 #include <linux/byteorder.h> 13 #include <string.h> 14 15 struct virtio_trans_ops *virtio_pci__get_trans_ops(void) 16 { 17 static struct virtio_trans_ops virtio_pci_trans = (struct virtio_trans_ops) { 18 .signal_vq = virtio_pci__signal_vq, 19 .signal_config = virtio_pci__signal_config, 20 .init = virtio_pci__init, 21 }; 22 return &virtio_pci_trans; 23 }; 24 25 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 26 { 27 struct virtio_pci_ioevent_param *ioeventfd = param; 28 struct virtio_pci *vpci = ioeventfd->vtrans->virtio; 29 30 ioeventfd->vtrans->virtio_ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 31 } 32 33 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_trans *vtrans, u32 vq) 34 { 35 struct ioevent ioevent; 36 struct virtio_pci *vpci = vtrans->virtio; 37 38 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 39 .vtrans = vtrans, 40 .vq = vq, 41 }; 42 43 ioevent = (struct ioevent) { 44 .io_addr = vpci->base_addr + VIRTIO_PCI_QUEUE_NOTIFY, 45 .io_len = sizeof(u16), 46 .fn = virtio_pci__ioevent_callback, 47 .fn_ptr = &vpci->ioeventfds[vq], 48 .datamatch = vq, 49 .fn_kvm = kvm, 50 .fd = eventfd(0, 0), 51 }; 52 53 ioeventfd__add_event(&ioevent); 54 55 if (vtrans->virtio_ops->notify_vq_eventfd) 56 vtrans->virtio_ops->notify_vq_eventfd(kvm, vpci->dev, vq, ioevent.fd); 57 58 return 0; 59 } 60 61 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 62 { 63 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 64 } 65 66 static bool virtio_pci__specific_io_in(struct kvm *kvm, struct virtio_trans *vtrans, u16 port, 67 void *data, int size, int offset) 68 { 69 u32 config_offset; 70 struct virtio_pci *vpci = vtrans->virtio; 71 int type = virtio__get_dev_specific_field(offset - 20, 72 virtio_pci__msix_enabled(vpci), 73 &config_offset); 74 if (type == VIRTIO_PCI_O_MSIX) { 75 switch (offset) { 76 case VIRTIO_MSI_CONFIG_VECTOR: 77 ioport__write16(data, vpci->config_vector); 78 break; 79 case VIRTIO_MSI_QUEUE_VECTOR: 80 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 81 break; 82 }; 83 84 return true; 85 } else if (type == VIRTIO_PCI_O_CONFIG) { 86 u8 cfg; 87 88 cfg = vtrans->virtio_ops->get_config(kvm, vpci->dev, config_offset); 89 ioport__write8(data, cfg); 90 return true; 91 } 92 93 return false; 94 } 95 96 static bool virtio_pci__io_in(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 97 { 98 unsigned long offset; 99 bool ret = true; 100 struct virtio_trans *vtrans; 101 struct virtio_pci *vpci; 102 u32 val; 103 104 vtrans = ioport->priv; 105 vpci = vtrans->virtio; 106 offset = port - vpci->base_addr; 107 108 switch (offset) { 109 case VIRTIO_PCI_HOST_FEATURES: 110 val = vtrans->virtio_ops->get_host_features(kvm, vpci->dev); 111 ioport__write32(data, val); 112 break; 113 case VIRTIO_PCI_QUEUE_PFN: 114 val = vtrans->virtio_ops->get_pfn_vq(kvm, vpci->dev, vpci->queue_selector); 115 ioport__write32(data, val); 116 break; 117 case VIRTIO_PCI_QUEUE_NUM: 118 val = vtrans->virtio_ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 119 ioport__write16(data, val); 120 break; 121 case VIRTIO_PCI_STATUS: 122 ioport__write8(data, vpci->status); 123 break; 124 case VIRTIO_PCI_ISR: 125 ioport__write8(data, vpci->isr); 126 kvm__irq_line(kvm, vpci->pci_hdr.irq_line, VIRTIO_IRQ_LOW); 127 vpci->isr = VIRTIO_IRQ_LOW; 128 break; 129 default: 130 ret = virtio_pci__specific_io_in(kvm, vtrans, port, data, size, offset); 131 break; 132 }; 133 134 return ret; 135 } 136 137 static bool virtio_pci__specific_io_out(struct kvm *kvm, struct virtio_trans *vtrans, u16 port, 138 void *data, int size, int offset) 139 { 140 struct virtio_pci *vpci = vtrans->virtio; 141 u32 config_offset, gsi, vec; 142 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 143 &config_offset); 144 if (type == VIRTIO_PCI_O_MSIX) { 145 switch (offset) { 146 case VIRTIO_MSI_CONFIG_VECTOR: 147 vec = vpci->config_vector = ioport__read16(data); 148 149 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 150 151 vpci->config_gsi = gsi; 152 break; 153 case VIRTIO_MSI_QUEUE_VECTOR: { 154 vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); 155 156 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 157 vpci->gsis[vpci->queue_selector] = gsi; 158 if (vtrans->virtio_ops->notify_vq_gsi) 159 vtrans->virtio_ops->notify_vq_gsi(kvm, vpci->dev, 160 vpci->queue_selector, gsi); 161 break; 162 } 163 }; 164 165 return true; 166 } else if (type == VIRTIO_PCI_O_CONFIG) { 167 vtrans->virtio_ops->set_config(kvm, vpci->dev, *(u8 *)data, config_offset); 168 169 return true; 170 } 171 172 return false; 173 } 174 175 static bool virtio_pci__io_out(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 176 { 177 unsigned long offset; 178 bool ret = true; 179 struct virtio_trans *vtrans; 180 struct virtio_pci *vpci; 181 u32 val; 182 183 vtrans = ioport->priv; 184 vpci = vtrans->virtio; 185 offset = port - vpci->base_addr; 186 187 switch (offset) { 188 case VIRTIO_PCI_GUEST_FEATURES: 189 val = ioport__read32(data); 190 vtrans->virtio_ops->set_guest_features(kvm, vpci->dev, val); 191 break; 192 case VIRTIO_PCI_QUEUE_PFN: 193 val = ioport__read32(data); 194 virtio_pci__init_ioeventfd(kvm, vtrans, vpci->queue_selector); 195 vtrans->virtio_ops->init_vq(kvm, vpci->dev, vpci->queue_selector, val); 196 break; 197 case VIRTIO_PCI_QUEUE_SEL: 198 vpci->queue_selector = ioport__read16(data); 199 break; 200 case VIRTIO_PCI_QUEUE_NOTIFY: 201 val = ioport__read16(data); 202 vtrans->virtio_ops->notify_vq(kvm, vpci->dev, val); 203 break; 204 case VIRTIO_PCI_STATUS: 205 vpci->status = ioport__read8(data); 206 break; 207 default: 208 ret = virtio_pci__specific_io_out(kvm, vtrans, port, data, size, offset); 209 break; 210 }; 211 212 return ret; 213 } 214 215 static struct ioport_operations virtio_pci__io_ops = { 216 .io_in = virtio_pci__io_in, 217 .io_out = virtio_pci__io_out, 218 }; 219 220 static void callback_mmio_table(u64 addr, u8 *data, u32 len, u8 is_write, void *ptr) 221 { 222 struct virtio_pci *vpci = ptr; 223 void *table; 224 u32 offset; 225 226 if (addr > vpci->msix_io_block + PCI_IO_SIZE) { 227 table = &vpci->msix_pba; 228 offset = vpci->msix_io_block + PCI_IO_SIZE; 229 } else { 230 table = &vpci->msix_table; 231 offset = vpci->msix_io_block; 232 } 233 234 if (is_write) 235 memcpy(table + addr - offset, data, len); 236 else 237 memcpy(data, table + addr - offset, len); 238 } 239 240 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_trans *vtrans, u32 vq) 241 { 242 struct virtio_pci *vpci = vtrans->virtio; 243 int tbl = vpci->vq_vector[vq]; 244 245 if (virtio_pci__msix_enabled(vpci)) { 246 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 247 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 248 249 vpci->msix_pba |= 1 << tbl; 250 return 0; 251 } 252 253 kvm__irq_trigger(kvm, vpci->gsis[vq]); 254 } else { 255 vpci->isr = VIRTIO_IRQ_HIGH; 256 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 257 } 258 return 0; 259 } 260 261 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_trans *vtrans) 262 { 263 struct virtio_pci *vpci = vtrans->virtio; 264 int tbl = vpci->config_vector; 265 266 if (virtio_pci__msix_enabled(vpci)) { 267 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 268 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 269 270 vpci->msix_pba |= 1 << tbl; 271 return 0; 272 } 273 274 kvm__irq_trigger(kvm, vpci->config_gsi); 275 } else { 276 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 277 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 278 } 279 280 return 0; 281 } 282 283 int virtio_pci__init(struct kvm *kvm, struct virtio_trans *vtrans, void *dev, 284 int device_id, int subsys_id, int class) 285 { 286 struct virtio_pci *vpci = vtrans->virtio; 287 u8 pin, line, ndev; 288 289 vpci->dev = dev; 290 vpci->msix_io_block = pci_get_io_space_block(PCI_IO_SIZE * 2); 291 292 vpci->base_addr = ioport__register(IOPORT_EMPTY, &virtio_pci__io_ops, IOPORT_SIZE, vtrans); 293 kvm__register_mmio(kvm, vpci->msix_io_block, PCI_IO_SIZE, false, callback_mmio_table, vpci); 294 295 vpci->pci_hdr = (struct pci_device_header) { 296 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 297 .device_id = cpu_to_le16(device_id), 298 .header_type = PCI_HEADER_TYPE_NORMAL, 299 .revision_id = 0, 300 .class[0] = class & 0xff, 301 .class[1] = (class >> 8) & 0xff, 302 .class[2] = (class >> 16) & 0xff, 303 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 304 .subsys_id = cpu_to_le16(subsys_id), 305 .bar[0] = cpu_to_le32(vpci->base_addr 306 | PCI_BASE_ADDRESS_SPACE_IO), 307 .bar[1] = cpu_to_le32(vpci->msix_io_block 308 | PCI_BASE_ADDRESS_SPACE_MEMORY), 309 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 310 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 311 .bar_size[0] = IOPORT_SIZE, 312 .bar_size[1] = PCI_IO_SIZE, 313 .bar_size[3] = PCI_IO_SIZE, 314 }; 315 316 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 317 vpci->pci_hdr.msix.next = 0; 318 /* 319 * We at most have VIRTIO_PCI_MAX_VQ entries for virt queue, 320 * VIRTIO_PCI_MAX_CONFIG entries for config. 321 * 322 * To quote the PCI spec: 323 * 324 * System software reads this field to determine the 325 * MSI-X Table Size N, which is encoded as N-1. 326 * For example, a returned value of "00000000011" 327 * indicates a table size of 4. 328 */ 329 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG - 1); 330 331 /* 332 * Both table and PBA could be mapped on the same BAR, but for now 333 * we're not in short of BARs 334 */ 335 vpci->pci_hdr.msix.table_offset = cpu_to_le32(1); /* Use BAR 1 */ 336 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(1 | PCI_IO_SIZE); /* Use BAR 3 */ 337 vpci->config_vector = 0; 338 339 if (irq__register_device(subsys_id, &ndev, &pin, &line) < 0) 340 return -1; 341 342 vpci->pci_hdr.irq_pin = pin; 343 vpci->pci_hdr.irq_line = line; 344 pci__register(&vpci->pci_hdr, ndev); 345 346 return 0; 347 } 348