1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/virtio-pci-dev.h" 6 #include "kvm/irq.h" 7 #include "kvm/virtio.h" 8 #include "kvm/ioeventfd.h" 9 #include "kvm/virtio-trans.h" 10 11 #include <linux/virtio_pci.h> 12 #include <linux/byteorder.h> 13 #include <string.h> 14 15 struct virtio_trans_ops *virtio_pci__get_trans_ops(void) 16 { 17 static struct virtio_trans_ops virtio_pci_trans = (struct virtio_trans_ops) { 18 .signal_vq = virtio_pci__signal_vq, 19 .signal_config = virtio_pci__signal_config, 20 .init = virtio_pci__init, 21 .uninit = virtio_pci__exit, 22 }; 23 return &virtio_pci_trans; 24 }; 25 26 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 27 { 28 struct virtio_pci_ioevent_param *ioeventfd = param; 29 struct virtio_pci *vpci = ioeventfd->vtrans->virtio; 30 31 ioeventfd->vtrans->virtio_ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 32 } 33 34 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_trans *vtrans, u32 vq) 35 { 36 struct ioevent ioevent; 37 struct virtio_pci *vpci = vtrans->virtio; 38 int r; 39 40 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 41 .vtrans = vtrans, 42 .vq = vq, 43 }; 44 45 ioevent = (struct ioevent) { 46 .io_addr = vpci->base_addr + VIRTIO_PCI_QUEUE_NOTIFY, 47 .io_len = sizeof(u16), 48 .fn = virtio_pci__ioevent_callback, 49 .fn_ptr = &vpci->ioeventfds[vq], 50 .datamatch = vq, 51 .fn_kvm = kvm, 52 .fd = eventfd(0, 0), 53 }; 54 55 r = ioeventfd__add_event(&ioevent); 56 if (r) 57 return r; 58 59 if (vtrans->virtio_ops->notify_vq_eventfd) 60 vtrans->virtio_ops->notify_vq_eventfd(kvm, vpci->dev, vq, ioevent.fd); 61 62 return 0; 63 } 64 65 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 66 { 67 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 68 } 69 70 static bool virtio_pci__specific_io_in(struct kvm *kvm, struct virtio_trans *vtrans, u16 port, 71 void *data, int size, int offset) 72 { 73 u32 config_offset; 74 struct virtio_pci *vpci = vtrans->virtio; 75 int type = virtio__get_dev_specific_field(offset - 20, 76 virtio_pci__msix_enabled(vpci), 77 &config_offset); 78 if (type == VIRTIO_PCI_O_MSIX) { 79 switch (offset) { 80 case VIRTIO_MSI_CONFIG_VECTOR: 81 ioport__write16(data, vpci->config_vector); 82 break; 83 case VIRTIO_MSI_QUEUE_VECTOR: 84 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 85 break; 86 }; 87 88 return true; 89 } else if (type == VIRTIO_PCI_O_CONFIG) { 90 u8 cfg; 91 92 cfg = vtrans->virtio_ops->get_config(kvm, vpci->dev, config_offset); 93 ioport__write8(data, cfg); 94 return true; 95 } 96 97 return false; 98 } 99 100 static bool virtio_pci__io_in(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 101 { 102 unsigned long offset; 103 bool ret = true; 104 struct virtio_trans *vtrans; 105 struct virtio_pci *vpci; 106 u32 val; 107 108 vtrans = ioport->priv; 109 vpci = vtrans->virtio; 110 offset = port - vpci->base_addr; 111 112 switch (offset) { 113 case VIRTIO_PCI_HOST_FEATURES: 114 val = vtrans->virtio_ops->get_host_features(kvm, vpci->dev); 115 ioport__write32(data, val); 116 break; 117 case VIRTIO_PCI_QUEUE_PFN: 118 val = vtrans->virtio_ops->get_pfn_vq(kvm, vpci->dev, vpci->queue_selector); 119 ioport__write32(data, val); 120 break; 121 case VIRTIO_PCI_QUEUE_NUM: 122 val = vtrans->virtio_ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 123 ioport__write16(data, val); 124 break; 125 case VIRTIO_PCI_STATUS: 126 ioport__write8(data, vpci->status); 127 break; 128 case VIRTIO_PCI_ISR: 129 ioport__write8(data, vpci->isr); 130 kvm__irq_line(kvm, vpci->pci_hdr.irq_line, VIRTIO_IRQ_LOW); 131 vpci->isr = VIRTIO_IRQ_LOW; 132 break; 133 default: 134 ret = virtio_pci__specific_io_in(kvm, vtrans, port, data, size, offset); 135 break; 136 }; 137 138 return ret; 139 } 140 141 static bool virtio_pci__specific_io_out(struct kvm *kvm, struct virtio_trans *vtrans, u16 port, 142 void *data, int size, int offset) 143 { 144 struct virtio_pci *vpci = vtrans->virtio; 145 u32 config_offset, gsi, vec; 146 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 147 &config_offset); 148 if (type == VIRTIO_PCI_O_MSIX) { 149 switch (offset) { 150 case VIRTIO_MSI_CONFIG_VECTOR: 151 vec = vpci->config_vector = ioport__read16(data); 152 153 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 154 155 vpci->config_gsi = gsi; 156 break; 157 case VIRTIO_MSI_QUEUE_VECTOR: 158 vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); 159 160 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 161 vpci->gsis[vpci->queue_selector] = gsi; 162 if (vtrans->virtio_ops->notify_vq_gsi) 163 vtrans->virtio_ops->notify_vq_gsi(kvm, vpci->dev, 164 vpci->queue_selector, gsi); 165 break; 166 }; 167 168 return true; 169 } else if (type == VIRTIO_PCI_O_CONFIG) { 170 vtrans->virtio_ops->set_config(kvm, vpci->dev, *(u8 *)data, config_offset); 171 172 return true; 173 } 174 175 return false; 176 } 177 178 static bool virtio_pci__io_out(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 179 { 180 unsigned long offset; 181 bool ret = true; 182 struct virtio_trans *vtrans; 183 struct virtio_pci *vpci; 184 u32 val; 185 186 vtrans = ioport->priv; 187 vpci = vtrans->virtio; 188 offset = port - vpci->base_addr; 189 190 switch (offset) { 191 case VIRTIO_PCI_GUEST_FEATURES: 192 val = ioport__read32(data); 193 vtrans->virtio_ops->set_guest_features(kvm, vpci->dev, val); 194 break; 195 case VIRTIO_PCI_QUEUE_PFN: 196 val = ioport__read32(data); 197 virtio_pci__init_ioeventfd(kvm, vtrans, vpci->queue_selector); 198 vtrans->virtio_ops->init_vq(kvm, vpci->dev, vpci->queue_selector, val); 199 break; 200 case VIRTIO_PCI_QUEUE_SEL: 201 vpci->queue_selector = ioport__read16(data); 202 break; 203 case VIRTIO_PCI_QUEUE_NOTIFY: 204 val = ioport__read16(data); 205 vtrans->virtio_ops->notify_vq(kvm, vpci->dev, val); 206 break; 207 case VIRTIO_PCI_STATUS: 208 vpci->status = ioport__read8(data); 209 break; 210 default: 211 ret = virtio_pci__specific_io_out(kvm, vtrans, port, data, size, offset); 212 break; 213 }; 214 215 return ret; 216 } 217 218 static struct ioport_operations virtio_pci__io_ops = { 219 .io_in = virtio_pci__io_in, 220 .io_out = virtio_pci__io_out, 221 }; 222 223 static void callback_mmio_table(u64 addr, u8 *data, u32 len, u8 is_write, void *ptr) 224 { 225 struct virtio_pci *vpci = ptr; 226 void *table; 227 u32 offset; 228 229 if (addr > vpci->msix_io_block + PCI_IO_SIZE) { 230 table = &vpci->msix_pba; 231 offset = vpci->msix_io_block + PCI_IO_SIZE; 232 } else { 233 table = &vpci->msix_table; 234 offset = vpci->msix_io_block; 235 } 236 237 if (is_write) 238 memcpy(table + addr - offset, data, len); 239 else 240 memcpy(data, table + addr - offset, len); 241 } 242 243 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_trans *vtrans, u32 vq) 244 { 245 struct virtio_pci *vpci = vtrans->virtio; 246 int tbl = vpci->vq_vector[vq]; 247 248 if (virtio_pci__msix_enabled(vpci)) { 249 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 250 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 251 252 vpci->msix_pba |= 1 << tbl; 253 return 0; 254 } 255 256 kvm__irq_trigger(kvm, vpci->gsis[vq]); 257 } else { 258 vpci->isr = VIRTIO_IRQ_HIGH; 259 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 260 } 261 return 0; 262 } 263 264 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_trans *vtrans) 265 { 266 struct virtio_pci *vpci = vtrans->virtio; 267 int tbl = vpci->config_vector; 268 269 if (virtio_pci__msix_enabled(vpci)) { 270 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 271 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 272 273 vpci->msix_pba |= 1 << tbl; 274 return 0; 275 } 276 277 kvm__irq_trigger(kvm, vpci->config_gsi); 278 } else { 279 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 280 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 281 } 282 283 return 0; 284 } 285 286 int virtio_pci__init(struct kvm *kvm, struct virtio_trans *vtrans, void *dev, 287 int device_id, int subsys_id, int class) 288 { 289 struct virtio_pci *vpci = vtrans->virtio; 290 u8 pin, line, ndev; 291 int r; 292 293 vpci->dev = dev; 294 vpci->msix_io_block = pci_get_io_space_block(PCI_IO_SIZE * 2); 295 296 r = ioport__register(IOPORT_EMPTY, &virtio_pci__io_ops, IOPORT_SIZE, vtrans); 297 if (r < 0) 298 return r; 299 300 vpci->base_addr = (u16)r; 301 r = kvm__register_mmio(kvm, vpci->msix_io_block, PCI_IO_SIZE, false, callback_mmio_table, vpci); 302 if (r < 0) 303 goto free_ioport; 304 305 vpci->pci_hdr = (struct pci_device_header) { 306 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 307 .device_id = cpu_to_le16(device_id), 308 .header_type = PCI_HEADER_TYPE_NORMAL, 309 .revision_id = 0, 310 .class[0] = class & 0xff, 311 .class[1] = (class >> 8) & 0xff, 312 .class[2] = (class >> 16) & 0xff, 313 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 314 .subsys_id = cpu_to_le16(subsys_id), 315 .bar[0] = cpu_to_le32(vpci->base_addr 316 | PCI_BASE_ADDRESS_SPACE_IO), 317 .bar[1] = cpu_to_le32(vpci->msix_io_block 318 | PCI_BASE_ADDRESS_SPACE_MEMORY), 319 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 320 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 321 .bar_size[0] = IOPORT_SIZE, 322 .bar_size[1] = PCI_IO_SIZE, 323 .bar_size[3] = PCI_IO_SIZE, 324 }; 325 326 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 327 vpci->pci_hdr.msix.next = 0; 328 /* 329 * We at most have VIRTIO_PCI_MAX_VQ entries for virt queue, 330 * VIRTIO_PCI_MAX_CONFIG entries for config. 331 * 332 * To quote the PCI spec: 333 * 334 * System software reads this field to determine the 335 * MSI-X Table Size N, which is encoded as N-1. 336 * For example, a returned value of "00000000011" 337 * indicates a table size of 4. 338 */ 339 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG - 1); 340 341 /* 342 * Both table and PBA could be mapped on the same BAR, but for now 343 * we're not in short of BARs 344 */ 345 vpci->pci_hdr.msix.table_offset = cpu_to_le32(1); /* Use BAR 1 */ 346 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(1 | PCI_IO_SIZE); /* Use BAR 3 */ 347 vpci->config_vector = 0; 348 349 r = irq__register_device(subsys_id, &ndev, &pin, &line); 350 if (r < 0) 351 goto free_mmio; 352 353 vpci->pci_hdr.irq_pin = pin; 354 vpci->pci_hdr.irq_line = line; 355 r = pci__register(&vpci->pci_hdr, ndev); 356 if (r < 0) 357 goto free_ioport; 358 359 return 0; 360 361 free_mmio: 362 kvm__deregister_mmio(kvm, vpci->msix_io_block); 363 free_ioport: 364 ioport__unregister(vpci->base_addr); 365 return r; 366 } 367 368 int virtio_pci__exit(struct kvm *kvm, struct virtio_trans *vtrans) 369 { 370 struct virtio_pci *vpci = vtrans->virtio; 371 int i; 372 373 kvm__deregister_mmio(kvm, vpci->msix_io_block); 374 ioport__unregister(vpci->base_addr); 375 376 for (i = 0; i < VIRTIO_PCI_MAX_VQ; i++) 377 ioeventfd__del_event(vpci->base_addr + VIRTIO_PCI_QUEUE_NOTIFY, i); 378 379 return 0; 380 }