1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/kvm-cpu.h" 6 #include "kvm/virtio-pci-dev.h" 7 #include "kvm/irq.h" 8 #include "kvm/virtio.h" 9 #include "kvm/ioeventfd.h" 10 11 #include <sys/ioctl.h> 12 #include <linux/virtio_pci.h> 13 #include <linux/byteorder.h> 14 #include <string.h> 15 16 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 17 { 18 struct virtio_pci_ioevent_param *ioeventfd = param; 19 struct virtio_pci *vpci = ioeventfd->vdev->virtio; 20 21 ioeventfd->vdev->ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 22 } 23 24 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 25 { 26 struct ioevent ioevent; 27 struct virtio_pci *vpci = vdev->virtio; 28 int i, r, flags = IOEVENTFD_FLAG_PIO; 29 int fds[2]; 30 31 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 32 .vdev = vdev, 33 .vq = vq, 34 }; 35 36 ioevent = (struct ioevent) { 37 .fn = virtio_pci__ioevent_callback, 38 .fn_ptr = &vpci->ioeventfds[vq], 39 .datamatch = vq, 40 .fn_kvm = kvm, 41 }; 42 43 /* 44 * Vhost will poll the eventfd in host kernel side, otherwise we 45 * need to poll in userspace. 46 */ 47 if (!vdev->use_vhost) 48 flags |= IOEVENTFD_FLAG_USER_POLL; 49 50 /* ioport */ 51 ioevent.io_addr = vpci->port_addr + VIRTIO_PCI_QUEUE_NOTIFY; 52 ioevent.io_len = sizeof(u16); 53 ioevent.fd = fds[0] = eventfd(0, 0); 54 r = ioeventfd__add_event(&ioevent, flags); 55 if (r) 56 return r; 57 58 /* mmio */ 59 ioevent.io_addr = vpci->mmio_addr + VIRTIO_PCI_QUEUE_NOTIFY; 60 ioevent.io_len = sizeof(u32); 61 ioevent.fd = fds[1] = eventfd(0, 0); 62 r = ioeventfd__add_event(&ioevent, flags); 63 if (r) 64 goto free_ioport_evt; 65 66 if (vdev->ops->notify_vq_eventfd) 67 for (i = 0; i < 2; ++i) 68 vdev->ops->notify_vq_eventfd(kvm, vpci->dev, vq, 69 fds[i]); 70 return 0; 71 72 free_ioport_evt: 73 ioeventfd__del_event(vpci->port_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 74 return r; 75 } 76 77 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 78 { 79 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 80 } 81 82 static bool virtio_pci__specific_io_in(struct kvm *kvm, struct virtio_device *vdev, u16 port, 83 void *data, int size, int offset) 84 { 85 u32 config_offset; 86 struct virtio_pci *vpci = vdev->virtio; 87 int type = virtio__get_dev_specific_field(offset - 20, 88 virtio_pci__msix_enabled(vpci), 89 &config_offset); 90 if (type == VIRTIO_PCI_O_MSIX) { 91 switch (offset) { 92 case VIRTIO_MSI_CONFIG_VECTOR: 93 ioport__write16(data, vpci->config_vector); 94 break; 95 case VIRTIO_MSI_QUEUE_VECTOR: 96 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 97 break; 98 }; 99 100 return true; 101 } else if (type == VIRTIO_PCI_O_CONFIG) { 102 u8 cfg; 103 104 cfg = vdev->ops->get_config(kvm, vpci->dev)[config_offset]; 105 ioport__write8(data, cfg); 106 return true; 107 } 108 109 return false; 110 } 111 112 static bool virtio_pci__io_in(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 113 { 114 unsigned long offset; 115 bool ret = true; 116 struct virtio_device *vdev; 117 struct virtio_pci *vpci; 118 struct kvm *kvm; 119 u32 val; 120 121 kvm = vcpu->kvm; 122 vdev = ioport->priv; 123 vpci = vdev->virtio; 124 offset = port - vpci->port_addr; 125 126 switch (offset) { 127 case VIRTIO_PCI_HOST_FEATURES: 128 val = vdev->ops->get_host_features(kvm, vpci->dev); 129 ioport__write32(data, val); 130 break; 131 case VIRTIO_PCI_QUEUE_PFN: 132 val = vdev->ops->get_pfn_vq(kvm, vpci->dev, vpci->queue_selector); 133 ioport__write32(data, val); 134 break; 135 case VIRTIO_PCI_QUEUE_NUM: 136 val = vdev->ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 137 ioport__write16(data, val); 138 break; 139 case VIRTIO_PCI_STATUS: 140 ioport__write8(data, vpci->status); 141 break; 142 case VIRTIO_PCI_ISR: 143 ioport__write8(data, vpci->isr); 144 kvm__irq_line(kvm, vpci->pci_hdr.irq_line, VIRTIO_IRQ_LOW); 145 vpci->isr = VIRTIO_IRQ_LOW; 146 break; 147 default: 148 ret = virtio_pci__specific_io_in(kvm, vdev, port, data, size, offset); 149 break; 150 }; 151 152 return ret; 153 } 154 155 static bool virtio_pci__specific_io_out(struct kvm *kvm, struct virtio_device *vdev, u16 port, 156 void *data, int size, int offset) 157 { 158 struct virtio_pci *vpci = vdev->virtio; 159 u32 config_offset, gsi, vec; 160 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 161 &config_offset); 162 if (type == VIRTIO_PCI_O_MSIX) { 163 switch (offset) { 164 case VIRTIO_MSI_CONFIG_VECTOR: 165 vec = vpci->config_vector = ioport__read16(data); 166 if (vec == VIRTIO_MSI_NO_VECTOR) 167 break; 168 169 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 170 171 vpci->config_gsi = gsi; 172 break; 173 case VIRTIO_MSI_QUEUE_VECTOR: 174 vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); 175 176 if (vec == VIRTIO_MSI_NO_VECTOR) 177 break; 178 179 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 180 vpci->gsis[vpci->queue_selector] = gsi; 181 if (vdev->ops->notify_vq_gsi) 182 vdev->ops->notify_vq_gsi(kvm, vpci->dev, 183 vpci->queue_selector, gsi); 184 break; 185 }; 186 187 return true; 188 } else if (type == VIRTIO_PCI_O_CONFIG) { 189 vdev->ops->get_config(kvm, vpci->dev)[config_offset] = *(u8 *)data; 190 191 return true; 192 } 193 194 return false; 195 } 196 197 static bool virtio_pci__io_out(struct ioport *ioport, struct kvm_cpu *vcpu, u16 port, void *data, int size) 198 { 199 unsigned long offset; 200 bool ret = true; 201 struct virtio_device *vdev; 202 struct virtio_pci *vpci; 203 struct kvm *kvm; 204 u32 val; 205 206 kvm = vcpu->kvm; 207 vdev = ioport->priv; 208 vpci = vdev->virtio; 209 offset = port - vpci->port_addr; 210 211 switch (offset) { 212 case VIRTIO_PCI_GUEST_FEATURES: 213 val = ioport__read32(data); 214 vdev->ops->set_guest_features(kvm, vpci->dev, val); 215 break; 216 case VIRTIO_PCI_QUEUE_PFN: 217 val = ioport__read32(data); 218 virtio_pci__init_ioeventfd(kvm, vdev, vpci->queue_selector); 219 vdev->ops->init_vq(kvm, vpci->dev, vpci->queue_selector, 220 1 << VIRTIO_PCI_QUEUE_ADDR_SHIFT, 221 VIRTIO_PCI_VRING_ALIGN, val); 222 break; 223 case VIRTIO_PCI_QUEUE_SEL: 224 vpci->queue_selector = ioport__read16(data); 225 break; 226 case VIRTIO_PCI_QUEUE_NOTIFY: 227 val = ioport__read16(data); 228 vdev->ops->notify_vq(kvm, vpci->dev, val); 229 break; 230 case VIRTIO_PCI_STATUS: 231 vpci->status = ioport__read8(data); 232 if (!vpci->status) /* Sample endianness on reset */ 233 vdev->endian = kvm_cpu__get_endianness(vcpu); 234 if (vdev->ops->notify_status) 235 vdev->ops->notify_status(kvm, vpci->dev, vpci->status); 236 break; 237 default: 238 ret = virtio_pci__specific_io_out(kvm, vdev, port, data, size, offset); 239 break; 240 }; 241 242 return ret; 243 } 244 245 static struct ioport_operations virtio_pci__io_ops = { 246 .io_in = virtio_pci__io_in, 247 .io_out = virtio_pci__io_out, 248 }; 249 250 static void virtio_pci__msix_mmio_callback(struct kvm_cpu *vcpu, 251 u64 addr, u8 *data, u32 len, 252 u8 is_write, void *ptr) 253 { 254 struct virtio_pci *vpci = ptr; 255 void *table; 256 u32 offset; 257 258 if (addr > vpci->msix_io_block + PCI_IO_SIZE) { 259 table = &vpci->msix_pba; 260 offset = vpci->msix_io_block + PCI_IO_SIZE; 261 } else { 262 table = &vpci->msix_table; 263 offset = vpci->msix_io_block; 264 } 265 266 if (is_write) 267 memcpy(table + addr - offset, data, len); 268 else 269 memcpy(data, table + addr - offset, len); 270 } 271 272 static void virtio_pci__signal_msi(struct kvm *kvm, struct virtio_pci *vpci, int vec) 273 { 274 struct kvm_msi msi = { 275 .address_lo = vpci->msix_table[vec].msg.address_lo, 276 .address_hi = vpci->msix_table[vec].msg.address_hi, 277 .data = vpci->msix_table[vec].msg.data, 278 }; 279 280 ioctl(kvm->vm_fd, KVM_SIGNAL_MSI, &msi); 281 } 282 283 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 284 { 285 struct virtio_pci *vpci = vdev->virtio; 286 int tbl = vpci->vq_vector[vq]; 287 288 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 289 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 290 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 291 292 vpci->msix_pba |= 1 << tbl; 293 return 0; 294 } 295 296 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 297 virtio_pci__signal_msi(kvm, vpci, vpci->vq_vector[vq]); 298 else 299 kvm__irq_trigger(kvm, vpci->gsis[vq]); 300 } else { 301 vpci->isr = VIRTIO_IRQ_HIGH; 302 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 303 } 304 return 0; 305 } 306 307 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_device *vdev) 308 { 309 struct virtio_pci *vpci = vdev->virtio; 310 int tbl = vpci->config_vector; 311 312 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 313 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 314 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 315 316 vpci->msix_pba |= 1 << tbl; 317 return 0; 318 } 319 320 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 321 virtio_pci__signal_msi(kvm, vpci, tbl); 322 else 323 kvm__irq_trigger(kvm, vpci->config_gsi); 324 } else { 325 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 326 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 327 } 328 329 return 0; 330 } 331 332 static void virtio_pci__io_mmio_callback(struct kvm_cpu *vcpu, 333 u64 addr, u8 *data, u32 len, 334 u8 is_write, void *ptr) 335 { 336 struct virtio_pci *vpci = ptr; 337 int direction = is_write ? KVM_EXIT_IO_OUT : KVM_EXIT_IO_IN; 338 u16 port = vpci->port_addr + (addr & (IOPORT_SIZE - 1)); 339 340 kvm__emulate_io(vcpu, port, data, direction, len, 1); 341 } 342 343 int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev, 344 int device_id, int subsys_id, int class) 345 { 346 struct virtio_pci *vpci = vdev->virtio; 347 int r; 348 349 vpci->kvm = kvm; 350 vpci->dev = dev; 351 352 r = ioport__register(kvm, IOPORT_EMPTY, &virtio_pci__io_ops, IOPORT_SIZE, vdev); 353 if (r < 0) 354 return r; 355 vpci->port_addr = (u16)r; 356 357 vpci->mmio_addr = pci_get_io_space_block(IOPORT_SIZE); 358 r = kvm__register_mmio(kvm, vpci->mmio_addr, IOPORT_SIZE, false, 359 virtio_pci__io_mmio_callback, vpci); 360 if (r < 0) 361 goto free_ioport; 362 363 vpci->msix_io_block = pci_get_io_space_block(PCI_IO_SIZE * 2); 364 r = kvm__register_mmio(kvm, vpci->msix_io_block, PCI_IO_SIZE * 2, false, 365 virtio_pci__msix_mmio_callback, vpci); 366 if (r < 0) 367 goto free_mmio; 368 369 vpci->pci_hdr = (struct pci_device_header) { 370 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 371 .device_id = cpu_to_le16(device_id), 372 .command = PCI_COMMAND_IO | PCI_COMMAND_MEMORY, 373 .header_type = PCI_HEADER_TYPE_NORMAL, 374 .revision_id = 0, 375 .class[0] = class & 0xff, 376 .class[1] = (class >> 8) & 0xff, 377 .class[2] = (class >> 16) & 0xff, 378 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 379 .subsys_id = cpu_to_le16(subsys_id), 380 .bar[0] = cpu_to_le32(vpci->mmio_addr 381 | PCI_BASE_ADDRESS_SPACE_MEMORY), 382 .bar[1] = cpu_to_le32(vpci->port_addr 383 | PCI_BASE_ADDRESS_SPACE_IO), 384 .bar[2] = cpu_to_le32(vpci->msix_io_block 385 | PCI_BASE_ADDRESS_SPACE_MEMORY), 386 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 387 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 388 .bar_size[0] = IOPORT_SIZE, 389 .bar_size[1] = IOPORT_SIZE, 390 .bar_size[2] = PCI_IO_SIZE * 2, 391 }; 392 393 vpci->dev_hdr = (struct device_header) { 394 .bus_type = DEVICE_BUS_PCI, 395 .data = &vpci->pci_hdr, 396 }; 397 398 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 399 vpci->pci_hdr.msix.next = 0; 400 /* 401 * We at most have VIRTIO_PCI_MAX_VQ entries for virt queue, 402 * VIRTIO_PCI_MAX_CONFIG entries for config. 403 * 404 * To quote the PCI spec: 405 * 406 * System software reads this field to determine the 407 * MSI-X Table Size N, which is encoded as N-1. 408 * For example, a returned value of "00000000011" 409 * indicates a table size of 4. 410 */ 411 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG - 1); 412 413 /* Both table and PBA are mapped to the same BAR (2) */ 414 vpci->pci_hdr.msix.table_offset = cpu_to_le32(2); 415 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(2 | PCI_IO_SIZE); 416 vpci->config_vector = 0; 417 418 if (kvm__supports_extension(kvm, KVM_CAP_SIGNAL_MSI)) 419 vpci->features |= VIRTIO_PCI_F_SIGNAL_MSI; 420 421 r = device__register(&vpci->dev_hdr); 422 if (r < 0) 423 goto free_msix_mmio; 424 425 return 0; 426 427 free_msix_mmio: 428 kvm__deregister_mmio(kvm, vpci->msix_io_block); 429 free_mmio: 430 kvm__deregister_mmio(kvm, vpci->mmio_addr); 431 free_ioport: 432 ioport__unregister(kvm, vpci->port_addr); 433 return r; 434 } 435 436 int virtio_pci__exit(struct kvm *kvm, struct virtio_device *vdev) 437 { 438 struct virtio_pci *vpci = vdev->virtio; 439 int i; 440 441 kvm__deregister_mmio(kvm, vpci->mmio_addr); 442 kvm__deregister_mmio(kvm, vpci->msix_io_block); 443 ioport__unregister(kvm, vpci->port_addr); 444 445 for (i = 0; i < VIRTIO_PCI_MAX_VQ; i++) { 446 ioeventfd__del_event(vpci->port_addr + VIRTIO_PCI_QUEUE_NOTIFY, i); 447 ioeventfd__del_event(vpci->mmio_addr + VIRTIO_PCI_QUEUE_NOTIFY, i); 448 } 449 450 return 0; 451 } 452