1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/virtio-pci-dev.h" 6 #include "kvm/irq.h" 7 #include "kvm/virtio.h" 8 #include "kvm/ioeventfd.h" 9 10 #include <sys/ioctl.h> 11 #include <linux/virtio_pci.h> 12 #include <linux/byteorder.h> 13 #include <string.h> 14 15 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 16 { 17 struct virtio_pci_ioevent_param *ioeventfd = param; 18 struct virtio_pci *vpci = ioeventfd->vdev->virtio; 19 20 ioeventfd->vdev->ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 21 } 22 23 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 24 { 25 struct ioevent ioevent; 26 struct virtio_pci *vpci = vdev->virtio; 27 int r; 28 29 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 30 .vdev = vdev, 31 .vq = vq, 32 }; 33 34 ioevent = (struct ioevent) { 35 .io_addr = vpci->base_addr + VIRTIO_PCI_QUEUE_NOTIFY, 36 .io_len = sizeof(u16), 37 .fn = virtio_pci__ioevent_callback, 38 .fn_ptr = &vpci->ioeventfds[vq], 39 .datamatch = vq, 40 .fn_kvm = kvm, 41 .fd = eventfd(0, 0), 42 }; 43 44 if (vdev->use_vhost) 45 /* 46 * Vhost will poll the eventfd in host kernel side, 47 * no need to poll in userspace. 48 */ 49 r = ioeventfd__add_event(&ioevent, true, false); 50 else 51 /* Need to poll in userspace. */ 52 r = ioeventfd__add_event(&ioevent, true, true); 53 if (r) 54 return r; 55 56 if (vdev->ops->notify_vq_eventfd) 57 vdev->ops->notify_vq_eventfd(kvm, vpci->dev, vq, ioevent.fd); 58 59 return 0; 60 } 61 62 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 63 { 64 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 65 } 66 67 static bool virtio_pci__specific_io_in(struct kvm *kvm, struct virtio_device *vdev, u16 port, 68 void *data, int size, int offset) 69 { 70 u32 config_offset; 71 struct virtio_pci *vpci = vdev->virtio; 72 int type = virtio__get_dev_specific_field(offset - 20, 73 virtio_pci__msix_enabled(vpci), 74 &config_offset); 75 if (type == VIRTIO_PCI_O_MSIX) { 76 switch (offset) { 77 case VIRTIO_MSI_CONFIG_VECTOR: 78 ioport__write16(data, vpci->config_vector); 79 break; 80 case VIRTIO_MSI_QUEUE_VECTOR: 81 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 82 break; 83 }; 84 85 return true; 86 } else if (type == VIRTIO_PCI_O_CONFIG) { 87 u8 cfg; 88 89 cfg = vdev->ops->get_config(kvm, vpci->dev)[config_offset]; 90 ioport__write8(data, cfg); 91 return true; 92 } 93 94 return false; 95 } 96 97 static bool virtio_pci__io_in(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 98 { 99 unsigned long offset; 100 bool ret = true; 101 struct virtio_device *vdev; 102 struct virtio_pci *vpci; 103 u32 val; 104 105 vdev = ioport->priv; 106 vpci = vdev->virtio; 107 offset = port - vpci->base_addr; 108 109 switch (offset) { 110 case VIRTIO_PCI_HOST_FEATURES: 111 val = vdev->ops->get_host_features(kvm, vpci->dev); 112 ioport__write32(data, val); 113 break; 114 case VIRTIO_PCI_QUEUE_PFN: 115 val = vdev->ops->get_pfn_vq(kvm, vpci->dev, vpci->queue_selector); 116 ioport__write32(data, val); 117 break; 118 case VIRTIO_PCI_QUEUE_NUM: 119 val = vdev->ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 120 ioport__write16(data, val); 121 break; 122 case VIRTIO_PCI_STATUS: 123 ioport__write8(data, vpci->status); 124 break; 125 case VIRTIO_PCI_ISR: 126 ioport__write8(data, vpci->isr); 127 kvm__irq_line(kvm, vpci->pci_hdr.irq_line, VIRTIO_IRQ_LOW); 128 vpci->isr = VIRTIO_IRQ_LOW; 129 break; 130 default: 131 ret = virtio_pci__specific_io_in(kvm, vdev, port, data, size, offset); 132 break; 133 }; 134 135 return ret; 136 } 137 138 static bool virtio_pci__specific_io_out(struct kvm *kvm, struct virtio_device *vdev, u16 port, 139 void *data, int size, int offset) 140 { 141 struct virtio_pci *vpci = vdev->virtio; 142 u32 config_offset, gsi, vec; 143 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 144 &config_offset); 145 if (type == VIRTIO_PCI_O_MSIX) { 146 switch (offset) { 147 case VIRTIO_MSI_CONFIG_VECTOR: 148 vec = vpci->config_vector = ioport__read16(data); 149 if (vec == VIRTIO_MSI_NO_VECTOR) 150 break; 151 152 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 153 154 vpci->config_gsi = gsi; 155 break; 156 case VIRTIO_MSI_QUEUE_VECTOR: 157 vec = vpci->vq_vector[vpci->queue_selector] = ioport__read16(data); 158 159 if (vec == VIRTIO_MSI_NO_VECTOR) 160 break; 161 162 gsi = irq__add_msix_route(kvm, &vpci->msix_table[vec].msg); 163 vpci->gsis[vpci->queue_selector] = gsi; 164 if (vdev->ops->notify_vq_gsi) 165 vdev->ops->notify_vq_gsi(kvm, vpci->dev, 166 vpci->queue_selector, gsi); 167 break; 168 }; 169 170 return true; 171 } else if (type == VIRTIO_PCI_O_CONFIG) { 172 vdev->ops->get_config(kvm, vpci->dev)[config_offset] = *(u8 *)data; 173 174 return true; 175 } 176 177 return false; 178 } 179 180 static bool virtio_pci__io_out(struct ioport *ioport, struct kvm *kvm, u16 port, void *data, int size) 181 { 182 unsigned long offset; 183 bool ret = true; 184 struct virtio_device *vdev; 185 struct virtio_pci *vpci; 186 u32 val; 187 188 vdev = ioport->priv; 189 vpci = vdev->virtio; 190 offset = port - vpci->base_addr; 191 192 switch (offset) { 193 case VIRTIO_PCI_GUEST_FEATURES: 194 val = ioport__read32(data); 195 vdev->ops->set_guest_features(kvm, vpci->dev, val); 196 break; 197 case VIRTIO_PCI_QUEUE_PFN: 198 val = ioport__read32(data); 199 virtio_pci__init_ioeventfd(kvm, vdev, vpci->queue_selector); 200 vdev->ops->init_vq(kvm, vpci->dev, vpci->queue_selector, val); 201 break; 202 case VIRTIO_PCI_QUEUE_SEL: 203 vpci->queue_selector = ioport__read16(data); 204 break; 205 case VIRTIO_PCI_QUEUE_NOTIFY: 206 val = ioport__read16(data); 207 vdev->ops->notify_vq(kvm, vpci->dev, val); 208 break; 209 case VIRTIO_PCI_STATUS: 210 vpci->status = ioport__read8(data); 211 break; 212 default: 213 ret = virtio_pci__specific_io_out(kvm, vdev, port, data, size, offset); 214 break; 215 }; 216 217 return ret; 218 } 219 220 static struct ioport_operations virtio_pci__io_ops = { 221 .io_in = virtio_pci__io_in, 222 .io_out = virtio_pci__io_out, 223 }; 224 225 static void virtio_pci__mmio_callback(u64 addr, u8 *data, u32 len, u8 is_write, void *ptr) 226 { 227 struct virtio_pci *vpci = ptr; 228 void *table; 229 u32 offset; 230 231 if (addr > vpci->msix_io_block + PCI_IO_SIZE) { 232 table = &vpci->msix_pba; 233 offset = vpci->msix_io_block + PCI_IO_SIZE; 234 } else { 235 table = &vpci->msix_table; 236 offset = vpci->msix_io_block; 237 } 238 239 if (is_write) 240 memcpy(table + addr - offset, data, len); 241 else 242 memcpy(data, table + addr - offset, len); 243 } 244 245 static void virtio_pci__signal_msi(struct kvm *kvm, struct virtio_pci *vpci, int vec) 246 { 247 struct kvm_msi msi = { 248 .address_lo = vpci->msix_table[vec].msg.address_lo, 249 .address_hi = vpci->msix_table[vec].msg.address_hi, 250 .data = vpci->msix_table[vec].msg.data, 251 }; 252 253 ioctl(kvm->vm_fd, KVM_SIGNAL_MSI, &msi); 254 } 255 256 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 257 { 258 struct virtio_pci *vpci = vdev->virtio; 259 int tbl = vpci->vq_vector[vq]; 260 261 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 262 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 263 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 264 265 vpci->msix_pba |= 1 << tbl; 266 return 0; 267 } 268 269 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 270 virtio_pci__signal_msi(kvm, vpci, vpci->vq_vector[vq]); 271 else 272 kvm__irq_trigger(kvm, vpci->gsis[vq]); 273 } else { 274 vpci->isr = VIRTIO_IRQ_HIGH; 275 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 276 } 277 return 0; 278 } 279 280 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_device *vdev) 281 { 282 struct virtio_pci *vpci = vdev->virtio; 283 int tbl = vpci->config_vector; 284 285 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 286 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 287 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 288 289 vpci->msix_pba |= 1 << tbl; 290 return 0; 291 } 292 293 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 294 virtio_pci__signal_msi(kvm, vpci, tbl); 295 else 296 kvm__irq_trigger(kvm, vpci->config_gsi); 297 } else { 298 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 299 kvm__irq_trigger(kvm, vpci->pci_hdr.irq_line); 300 } 301 302 return 0; 303 } 304 305 int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev, 306 int device_id, int subsys_id, int class) 307 { 308 struct virtio_pci *vpci = vdev->virtio; 309 u8 pin, line; 310 int r; 311 312 vpci->dev = dev; 313 vpci->msix_io_block = pci_get_io_space_block(PCI_IO_SIZE * 2); 314 315 r = ioport__register(kvm, IOPORT_EMPTY, &virtio_pci__io_ops, IOPORT_SIZE, vdev); 316 if (r < 0) 317 return r; 318 319 vpci->base_addr = (u16)r; 320 r = kvm__register_mmio(kvm, vpci->msix_io_block, PCI_IO_SIZE, false, 321 virtio_pci__mmio_callback, vpci); 322 if (r < 0) 323 goto free_ioport; 324 325 vpci->pci_hdr = (struct pci_device_header) { 326 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 327 .device_id = cpu_to_le16(device_id), 328 .header_type = PCI_HEADER_TYPE_NORMAL, 329 .revision_id = 0, 330 .class[0] = class & 0xff, 331 .class[1] = (class >> 8) & 0xff, 332 .class[2] = (class >> 16) & 0xff, 333 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 334 .subsys_id = cpu_to_le16(subsys_id), 335 .bar[0] = cpu_to_le32(vpci->base_addr 336 | PCI_BASE_ADDRESS_SPACE_IO), 337 .bar[1] = cpu_to_le32(vpci->msix_io_block 338 | PCI_BASE_ADDRESS_SPACE_MEMORY), 339 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 340 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 341 .bar_size[0] = IOPORT_SIZE, 342 .bar_size[1] = PCI_IO_SIZE, 343 .bar_size[3] = PCI_IO_SIZE, 344 }; 345 346 vpci->dev_hdr = (struct device_header) { 347 .bus_type = DEVICE_BUS_PCI, 348 .data = &vpci->pci_hdr, 349 }; 350 351 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 352 vpci->pci_hdr.msix.next = 0; 353 /* 354 * We at most have VIRTIO_PCI_MAX_VQ entries for virt queue, 355 * VIRTIO_PCI_MAX_CONFIG entries for config. 356 * 357 * To quote the PCI spec: 358 * 359 * System software reads this field to determine the 360 * MSI-X Table Size N, which is encoded as N-1. 361 * For example, a returned value of "00000000011" 362 * indicates a table size of 4. 363 */ 364 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG - 1); 365 366 /* 367 * Both table and PBA could be mapped on the same BAR, but for now 368 * we're not in short of BARs 369 */ 370 vpci->pci_hdr.msix.table_offset = cpu_to_le32(1); /* Use BAR 1 */ 371 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(1 | PCI_IO_SIZE); /* Use BAR 3 */ 372 vpci->config_vector = 0; 373 374 r = irq__register_device(subsys_id, &pin, &line); 375 if (r < 0) 376 goto free_mmio; 377 378 if (kvm__supports_extension(kvm, KVM_CAP_SIGNAL_MSI)) 379 vpci->features |= VIRTIO_PCI_F_SIGNAL_MSI; 380 381 vpci->pci_hdr.irq_pin = pin; 382 vpci->pci_hdr.irq_line = line; 383 r = device__register(&vpci->dev_hdr); 384 if (r < 0) 385 goto free_ioport; 386 387 return 0; 388 389 free_mmio: 390 kvm__deregister_mmio(kvm, vpci->msix_io_block); 391 free_ioport: 392 ioport__unregister(kvm, vpci->base_addr); 393 return r; 394 } 395 396 int virtio_pci__exit(struct kvm *kvm, struct virtio_device *vdev) 397 { 398 struct virtio_pci *vpci = vdev->virtio; 399 int i; 400 401 kvm__deregister_mmio(kvm, vpci->msix_io_block); 402 ioport__unregister(kvm, vpci->base_addr); 403 404 for (i = 0; i < VIRTIO_PCI_MAX_VQ; i++) 405 ioeventfd__del_event(vpci->base_addr + VIRTIO_PCI_QUEUE_NOTIFY, i); 406 407 return 0; 408 } 409