1 #include "kvm/virtio-pci.h" 2 3 #include "kvm/ioport.h" 4 #include "kvm/kvm.h" 5 #include "kvm/kvm-cpu.h" 6 #include "kvm/virtio-pci-dev.h" 7 #include "kvm/irq.h" 8 #include "kvm/virtio.h" 9 #include "kvm/ioeventfd.h" 10 #include "kvm/util.h" 11 12 #include <sys/ioctl.h> 13 #include <linux/virtio_pci.h> 14 #include <linux/byteorder.h> 15 #include <assert.h> 16 #include <string.h> 17 18 #define ALIGN_UP(x, s) ALIGN((x) + (s) - 1, (s)) 19 #define VIRTIO_NR_MSIX (VIRTIO_PCI_MAX_VQ + VIRTIO_PCI_MAX_CONFIG) 20 #define VIRTIO_MSIX_TABLE_SIZE (VIRTIO_NR_MSIX * 16) 21 #define VIRTIO_MSIX_PBA_SIZE (ALIGN_UP(VIRTIO_MSIX_TABLE_SIZE, 64) / 8) 22 #define VIRTIO_MSIX_BAR_SIZE (1UL << fls_long(VIRTIO_MSIX_TABLE_SIZE + \ 23 VIRTIO_MSIX_PBA_SIZE)) 24 25 static u16 virtio_pci__port_addr(struct virtio_pci *vpci) 26 { 27 return pci__bar_address(&vpci->pci_hdr, 0); 28 } 29 30 static u32 virtio_pci__mmio_addr(struct virtio_pci *vpci) 31 { 32 return pci__bar_address(&vpci->pci_hdr, 1); 33 } 34 35 static u32 virtio_pci__msix_io_addr(struct virtio_pci *vpci) 36 { 37 return pci__bar_address(&vpci->pci_hdr, 2); 38 } 39 40 static void virtio_pci__ioevent_callback(struct kvm *kvm, void *param) 41 { 42 struct virtio_pci_ioevent_param *ioeventfd = param; 43 struct virtio_pci *vpci = ioeventfd->vdev->virtio; 44 45 ioeventfd->vdev->ops->notify_vq(kvm, vpci->dev, ioeventfd->vq); 46 } 47 48 static int virtio_pci__init_ioeventfd(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 49 { 50 struct ioevent ioevent; 51 struct virtio_pci *vpci = vdev->virtio; 52 u32 mmio_addr = virtio_pci__mmio_addr(vpci); 53 u16 port_addr = virtio_pci__port_addr(vpci); 54 int r, flags = 0; 55 int fd; 56 57 vpci->ioeventfds[vq] = (struct virtio_pci_ioevent_param) { 58 .vdev = vdev, 59 .vq = vq, 60 }; 61 62 ioevent = (struct ioevent) { 63 .fn = virtio_pci__ioevent_callback, 64 .fn_ptr = &vpci->ioeventfds[vq], 65 .datamatch = vq, 66 .fn_kvm = kvm, 67 }; 68 69 /* 70 * Vhost will poll the eventfd in host kernel side, otherwise we 71 * need to poll in userspace. 72 */ 73 if (!vdev->use_vhost) 74 flags |= IOEVENTFD_FLAG_USER_POLL; 75 76 /* ioport */ 77 ioevent.io_addr = port_addr + VIRTIO_PCI_QUEUE_NOTIFY; 78 ioevent.io_len = sizeof(u16); 79 ioevent.fd = fd = eventfd(0, 0); 80 r = ioeventfd__add_event(&ioevent, flags | IOEVENTFD_FLAG_PIO); 81 if (r) 82 return r; 83 84 /* mmio */ 85 ioevent.io_addr = mmio_addr + VIRTIO_PCI_QUEUE_NOTIFY; 86 ioevent.io_len = sizeof(u16); 87 ioevent.fd = eventfd(0, 0); 88 r = ioeventfd__add_event(&ioevent, flags); 89 if (r) 90 goto free_ioport_evt; 91 92 if (vdev->ops->notify_vq_eventfd) 93 vdev->ops->notify_vq_eventfd(kvm, vpci->dev, vq, fd); 94 return 0; 95 96 free_ioport_evt: 97 ioeventfd__del_event(port_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 98 return r; 99 } 100 101 static void virtio_pci_exit_vq(struct kvm *kvm, struct virtio_device *vdev, 102 int vq) 103 { 104 struct virtio_pci *vpci = vdev->virtio; 105 u32 mmio_addr = virtio_pci__mmio_addr(vpci); 106 u16 port_addr = virtio_pci__port_addr(vpci); 107 108 ioeventfd__del_event(mmio_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 109 ioeventfd__del_event(port_addr + VIRTIO_PCI_QUEUE_NOTIFY, vq); 110 virtio_exit_vq(kvm, vdev, vpci->dev, vq); 111 } 112 113 static inline bool virtio_pci__msix_enabled(struct virtio_pci *vpci) 114 { 115 return vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_ENABLE); 116 } 117 118 static bool virtio_pci__specific_data_in(struct kvm *kvm, struct virtio_device *vdev, 119 void *data, u32 size, unsigned long offset) 120 { 121 u32 config_offset; 122 struct virtio_pci *vpci = vdev->virtio; 123 int type = virtio__get_dev_specific_field(offset - 20, 124 virtio_pci__msix_enabled(vpci), 125 &config_offset); 126 if (type == VIRTIO_PCI_O_MSIX) { 127 switch (offset) { 128 case VIRTIO_MSI_CONFIG_VECTOR: 129 ioport__write16(data, vpci->config_vector); 130 break; 131 case VIRTIO_MSI_QUEUE_VECTOR: 132 ioport__write16(data, vpci->vq_vector[vpci->queue_selector]); 133 break; 134 }; 135 136 return true; 137 } else if (type == VIRTIO_PCI_O_CONFIG) { 138 return virtio_access_config(kvm, vdev, vpci->dev, config_offset, 139 data, size, false); 140 } 141 142 return false; 143 } 144 145 static bool virtio_pci__data_in(struct kvm_cpu *vcpu, struct virtio_device *vdev, 146 unsigned long offset, void *data, u32 size) 147 { 148 bool ret = true; 149 struct virtio_pci *vpci; 150 struct virt_queue *vq; 151 struct kvm *kvm; 152 u32 val; 153 154 kvm = vcpu->kvm; 155 vpci = vdev->virtio; 156 157 switch (offset) { 158 case VIRTIO_PCI_HOST_FEATURES: 159 val = vdev->ops->get_host_features(kvm, vpci->dev); 160 ioport__write32(data, val); 161 break; 162 case VIRTIO_PCI_QUEUE_PFN: 163 vq = vdev->ops->get_vq(kvm, vpci->dev, vpci->queue_selector); 164 ioport__write32(data, vq->vring_addr.pfn); 165 break; 166 case VIRTIO_PCI_QUEUE_NUM: 167 val = vdev->ops->get_size_vq(kvm, vpci->dev, vpci->queue_selector); 168 ioport__write16(data, val); 169 break; 170 case VIRTIO_PCI_STATUS: 171 ioport__write8(data, vpci->status); 172 break; 173 case VIRTIO_PCI_ISR: 174 ioport__write8(data, vpci->isr); 175 kvm__irq_line(kvm, vpci->legacy_irq_line, VIRTIO_IRQ_LOW); 176 vpci->isr = VIRTIO_IRQ_LOW; 177 break; 178 default: 179 ret = virtio_pci__specific_data_in(kvm, vdev, data, size, offset); 180 break; 181 }; 182 183 return ret; 184 } 185 186 static void update_msix_map(struct virtio_pci *vpci, 187 struct msix_table *msix_entry, u32 vecnum) 188 { 189 u32 gsi, i; 190 191 /* Find the GSI number used for that vector */ 192 if (vecnum == vpci->config_vector) { 193 gsi = vpci->config_gsi; 194 } else { 195 for (i = 0; i < VIRTIO_PCI_MAX_VQ; i++) 196 if (vpci->vq_vector[i] == vecnum) 197 break; 198 if (i == VIRTIO_PCI_MAX_VQ) 199 return; 200 gsi = vpci->gsis[i]; 201 } 202 203 if (gsi == 0) 204 return; 205 206 msix_entry = &msix_entry[vecnum]; 207 irq__update_msix_route(vpci->kvm, gsi, &msix_entry->msg); 208 } 209 210 static bool virtio_pci__specific_data_out(struct kvm *kvm, struct virtio_device *vdev, 211 void *data, u32 size, unsigned long offset) 212 { 213 struct virtio_pci *vpci = vdev->virtio; 214 u32 config_offset, vec; 215 int gsi; 216 int type = virtio__get_dev_specific_field(offset - 20, virtio_pci__msix_enabled(vpci), 217 &config_offset); 218 if (type == VIRTIO_PCI_O_MSIX) { 219 switch (offset) { 220 case VIRTIO_MSI_CONFIG_VECTOR: 221 vec = vpci->config_vector = ioport__read16(data); 222 if (vec == VIRTIO_MSI_NO_VECTOR) 223 break; 224 225 gsi = irq__add_msix_route(kvm, 226 &vpci->msix_table[vec].msg, 227 vpci->dev_hdr.dev_num << 3); 228 /* 229 * We don't need IRQ routing if we can use 230 * MSI injection via the KVM_SIGNAL_MSI ioctl. 231 */ 232 if (gsi == -ENXIO && 233 vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 234 break; 235 236 if (gsi < 0) { 237 die("failed to configure MSIs"); 238 break; 239 } 240 241 vpci->config_gsi = gsi; 242 break; 243 case VIRTIO_MSI_QUEUE_VECTOR: 244 vec = ioport__read16(data); 245 vpci->vq_vector[vpci->queue_selector] = vec; 246 247 if (vec == VIRTIO_MSI_NO_VECTOR) 248 break; 249 250 gsi = irq__add_msix_route(kvm, 251 &vpci->msix_table[vec].msg, 252 vpci->dev_hdr.dev_num << 3); 253 /* 254 * We don't need IRQ routing if we can use 255 * MSI injection via the KVM_SIGNAL_MSI ioctl. 256 */ 257 if (gsi == -ENXIO && 258 vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 259 break; 260 261 if (gsi < 0) { 262 die("failed to configure MSIs"); 263 break; 264 } 265 266 vpci->gsis[vpci->queue_selector] = gsi; 267 if (vdev->ops->notify_vq_gsi) 268 vdev->ops->notify_vq_gsi(kvm, vpci->dev, 269 vpci->queue_selector, 270 gsi); 271 break; 272 }; 273 274 return true; 275 } else if (type == VIRTIO_PCI_O_CONFIG) { 276 return virtio_access_config(kvm, vdev, vpci->dev, config_offset, 277 data, size, true); 278 } 279 280 return false; 281 } 282 283 static bool virtio_pci__data_out(struct kvm_cpu *vcpu, struct virtio_device *vdev, 284 unsigned long offset, void *data, u32 size) 285 { 286 bool ret = true; 287 struct virtio_pci *vpci; 288 struct virt_queue *vq; 289 struct kvm *kvm; 290 u32 val; 291 unsigned int vq_count; 292 293 kvm = vcpu->kvm; 294 vpci = vdev->virtio; 295 vq_count = vdev->ops->get_vq_count(kvm, vpci->dev); 296 297 switch (offset) { 298 case VIRTIO_PCI_GUEST_FEATURES: 299 val = ioport__read32(data); 300 virtio_set_guest_features(kvm, vdev, vpci->dev, val); 301 break; 302 case VIRTIO_PCI_QUEUE_PFN: 303 val = ioport__read32(data); 304 if (val) { 305 vq = vdev->ops->get_vq(kvm, vpci->dev, 306 vpci->queue_selector); 307 vq->vring_addr = (struct vring_addr) { 308 .legacy = true, 309 .pfn = val, 310 .align = VIRTIO_PCI_VRING_ALIGN, 311 .pgsize = 1 << VIRTIO_PCI_QUEUE_ADDR_SHIFT, 312 }; 313 virtio_pci__init_ioeventfd(kvm, vdev, 314 vpci->queue_selector); 315 vdev->ops->init_vq(kvm, vpci->dev, 316 vpci->queue_selector); 317 } else { 318 virtio_pci_exit_vq(kvm, vdev, vpci->queue_selector); 319 } 320 break; 321 case VIRTIO_PCI_QUEUE_SEL: 322 val = ioport__read16(data); 323 if (val >= vq_count) { 324 WARN_ONCE(1, "QUEUE_SEL value (%u) is larger than VQ count (%u)\n", 325 val, vq_count); 326 return false; 327 } 328 vpci->queue_selector = val; 329 break; 330 case VIRTIO_PCI_QUEUE_NOTIFY: 331 val = ioport__read16(data); 332 if (val >= vq_count) { 333 WARN_ONCE(1, "QUEUE_SEL value (%u) is larger than VQ count (%u)\n", 334 val, vq_count); 335 return false; 336 } 337 vdev->ops->notify_vq(kvm, vpci->dev, val); 338 break; 339 case VIRTIO_PCI_STATUS: 340 vpci->status = ioport__read8(data); 341 if (!vpci->status) /* Sample endianness on reset */ 342 vdev->endian = kvm_cpu__get_endianness(vcpu); 343 virtio_notify_status(kvm, vdev, vpci->dev, vpci->status); 344 break; 345 default: 346 ret = virtio_pci__specific_data_out(kvm, vdev, data, size, offset); 347 break; 348 }; 349 350 return ret; 351 } 352 353 static void virtio_pci__msix_mmio_callback(struct kvm_cpu *vcpu, 354 u64 addr, u8 *data, u32 len, 355 u8 is_write, void *ptr) 356 { 357 struct virtio_device *vdev = ptr; 358 struct virtio_pci *vpci = vdev->virtio; 359 struct msix_table *table; 360 u32 msix_io_addr = virtio_pci__msix_io_addr(vpci); 361 u32 pba_offset; 362 int vecnum; 363 size_t offset; 364 365 BUILD_BUG_ON(VIRTIO_NR_MSIX > (sizeof(vpci->msix_pba) * 8)); 366 367 pba_offset = vpci->pci_hdr.msix.pba_offset & ~PCI_MSIX_TABLE_BIR; 368 if (addr >= msix_io_addr + pba_offset) { 369 /* Read access to PBA */ 370 if (is_write) 371 return; 372 offset = addr - (msix_io_addr + pba_offset); 373 if ((offset + len) > sizeof (vpci->msix_pba)) 374 return; 375 memcpy(data, (void *)&vpci->msix_pba + offset, len); 376 return; 377 } 378 379 table = vpci->msix_table; 380 offset = addr - msix_io_addr; 381 382 vecnum = offset / sizeof(struct msix_table); 383 offset = offset % sizeof(struct msix_table); 384 385 if (!is_write) { 386 memcpy(data, (void *)&table[vecnum] + offset, len); 387 return; 388 } 389 390 memcpy((void *)&table[vecnum] + offset, data, len); 391 392 /* Did we just update the address or payload? */ 393 if (offset < offsetof(struct msix_table, ctrl)) 394 update_msix_map(vpci, table, vecnum); 395 } 396 397 static void virtio_pci__signal_msi(struct kvm *kvm, struct virtio_pci *vpci, 398 int vec) 399 { 400 struct kvm_msi msi = { 401 .address_lo = vpci->msix_table[vec].msg.address_lo, 402 .address_hi = vpci->msix_table[vec].msg.address_hi, 403 .data = vpci->msix_table[vec].msg.data, 404 }; 405 406 if (kvm->msix_needs_devid) { 407 msi.flags = KVM_MSI_VALID_DEVID; 408 msi.devid = vpci->dev_hdr.dev_num << 3; 409 } 410 411 irq__signal_msi(kvm, &msi); 412 } 413 414 int virtio_pci__signal_vq(struct kvm *kvm, struct virtio_device *vdev, u32 vq) 415 { 416 struct virtio_pci *vpci = vdev->virtio; 417 int tbl = vpci->vq_vector[vq]; 418 419 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 420 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 421 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 422 423 vpci->msix_pba |= 1 << tbl; 424 return 0; 425 } 426 427 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 428 virtio_pci__signal_msi(kvm, vpci, vpci->vq_vector[vq]); 429 else 430 kvm__irq_trigger(kvm, vpci->gsis[vq]); 431 } else { 432 vpci->isr = VIRTIO_IRQ_HIGH; 433 kvm__irq_line(kvm, vpci->legacy_irq_line, VIRTIO_IRQ_HIGH); 434 } 435 return 0; 436 } 437 438 int virtio_pci__signal_config(struct kvm *kvm, struct virtio_device *vdev) 439 { 440 struct virtio_pci *vpci = vdev->virtio; 441 int tbl = vpci->config_vector; 442 443 if (virtio_pci__msix_enabled(vpci) && tbl != VIRTIO_MSI_NO_VECTOR) { 444 if (vpci->pci_hdr.msix.ctrl & cpu_to_le16(PCI_MSIX_FLAGS_MASKALL) || 445 vpci->msix_table[tbl].ctrl & cpu_to_le16(PCI_MSIX_ENTRY_CTRL_MASKBIT)) { 446 447 vpci->msix_pba |= 1 << tbl; 448 return 0; 449 } 450 451 if (vpci->features & VIRTIO_PCI_F_SIGNAL_MSI) 452 virtio_pci__signal_msi(kvm, vpci, tbl); 453 else 454 kvm__irq_trigger(kvm, vpci->config_gsi); 455 } else { 456 vpci->isr = VIRTIO_PCI_ISR_CONFIG; 457 kvm__irq_trigger(kvm, vpci->legacy_irq_line); 458 } 459 460 return 0; 461 } 462 463 static void virtio_pci__io_mmio_callback(struct kvm_cpu *vcpu, 464 u64 addr, u8 *data, u32 len, 465 u8 is_write, void *ptr) 466 { 467 struct virtio_device *vdev = ptr; 468 struct virtio_pci *vpci = vdev->virtio; 469 u32 ioport_addr = virtio_pci__port_addr(vpci); 470 u32 base_addr; 471 472 if (addr >= ioport_addr && 473 addr < ioport_addr + pci__bar_size(&vpci->pci_hdr, 0)) 474 base_addr = ioport_addr; 475 else 476 base_addr = virtio_pci__mmio_addr(vpci); 477 478 if (!is_write) 479 virtio_pci__data_in(vcpu, vdev, addr - base_addr, data, len); 480 else 481 virtio_pci__data_out(vcpu, vdev, addr - base_addr, data, len); 482 } 483 484 static int virtio_pci__bar_activate(struct kvm *kvm, 485 struct pci_device_header *pci_hdr, 486 int bar_num, void *data) 487 { 488 struct virtio_device *vdev = data; 489 u32 bar_addr, bar_size; 490 int r = -EINVAL; 491 492 assert(bar_num <= 2); 493 494 bar_addr = pci__bar_address(pci_hdr, bar_num); 495 bar_size = pci__bar_size(pci_hdr, bar_num); 496 497 switch (bar_num) { 498 case 0: 499 r = kvm__register_pio(kvm, bar_addr, bar_size, 500 virtio_pci__io_mmio_callback, vdev); 501 break; 502 case 1: 503 r = kvm__register_mmio(kvm, bar_addr, bar_size, false, 504 virtio_pci__io_mmio_callback, vdev); 505 break; 506 case 2: 507 r = kvm__register_mmio(kvm, bar_addr, bar_size, false, 508 virtio_pci__msix_mmio_callback, vdev); 509 break; 510 } 511 512 return r; 513 } 514 515 static int virtio_pci__bar_deactivate(struct kvm *kvm, 516 struct pci_device_header *pci_hdr, 517 int bar_num, void *data) 518 { 519 u32 bar_addr; 520 bool success; 521 int r = -EINVAL; 522 523 assert(bar_num <= 2); 524 525 bar_addr = pci__bar_address(pci_hdr, bar_num); 526 527 switch (bar_num) { 528 case 0: 529 r = kvm__deregister_pio(kvm, bar_addr); 530 break; 531 case 1: 532 case 2: 533 success = kvm__deregister_mmio(kvm, bar_addr); 534 /* kvm__deregister_mmio fails when the region is not found. */ 535 r = (success ? 0 : -ENOENT); 536 break; 537 } 538 539 return r; 540 } 541 542 int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev, 543 int device_id, int subsys_id, int class) 544 { 545 struct virtio_pci *vpci = vdev->virtio; 546 u32 mmio_addr, msix_io_block; 547 u16 port_addr; 548 int r; 549 550 vpci->kvm = kvm; 551 vpci->dev = dev; 552 553 BUILD_BUG_ON(!is_power_of_two(PCI_IO_SIZE)); 554 555 port_addr = pci_get_io_port_block(PCI_IO_SIZE); 556 mmio_addr = pci_get_mmio_block(PCI_IO_SIZE); 557 msix_io_block = pci_get_mmio_block(VIRTIO_MSIX_BAR_SIZE); 558 559 vpci->pci_hdr = (struct pci_device_header) { 560 .vendor_id = cpu_to_le16(PCI_VENDOR_ID_REDHAT_QUMRANET), 561 .device_id = cpu_to_le16(device_id), 562 .command = PCI_COMMAND_IO | PCI_COMMAND_MEMORY, 563 .header_type = PCI_HEADER_TYPE_NORMAL, 564 .revision_id = 0, 565 .class[0] = class & 0xff, 566 .class[1] = (class >> 8) & 0xff, 567 .class[2] = (class >> 16) & 0xff, 568 .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), 569 .subsys_id = cpu_to_le16(subsys_id), 570 .bar[0] = cpu_to_le32(port_addr 571 | PCI_BASE_ADDRESS_SPACE_IO), 572 .bar[1] = cpu_to_le32(mmio_addr 573 | PCI_BASE_ADDRESS_SPACE_MEMORY), 574 .bar[2] = cpu_to_le32(msix_io_block 575 | PCI_BASE_ADDRESS_SPACE_MEMORY), 576 .status = cpu_to_le16(PCI_STATUS_CAP_LIST), 577 .capabilities = (void *)&vpci->pci_hdr.msix - (void *)&vpci->pci_hdr, 578 .bar_size[0] = cpu_to_le32(PCI_IO_SIZE), 579 .bar_size[1] = cpu_to_le32(PCI_IO_SIZE), 580 .bar_size[2] = cpu_to_le32(VIRTIO_MSIX_BAR_SIZE), 581 }; 582 583 r = pci__register_bar_regions(kvm, &vpci->pci_hdr, 584 virtio_pci__bar_activate, 585 virtio_pci__bar_deactivate, vdev); 586 if (r < 0) 587 return r; 588 589 vpci->dev_hdr = (struct device_header) { 590 .bus_type = DEVICE_BUS_PCI, 591 .data = &vpci->pci_hdr, 592 }; 593 594 vpci->pci_hdr.msix.cap = PCI_CAP_ID_MSIX; 595 vpci->pci_hdr.msix.next = 0; 596 /* 597 * We at most have VIRTIO_NR_MSIX entries (VIRTIO_PCI_MAX_VQ 598 * entries for virt queue, VIRTIO_PCI_MAX_CONFIG entries for 599 * config). 600 * 601 * To quote the PCI spec: 602 * 603 * System software reads this field to determine the 604 * MSI-X Table Size N, which is encoded as N-1. 605 * For example, a returned value of "00000000011" 606 * indicates a table size of 4. 607 */ 608 vpci->pci_hdr.msix.ctrl = cpu_to_le16(VIRTIO_NR_MSIX - 1); 609 610 /* Both table and PBA are mapped to the same BAR (2) */ 611 vpci->pci_hdr.msix.table_offset = cpu_to_le32(2); 612 vpci->pci_hdr.msix.pba_offset = cpu_to_le32(2 | VIRTIO_MSIX_TABLE_SIZE); 613 vpci->config_vector = 0; 614 615 if (irq__can_signal_msi(kvm)) 616 vpci->features |= VIRTIO_PCI_F_SIGNAL_MSI; 617 618 vpci->legacy_irq_line = pci__assign_irq(&vpci->pci_hdr); 619 620 r = device__register(&vpci->dev_hdr); 621 if (r < 0) 622 return r; 623 624 return 0; 625 } 626 627 int virtio_pci__reset(struct kvm *kvm, struct virtio_device *vdev) 628 { 629 unsigned int vq; 630 struct virtio_pci *vpci = vdev->virtio; 631 632 for (vq = 0; vq < vdev->ops->get_vq_count(kvm, vpci->dev); vq++) 633 virtio_pci_exit_vq(kvm, vdev, vq); 634 635 return 0; 636 } 637 638 int virtio_pci__exit(struct kvm *kvm, struct virtio_device *vdev) 639 { 640 struct virtio_pci *vpci = vdev->virtio; 641 642 virtio_pci__reset(kvm, vdev); 643 kvm__deregister_mmio(kvm, virtio_pci__mmio_addr(vpci)); 644 kvm__deregister_mmio(kvm, virtio_pci__msix_io_addr(vpci)); 645 kvm__deregister_pio(kvm, virtio_pci__port_addr(vpci)); 646 647 return 0; 648 } 649