1b30d05adSPekka Enberg #include "kvm/blk-virtio.h" 2b30d05adSPekka Enberg 3c435b91dSPekka Enberg #include "kvm/virtio_blk.h" 4984b7ae0SPekka Enberg #include "kvm/virtio_pci.h" 5b30d05adSPekka Enberg #include "kvm/ioport.h" 68b1ff07eSPekka Enberg #include "kvm/kvm.h" 7b30d05adSPekka Enberg #include "kvm/pci.h" 8b30d05adSPekka Enberg 98b1ff07eSPekka Enberg #define VIRTIO_BLK_IRQ 14 10984b7ae0SPekka Enberg 11fbc2fbf9SPekka Enberg struct device { 1240ce993fSPekka Enberg struct virtio_blk_config blk_config; 13c435b91dSPekka Enberg uint32_t host_features; 14fbc2fbf9SPekka Enberg uint32_t guest_features; 1540ce993fSPekka Enberg uint16_t config_vector; 16fbc2fbf9SPekka Enberg uint8_t status; 17fbc2fbf9SPekka Enberg }; 18fbc2fbf9SPekka Enberg 1940ce993fSPekka Enberg #define DISK_CYLINDERS 1024 2040ce993fSPekka Enberg #define DISK_HEADS 64 2140ce993fSPekka Enberg #define DISK_SECTORS 32 2240ce993fSPekka Enberg 23c435b91dSPekka Enberg static struct device device = { 2440ce993fSPekka Enberg .blk_config = (struct virtio_blk_config) { 2540ce993fSPekka Enberg .capacity = DISK_CYLINDERS * DISK_HEADS * DISK_SECTORS, 2640ce993fSPekka Enberg /* VIRTIO_BLK_F_GEOMETRY */ 2740ce993fSPekka Enberg .geometry = { 2840ce993fSPekka Enberg .cylinders = DISK_CYLINDERS, 2940ce993fSPekka Enberg .heads = DISK_HEADS, 3040ce993fSPekka Enberg .sectors = DISK_SECTORS, 3140ce993fSPekka Enberg }, 3240ce993fSPekka Enberg /* VIRTIO_BLK_SIZE */ 3340ce993fSPekka Enberg .blk_size = 4096, 3440ce993fSPekka Enberg }, 3598790f28SPekka Enberg .host_features = (1UL << VIRTIO_BLK_F_GEOMETRY) 36*cb938db9SPekka Enberg | (1UL << VIRTIO_BLK_F_RO) 37c435b91dSPekka Enberg | (1UL << VIRTIO_BLK_F_BLK_SIZE), 38c435b91dSPekka Enberg }; 39fbc2fbf9SPekka Enberg 4040ce993fSPekka Enberg static bool virtio_blk_config_in(void *data, unsigned long offset, int size, uint32_t count) 4140ce993fSPekka Enberg { 4240ce993fSPekka Enberg uint8_t *config_space = (uint8_t *) &device.blk_config; 4340ce993fSPekka Enberg 4440ce993fSPekka Enberg if (size != 1 || count != 1) 4540ce993fSPekka Enberg return false; 4640ce993fSPekka Enberg 4740ce993fSPekka Enberg ioport__write8(data, config_space[offset - VIRTIO_PCI_CONFIG_NOMSI]); 4840ce993fSPekka Enberg 4940ce993fSPekka Enberg return true; 5040ce993fSPekka Enberg } 5140ce993fSPekka Enberg 52fbc2fbf9SPekka Enberg static bool blk_virtio_in(struct kvm *self, uint16_t port, void *data, int size, uint32_t count) 53fbc2fbf9SPekka Enberg { 54fbc2fbf9SPekka Enberg unsigned long offset; 55fbc2fbf9SPekka Enberg 56fbc2fbf9SPekka Enberg offset = port - IOPORT_VIRTIO; 57fbc2fbf9SPekka Enberg 58fbc2fbf9SPekka Enberg switch (offset) { 59fbc2fbf9SPekka Enberg case VIRTIO_PCI_HOST_FEATURES: 60c435b91dSPekka Enberg ioport__write32(data, device.host_features); 61fbc2fbf9SPekka Enberg break; 62fbc2fbf9SPekka Enberg case VIRTIO_PCI_GUEST_FEATURES: 638b1ff07eSPekka Enberg return false; 64fbc2fbf9SPekka Enberg case VIRTIO_PCI_QUEUE_PFN: 658b1ff07eSPekka Enberg ioport__write32(data, 0x00); 668b1ff07eSPekka Enberg break; 67fbc2fbf9SPekka Enberg case VIRTIO_PCI_QUEUE_NUM: 688b1ff07eSPekka Enberg ioport__write16(data, 0x10); 698b1ff07eSPekka Enberg break; 70fbc2fbf9SPekka Enberg case VIRTIO_PCI_QUEUE_SEL: 71fbc2fbf9SPekka Enberg case VIRTIO_PCI_QUEUE_NOTIFY: 72fbc2fbf9SPekka Enberg return false; 73fbc2fbf9SPekka Enberg case VIRTIO_PCI_STATUS: 74fbc2fbf9SPekka Enberg ioport__write8(data, device.status); 75fbc2fbf9SPekka Enberg break; 76fbc2fbf9SPekka Enberg case VIRTIO_PCI_ISR: 778b1ff07eSPekka Enberg ioport__write8(data, 0x1); 788b1ff07eSPekka Enberg kvm__irq_line(self, VIRTIO_BLK_IRQ, 0); 797e61688eSPekka Enberg break; 80fbc2fbf9SPekka Enberg case VIRTIO_MSI_CONFIG_VECTOR: 8140ce993fSPekka Enberg ioport__write16(data, device.config_vector); 8240ce993fSPekka Enberg break; 83fbc2fbf9SPekka Enberg default: 8440ce993fSPekka Enberg return virtio_blk_config_in(data, offset, size, count); 85fbc2fbf9SPekka Enberg }; 86fbc2fbf9SPekka Enberg 87fbc2fbf9SPekka Enberg return true; 88fbc2fbf9SPekka Enberg } 89fbc2fbf9SPekka Enberg 90fbc2fbf9SPekka Enberg static bool blk_virtio_out(struct kvm *self, uint16_t port, void *data, int size, uint32_t count) 91fbc2fbf9SPekka Enberg { 92fbc2fbf9SPekka Enberg unsigned long offset; 93fbc2fbf9SPekka Enberg 94fbc2fbf9SPekka Enberg offset = port - IOPORT_VIRTIO; 95fbc2fbf9SPekka Enberg 96fbc2fbf9SPekka Enberg switch (offset) { 97fbc2fbf9SPekka Enberg case VIRTIO_PCI_GUEST_FEATURES: 98fbc2fbf9SPekka Enberg device.guest_features = ioport__read32(data); 99fbc2fbf9SPekka Enberg break; 100fbc2fbf9SPekka Enberg case VIRTIO_PCI_QUEUE_PFN: 1017e61688eSPekka Enberg break; 102fbc2fbf9SPekka Enberg case VIRTIO_PCI_QUEUE_SEL: 1037e61688eSPekka Enberg break; 1047e61688eSPekka Enberg case VIRTIO_PCI_QUEUE_NOTIFY: 1058b1ff07eSPekka Enberg kvm__irq_line(self, VIRTIO_BLK_IRQ, 1); 1067e61688eSPekka Enberg break; 107fbc2fbf9SPekka Enberg case VIRTIO_PCI_STATUS: 108fbc2fbf9SPekka Enberg device.status = ioport__read8(data); 109fbc2fbf9SPekka Enberg break; 110fbc2fbf9SPekka Enberg case VIRTIO_MSI_CONFIG_VECTOR: 11140ce993fSPekka Enberg device.config_vector = VIRTIO_MSI_NO_VECTOR; 11240ce993fSPekka Enberg break; 113fbc2fbf9SPekka Enberg case VIRTIO_MSI_QUEUE_VECTOR: 11440ce993fSPekka Enberg break; 115fbc2fbf9SPekka Enberg default: 116fbc2fbf9SPekka Enberg return false; 117fbc2fbf9SPekka Enberg }; 118fbc2fbf9SPekka Enberg 119fbc2fbf9SPekka Enberg return true; 120fbc2fbf9SPekka Enberg } 121fbc2fbf9SPekka Enberg 122fbc2fbf9SPekka Enberg static struct ioport_operations blk_virtio_io_ops = { 123fbc2fbf9SPekka Enberg .io_in = blk_virtio_in, 124fbc2fbf9SPekka Enberg .io_out = blk_virtio_out, 125fbc2fbf9SPekka Enberg }; 126fbc2fbf9SPekka Enberg 127b30d05adSPekka Enberg #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 128b30d05adSPekka Enberg #define PCI_DEVICE_ID_VIRTIO_BLK 0x1001 129b30d05adSPekka Enberg #define PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET 0x1af4 130b30d05adSPekka Enberg #define PCI_SUBSYSTEM_ID_VIRTIO_BLK 0x0002 131b30d05adSPekka Enberg 132fbc2fbf9SPekka Enberg static struct pci_device_header blk_virtio_pci_device = { 133b30d05adSPekka Enberg .vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET, 134b30d05adSPekka Enberg .device_id = PCI_DEVICE_ID_VIRTIO_BLK, 135b30d05adSPekka Enberg .header_type = PCI_HEADER_TYPE_NORMAL, 136b30d05adSPekka Enberg .revision_id = 0, 137b30d05adSPekka Enberg .class = 0x010000, 138b30d05adSPekka Enberg .subsys_vendor_id = PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET, 139b30d05adSPekka Enberg .subsys_id = PCI_SUBSYSTEM_ID_VIRTIO_BLK, 140b30d05adSPekka Enberg .bar[0] = IOPORT_VIRTIO | PCI_BASE_ADDRESS_SPACE_IO, 141dc53a427SPekka Enberg /* XXX: Is this IRQ setup OK? */ 142dc53a427SPekka Enberg .irq_pin = 1, 1438b1ff07eSPekka Enberg .irq_line = VIRTIO_BLK_IRQ, 144b30d05adSPekka Enberg }; 145b30d05adSPekka Enberg 146b30d05adSPekka Enberg void blk_virtio__init(void) 147b30d05adSPekka Enberg { 148fbc2fbf9SPekka Enberg pci__register(&blk_virtio_pci_device, 1); 149b30d05adSPekka Enberg 1508b1ff07eSPekka Enberg ioport__register(IOPORT_VIRTIO, &blk_virtio_io_ops, 256); 151b30d05adSPekka Enberg } 152