1721da166SAnup Patel /* SPDX-License-Identifier: GPL-2.0-only */ 2721da166SAnup Patel /* 3721da166SAnup Patel * Common SBI related defines and macros to be used by RISC-V kernel, 4721da166SAnup Patel * RISC-V KVM and userspace. 5721da166SAnup Patel * 6721da166SAnup Patel * Copyright (c) 2019 Western Digital Corporation or its affiliates. 7721da166SAnup Patel */ 8721da166SAnup Patel 9721da166SAnup Patel #ifndef __RISCV_SBI_H__ 10721da166SAnup Patel #define __RISCV_SBI_H__ 11721da166SAnup Patel 12721da166SAnup Patel enum sbi_ext_id { 13721da166SAnup Patel SBI_EXT_0_1_SET_TIMER = 0x0, 14721da166SAnup Patel SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1, 15721da166SAnup Patel SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2, 16721da166SAnup Patel SBI_EXT_0_1_CLEAR_IPI = 0x3, 17721da166SAnup Patel SBI_EXT_0_1_SEND_IPI = 0x4, 18721da166SAnup Patel SBI_EXT_0_1_REMOTE_FENCE_I = 0x5, 19721da166SAnup Patel SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6, 20721da166SAnup Patel SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, 21721da166SAnup Patel SBI_EXT_0_1_SHUTDOWN = 0x8, 22721da166SAnup Patel SBI_EXT_BASE = 0x10, 23*4ddaa424SAnup Patel SBI_EXT_DBCN = 0x4442434E, 24721da166SAnup Patel }; 25721da166SAnup Patel 26721da166SAnup Patel enum sbi_ext_base_fid { 27721da166SAnup Patel SBI_BASE_GET_SPEC_VERSION = 0, 28721da166SAnup Patel SBI_BASE_GET_IMP_ID, 29721da166SAnup Patel SBI_BASE_GET_IMP_VERSION, 30721da166SAnup Patel SBI_BASE_PROBE_EXT, 31721da166SAnup Patel SBI_BASE_GET_MVENDORID, 32721da166SAnup Patel SBI_BASE_GET_MARCHID, 33721da166SAnup Patel SBI_BASE_GET_MIMPID, 34721da166SAnup Patel }; 35721da166SAnup Patel 36*4ddaa424SAnup Patel enum sbi_ext_dbcn_fid { 37*4ddaa424SAnup Patel SBI_EXT_DBCN_CONSOLE_WRITE = 0, 38*4ddaa424SAnup Patel SBI_EXT_DBCN_CONSOLE_READ = 1, 39*4ddaa424SAnup Patel SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, 40*4ddaa424SAnup Patel }; 41*4ddaa424SAnup Patel 42721da166SAnup Patel #define SBI_SPEC_VERSION_DEFAULT 0x1 43721da166SAnup Patel #define SBI_SPEC_VERSION_MAJOR_OFFSET 24 44721da166SAnup Patel #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f 45721da166SAnup Patel #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff 46721da166SAnup Patel 47721da166SAnup Patel /* SBI return error codes */ 48721da166SAnup Patel #define SBI_SUCCESS 0 49721da166SAnup Patel #define SBI_ERR_FAILURE -1 50721da166SAnup Patel #define SBI_ERR_NOT_SUPPORTED -2 51721da166SAnup Patel #define SBI_ERR_INVALID_PARAM -3 52721da166SAnup Patel #define SBI_ERR_DENIED -4 53721da166SAnup Patel #define SBI_ERR_INVALID_ADDRESS -5 54*4ddaa424SAnup Patel #define SBI_ERR_ALREADY_AVAILABLE -6 55*4ddaa424SAnup Patel #define SBI_ERR_ALREADY_STARTED -7 56*4ddaa424SAnup Patel #define SBI_ERR_ALREADY_STOPPED -8 57721da166SAnup Patel 58721da166SAnup Patel #endif 59