1*31638bcaSCyrill Gorcunov #ifndef VIRTIO_PCI_DEV_H_ 2*31638bcaSCyrill Gorcunov #define VIRTIO_PCI_DEV_H_ 3*31638bcaSCyrill Gorcunov 4*31638bcaSCyrill Gorcunov /* 5*31638bcaSCyrill Gorcunov * Virtio PCI device constants and resources 6*31638bcaSCyrill Gorcunov * they do use (such as irqs and pins). 7*31638bcaSCyrill Gorcunov */ 8*31638bcaSCyrill Gorcunov 9*31638bcaSCyrill Gorcunov #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 10*31638bcaSCyrill Gorcunov #define PCI_DEVICE_ID_VIRTIO_BLK 0x1001 11*31638bcaSCyrill Gorcunov #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 12*31638bcaSCyrill Gorcunov #define PCI_DEVICE_ID_VIRTIO_RNG 0x1004 13*31638bcaSCyrill Gorcunov 14*31638bcaSCyrill Gorcunov #define PCI_SUBSYSTEM_ID_VIRTIO_NET 0x0001 15*31638bcaSCyrill Gorcunov #define PCI_SUBSYSTEM_ID_VIRTIO_BLK 0x0002 16*31638bcaSCyrill Gorcunov #define PCI_SUBSYSTEM_ID_VIRTIO_CONSOLE 0x0003 17*31638bcaSCyrill Gorcunov #define PCI_SUBSYSTEM_ID_VIRTIO_RNG 0x0004 18*31638bcaSCyrill Gorcunov 19*31638bcaSCyrill Gorcunov enum { 20*31638bcaSCyrill Gorcunov PCI_VIRTIO_BLK_DEVNUM = 10, 21*31638bcaSCyrill Gorcunov PCI_VIRTIO_CONSOLE_DEVNUM = 2, 22*31638bcaSCyrill Gorcunov PCI_VIRTIO_NET_DEVNUM = 3, 23*31638bcaSCyrill Gorcunov PCI_VIRTIO_RNG_DEVNUM = 4, 24*31638bcaSCyrill Gorcunov }; 25*31638bcaSCyrill Gorcunov 26*31638bcaSCyrill Gorcunov enum { 27*31638bcaSCyrill Gorcunov VIRTIO_BLK_PIN = 1, 28*31638bcaSCyrill Gorcunov VIRTIO_CONSOLE_PIN = 2, 29*31638bcaSCyrill Gorcunov VIRTIO_NET_PIN = 3, 30*31638bcaSCyrill Gorcunov VIRTIO_RNG_PIN = 4, 31*31638bcaSCyrill Gorcunov }; 32*31638bcaSCyrill Gorcunov 33*31638bcaSCyrill Gorcunov enum { 34*31638bcaSCyrill Gorcunov VIRTIO_RNG_IRQ = 11, 35*31638bcaSCyrill Gorcunov VIRTIO_CONSOLE_IRQ = 13, 36*31638bcaSCyrill Gorcunov VIRTIO_NET_IRQ = 14, 37*31638bcaSCyrill Gorcunov VIRTIO_BLK_IRQ = 15, 38*31638bcaSCyrill Gorcunov }; 39*31638bcaSCyrill Gorcunov 40*31638bcaSCyrill Gorcunov #endif /* VIRTIO_PCI_DEV_H_ */ 41