160742802SPekka Enberg #ifndef KVM__PCI_H 260742802SPekka Enberg #define KVM__PCI_H 360742802SPekka Enberg 43fdf659dSSasha Levin #include <linux/types.h> 51de74957SSasha Levin #include <linux/kvm.h> 620c64ecaSPekka Enberg #include <linux/pci_regs.h> 71de74957SSasha Levin #include <linux/msi.h> 876f9c841SCyrill Gorcunov 9*9d755a36SMatt Evans #define PCI_MAX_DEVICES 256 104402a581SPekka Enberg /* 114402a581SPekka Enberg * PCI Configuration Mechanism #1 I/O ports. See Section 3.7.4.1. 124402a581SPekka Enberg * ("Configuration Mechanism #1") of the PCI Local Bus Specification 2.1 for 134402a581SPekka Enberg * details. 144402a581SPekka Enberg */ 15305b72ceSCyrill Gorcunov #define PCI_CONFIG_ADDRESS 0xcf8 16305b72ceSCyrill Gorcunov #define PCI_CONFIG_DATA 0xcfc 172b9e4709SCyrill Gorcunov #define PCI_CONFIG_BUS_FORWARD 0xcfa 1895d13a52SSasha Levin #define PCI_IO_SIZE 0x100 19305b72ceSCyrill Gorcunov 204402a581SPekka Enberg struct pci_config_address { 214402a581SPekka Enberg unsigned zeros : 2; /* 1 .. 0 */ 224402a581SPekka Enberg unsigned register_number : 6; /* 7 .. 2 */ 234402a581SPekka Enberg unsigned function_number : 3; /* 10 .. 8 */ 244402a581SPekka Enberg unsigned device_number : 5; /* 15 .. 11 */ 254402a581SPekka Enberg unsigned bus_number : 8; /* 23 .. 16 */ 264402a581SPekka Enberg unsigned reserved : 7; /* 30 .. 24 */ 274402a581SPekka Enberg unsigned enable_bit : 1; /* 31 */ 284402a581SPekka Enberg }; 294402a581SPekka Enberg 30bc485053SSasha Levin struct msix_table { 311de74957SSasha Levin struct msi_msg msg; 32bc485053SSasha Levin u32 ctrl; 33bc485053SSasha Levin }; 34bc485053SSasha Levin 35bc485053SSasha Levin struct msix_cap { 36bc485053SSasha Levin u8 cap; 37bc485053SSasha Levin u8 next; 3806f48103SSasha Levin u16 ctrl; 39bc485053SSasha Levin u32 table_offset; 4006f48103SSasha Levin u32 pba_offset; 41bc485053SSasha Levin }; 42bc485053SSasha Levin 4376f9c841SCyrill Gorcunov struct pci_device_header { 443fdf659dSSasha Levin u16 vendor_id; 453fdf659dSSasha Levin u16 device_id; 463fdf659dSSasha Levin u16 command; 473fdf659dSSasha Levin u16 status; 483fdf659dSSasha Levin u16 revision_id : 8; 493fdf659dSSasha Levin u32 class : 24; 503fdf659dSSasha Levin u8 cacheline_size; 513fdf659dSSasha Levin u8 latency_timer; 523fdf659dSSasha Levin u8 header_type; 533fdf659dSSasha Levin u8 bist; 543fdf659dSSasha Levin u32 bar[6]; 553fdf659dSSasha Levin u32 card_bus; 563fdf659dSSasha Levin u16 subsys_vendor_id; 573fdf659dSSasha Levin u16 subsys_id; 583fdf659dSSasha Levin u32 exp_rom_bar; 593fdf659dSSasha Levin u32 capabilities : 8; 603fdf659dSSasha Levin u32 reserved1 : 24; 613fdf659dSSasha Levin u32 reserved2; 623fdf659dSSasha Levin u8 irq_line; 633fdf659dSSasha Levin u8 irq_pin; 643fdf659dSSasha Levin u8 min_gnt; 653fdf659dSSasha Levin u8 max_lat; 66bc485053SSasha Levin struct msix_cap msix; 67c64f7ff0SSasha Levin u8 empty[136]; /* Rest of PCI config space */ 68c64f7ff0SSasha Levin u32 bar_size[6]; 6976f9c841SCyrill Gorcunov }; 7076f9c841SCyrill Gorcunov 7160742802SPekka Enberg void pci__init(void); 723fdf659dSSasha Levin void pci__register(struct pci_device_header *dev, u8 dev_num); 7395d13a52SSasha Levin u32 pci_get_io_space_block(u32 size); 7460742802SPekka Enberg 7560742802SPekka Enberg #endif /* KVM__PCI_H */ 76