1 #include "kvm/devices.h" 2 #include "kvm/fdt.h" 3 #include "kvm/of_pci.h" 4 #include "kvm/pci.h" 5 #include "kvm/util.h" 6 7 #include "arm-common/pci.h" 8 9 /* 10 * An entry in the interrupt-map table looks like: 11 * <pci unit address> <pci interrupt pin> <gic phandle> <gic interrupt> 12 */ 13 14 struct of_gic_irq { 15 u32 type, num, flags; 16 } __attribute__((packed)); 17 18 struct of_interrupt_map_entry { 19 struct of_pci_irq_mask pci_irq_mask; 20 u32 gic_phandle; 21 struct of_gic_irq gic_irq; 22 } __attribute__((packed)); 23 24 void pci__generate_fdt_nodes(void *fdt, u32 gic_phandle) 25 { 26 struct device_header *dev_hdr; 27 struct of_interrupt_map_entry irq_map[OF_PCI_IRQ_MAP_MAX]; 28 unsigned nentries = 0; 29 /* Bus range */ 30 u32 bus_range[] = { cpu_to_fdt32(0), cpu_to_fdt32(1), }; 31 /* Configuration Space */ 32 u64 cfg_reg_prop[] = { cpu_to_fdt64(KVM_PCI_CFG_AREA), 33 cpu_to_fdt64(ARM_PCI_CFG_SIZE), }; 34 /* Describe the memory ranges */ 35 struct of_pci_ranges_entry ranges[] = { 36 { 37 .pci_addr = { 38 .hi = cpu_to_fdt32(of_pci_b_ss(OF_PCI_SS_IO)), 39 .mid = 0, 40 .lo = 0, 41 }, 42 .cpu_addr = cpu_to_fdt64(KVM_IOPORT_AREA), 43 .length = cpu_to_fdt64(ARM_IOPORT_SIZE), 44 }, 45 { 46 .pci_addr = { 47 .hi = cpu_to_fdt32(of_pci_b_ss(OF_PCI_SS_M32)), 48 .mid = cpu_to_fdt32(KVM_PCI_MMIO_AREA >> 32), 49 .lo = cpu_to_fdt32(KVM_PCI_MMIO_AREA), 50 }, 51 .cpu_addr = cpu_to_fdt64(KVM_PCI_MMIO_AREA), 52 .length = cpu_to_fdt64(ARM_PCI_MMIO_SIZE), 53 }, 54 }; 55 56 /* Boilerplate PCI properties */ 57 _FDT(fdt_begin_node(fdt, "pci")); 58 _FDT(fdt_property_string(fdt, "device_type", "pci")); 59 _FDT(fdt_property_cell(fdt, "#address-cells", 0x3)); 60 _FDT(fdt_property_cell(fdt, "#size-cells", 0x2)); 61 _FDT(fdt_property_cell(fdt, "#interrupt-cells", 0x1)); 62 _FDT(fdt_property_string(fdt, "compatible", "pci-host-cam-generic")); 63 64 _FDT(fdt_property(fdt, "bus-range", bus_range, sizeof(bus_range))); 65 _FDT(fdt_property(fdt, "reg", &cfg_reg_prop, sizeof(cfg_reg_prop))); 66 _FDT(fdt_property(fdt, "ranges", ranges, sizeof(ranges))); 67 68 /* Generate the interrupt map ... */ 69 dev_hdr = device__first_dev(DEVICE_BUS_PCI); 70 while (dev_hdr && nentries < ARRAY_SIZE(irq_map)) { 71 struct of_interrupt_map_entry *entry = &irq_map[nentries]; 72 struct pci_device_header *pci_hdr = dev_hdr->data; 73 u8 dev_num = dev_hdr->dev_num; 74 u8 pin = pci_hdr->irq_pin; 75 u8 irq = pci_hdr->irq_line; 76 77 *entry = (struct of_interrupt_map_entry) { 78 .pci_irq_mask = { 79 .pci_addr = { 80 .hi = cpu_to_fdt32(of_pci_b_ddddd(dev_num)), 81 .mid = 0, 82 .lo = 0, 83 }, 84 .pci_pin = cpu_to_fdt32(pin), 85 }, 86 .gic_phandle = cpu_to_fdt32(gic_phandle), 87 .gic_irq = { 88 .type = cpu_to_fdt32(GIC_FDT_IRQ_TYPE_SPI), 89 .num = cpu_to_fdt32(irq - GIC_SPI_IRQ_BASE), 90 .flags = cpu_to_fdt32(GIC_FDT_IRQ_FLAGS_EDGE_LO_HI), 91 }, 92 }; 93 94 nentries++; 95 dev_hdr = device__next_dev(dev_hdr); 96 } 97 98 _FDT(fdt_property(fdt, "interrupt-map", irq_map, 99 sizeof(struct of_interrupt_map_entry) * nentries)); 100 101 /* ... and the corresponding mask. */ 102 if (nentries) { 103 struct of_pci_irq_mask irq_mask = { 104 .pci_addr = { 105 .hi = cpu_to_fdt32(of_pci_b_ddddd(-1)), 106 .mid = 0, 107 .lo = 0, 108 }, 109 .pci_pin = cpu_to_fdt32(7), 110 }; 111 112 _FDT(fdt_property(fdt, "interrupt-map-mask", &irq_mask, 113 sizeof(irq_mask))); 114 } 115 116 _FDT(fdt_end_node(fdt)); 117 } 118