1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 25 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 26 27 u64 ia32_pat; 28 u64 ia32_efer; 29 void *io_bitmap_a, *io_bitmap_b; 30 u16 ioport; 31 32 unsigned long *pml4; 33 u64 eptp; 34 void *data_page1, *data_page2; 35 36 phys_addr_t pci_physaddr; 37 38 void *pml_log; 39 #define PML_INDEX 512 40 41 static inline unsigned ffs(unsigned x) 42 { 43 int pos = -1; 44 45 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 46 : "+r"(pos) : "rm"(x) : "eax"); 47 return pos + 1; 48 } 49 50 static inline void vmcall(void) 51 { 52 asm volatile("vmcall"); 53 } 54 55 static void basic_guest_main(void) 56 { 57 report_pass("Basic VMX test"); 58 } 59 60 static int basic_exit_handler(union exit_reason exit_reason) 61 { 62 report_fail("Basic VMX test"); 63 print_vmexit_info(exit_reason); 64 return VMX_TEST_EXIT; 65 } 66 67 static void vmenter_main(void) 68 { 69 u64 rax; 70 u64 rsp, resume_rsp; 71 72 report_pass("test vmlaunch"); 73 74 asm volatile( 75 "mov %%rsp, %0\n\t" 76 "mov %3, %%rax\n\t" 77 "vmcall\n\t" 78 "mov %%rax, %1\n\t" 79 "mov %%rsp, %2\n\t" 80 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 81 : "g"(0xABCD)); 82 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 83 } 84 85 static int vmenter_exit_handler(union exit_reason exit_reason) 86 { 87 u64 guest_rip = vmcs_read(GUEST_RIP); 88 89 switch (exit_reason.basic) { 90 case VMX_VMCALL: 91 if (regs.rax != 0xABCD) { 92 report_fail("test vmresume"); 93 return VMX_TEST_VMEXIT; 94 } 95 regs.rax = 0xFFFF; 96 vmcs_write(GUEST_RIP, guest_rip + 3); 97 return VMX_TEST_RESUME; 98 default: 99 report_fail("test vmresume"); 100 print_vmexit_info(exit_reason); 101 } 102 return VMX_TEST_VMEXIT; 103 } 104 105 u32 preempt_scale; 106 volatile unsigned long long tsc_val; 107 volatile u32 preempt_val; 108 u64 saved_rip; 109 110 static int preemption_timer_init(struct vmcs *vmcs) 111 { 112 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 113 printf("\tPreemption timer is not supported\n"); 114 return VMX_TEST_EXIT; 115 } 116 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 117 preempt_val = 10000000; 118 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 119 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 120 121 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 122 printf("\tSave preemption value is not supported\n"); 123 124 return VMX_TEST_START; 125 } 126 127 static void preemption_timer_main(void) 128 { 129 tsc_val = rdtsc(); 130 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 131 vmx_set_test_stage(0); 132 vmcall(); 133 if (vmx_get_test_stage() == 1) 134 vmcall(); 135 } 136 vmx_set_test_stage(1); 137 while (vmx_get_test_stage() == 1) { 138 if (((rdtsc() - tsc_val) >> preempt_scale) 139 > 10 * preempt_val) { 140 vmx_set_test_stage(2); 141 vmcall(); 142 } 143 } 144 tsc_val = rdtsc(); 145 asm volatile ("hlt"); 146 vmcall(); 147 vmx_set_test_stage(5); 148 vmcall(); 149 } 150 151 static int preemption_timer_exit_handler(union exit_reason exit_reason) 152 { 153 bool guest_halted; 154 u64 guest_rip; 155 u32 insn_len; 156 u32 ctrl_exit; 157 158 guest_rip = vmcs_read(GUEST_RIP); 159 insn_len = vmcs_read(EXI_INST_LEN); 160 switch (exit_reason.basic) { 161 case VMX_PREEMPT: 162 switch (vmx_get_test_stage()) { 163 case 1: 164 case 2: 165 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 166 "busy-wait for preemption timer"); 167 vmx_set_test_stage(3); 168 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 169 return VMX_TEST_RESUME; 170 case 3: 171 guest_halted = 172 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 174 && guest_halted, 175 "preemption timer during hlt"); 176 vmx_set_test_stage(4); 177 vmcs_write(PIN_CONTROLS, 178 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 179 vmcs_write(EXI_CONTROLS, 180 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 181 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 182 return VMX_TEST_RESUME; 183 case 4: 184 report(saved_rip == guest_rip, 185 "preemption timer with 0 value"); 186 break; 187 default: 188 report_fail("Invalid stage."); 189 print_vmexit_info(exit_reason); 190 break; 191 } 192 break; 193 case VMX_VMCALL: 194 vmcs_write(GUEST_RIP, guest_rip + insn_len); 195 switch (vmx_get_test_stage()) { 196 case 0: 197 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 198 "Keep preemption value"); 199 vmx_set_test_stage(1); 200 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 201 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 202 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 203 vmcs_write(EXI_CONTROLS, ctrl_exit); 204 return VMX_TEST_RESUME; 205 case 1: 206 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 207 "Save preemption value"); 208 return VMX_TEST_RESUME; 209 case 2: 210 report_fail("busy-wait for preemption timer"); 211 vmx_set_test_stage(3); 212 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 213 return VMX_TEST_RESUME; 214 case 3: 215 report_fail("preemption timer during hlt"); 216 vmx_set_test_stage(4); 217 /* fall through */ 218 case 4: 219 vmcs_write(PIN_CONTROLS, 220 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 221 vmcs_write(PREEMPT_TIMER_VALUE, 0); 222 saved_rip = guest_rip + insn_len; 223 return VMX_TEST_RESUME; 224 case 5: 225 report_fail("preemption timer with 0 value (vmcall stage 5)"); 226 break; 227 default: 228 // Should not reach here 229 report_fail("unexpected stage, %d", 230 vmx_get_test_stage()); 231 print_vmexit_info(exit_reason); 232 return VMX_TEST_VMEXIT; 233 } 234 break; 235 default: 236 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 237 print_vmexit_info(exit_reason); 238 } 239 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 240 return VMX_TEST_VMEXIT; 241 } 242 243 static void msr_bmp_init(void) 244 { 245 void *msr_bitmap; 246 u32 ctrl_cpu0; 247 248 msr_bitmap = alloc_page(); 249 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 250 ctrl_cpu0 |= CPU_MSR_BITMAP; 251 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 252 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 253 } 254 255 static void *get_msr_bitmap(void) 256 { 257 void *msr_bitmap; 258 259 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 260 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 261 } else { 262 msr_bitmap = alloc_page(); 263 memset(msr_bitmap, 0xff, PAGE_SIZE); 264 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 265 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 266 } 267 268 return msr_bitmap; 269 } 270 271 static void disable_intercept_for_x2apic_msrs(void) 272 { 273 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 274 u32 msr; 275 276 for (msr = APIC_BASE_MSR; 277 msr < (APIC_BASE_MSR+0xff); 278 msr += BITS_PER_LONG) { 279 unsigned int word = msr / BITS_PER_LONG; 280 281 msr_bitmap[word] = 0; 282 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 283 } 284 } 285 286 static int test_ctrl_pat_init(struct vmcs *vmcs) 287 { 288 u64 ctrl_ent; 289 u64 ctrl_exi; 290 291 msr_bmp_init(); 292 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 293 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 294 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 295 printf("\tSave/load PAT is not supported\n"); 296 return 1; 297 } 298 299 ctrl_ent = vmcs_read(ENT_CONTROLS); 300 ctrl_exi = vmcs_read(EXI_CONTROLS); 301 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 302 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 303 vmcs_write(ENT_CONTROLS, ctrl_ent); 304 vmcs_write(EXI_CONTROLS, ctrl_exi); 305 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 306 vmcs_write(GUEST_PAT, 0x0); 307 vmcs_write(HOST_PAT, ia32_pat); 308 return VMX_TEST_START; 309 } 310 311 static void test_ctrl_pat_main(void) 312 { 313 u64 guest_ia32_pat; 314 315 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 316 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 317 printf("\tENT_LOAD_PAT is not supported.\n"); 318 else { 319 if (guest_ia32_pat != 0) { 320 report_fail("Entry load PAT"); 321 return; 322 } 323 } 324 wrmsr(MSR_IA32_CR_PAT, 0x6); 325 vmcall(); 326 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 327 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 328 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 329 } 330 331 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 332 { 333 u64 guest_rip; 334 u64 guest_pat; 335 336 guest_rip = vmcs_read(GUEST_RIP); 337 switch (exit_reason.basic) { 338 case VMX_VMCALL: 339 guest_pat = vmcs_read(GUEST_PAT); 340 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 341 printf("\tEXI_SAVE_PAT is not supported\n"); 342 vmcs_write(GUEST_PAT, 0x6); 343 } else { 344 report(guest_pat == 0x6, "Exit save PAT"); 345 } 346 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 347 printf("\tEXI_LOAD_PAT is not supported\n"); 348 else 349 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 350 "Exit load PAT"); 351 vmcs_write(GUEST_PAT, ia32_pat); 352 vmcs_write(GUEST_RIP, guest_rip + 3); 353 return VMX_TEST_RESUME; 354 default: 355 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 356 break; 357 } 358 return VMX_TEST_VMEXIT; 359 } 360 361 static int test_ctrl_efer_init(struct vmcs *vmcs) 362 { 363 u64 ctrl_ent; 364 u64 ctrl_exi; 365 366 msr_bmp_init(); 367 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 368 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 369 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 370 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 371 ia32_efer = rdmsr(MSR_EFER); 372 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 373 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 374 return VMX_TEST_START; 375 } 376 377 static void test_ctrl_efer_main(void) 378 { 379 u64 guest_ia32_efer; 380 381 guest_ia32_efer = rdmsr(MSR_EFER); 382 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 383 printf("\tENT_LOAD_EFER is not supported.\n"); 384 else { 385 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 386 report_fail("Entry load EFER"); 387 return; 388 } 389 } 390 wrmsr(MSR_EFER, ia32_efer); 391 vmcall(); 392 guest_ia32_efer = rdmsr(MSR_EFER); 393 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 394 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 395 } 396 397 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 398 { 399 u64 guest_rip; 400 u64 guest_efer; 401 402 guest_rip = vmcs_read(GUEST_RIP); 403 switch (exit_reason.basic) { 404 case VMX_VMCALL: 405 guest_efer = vmcs_read(GUEST_EFER); 406 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 407 printf("\tEXI_SAVE_EFER is not supported\n"); 408 vmcs_write(GUEST_EFER, ia32_efer); 409 } else { 410 report(guest_efer == ia32_efer, "Exit save EFER"); 411 } 412 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 413 printf("\tEXI_LOAD_EFER is not supported\n"); 414 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 415 } else { 416 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 417 "Exit load EFER"); 418 } 419 vmcs_write(GUEST_PAT, ia32_efer); 420 vmcs_write(GUEST_RIP, guest_rip + 3); 421 return VMX_TEST_RESUME; 422 default: 423 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 424 break; 425 } 426 return VMX_TEST_VMEXIT; 427 } 428 429 u32 guest_cr0, guest_cr4; 430 431 static void cr_shadowing_main(void) 432 { 433 u32 cr0, cr4, tmp; 434 435 // Test read through 436 vmx_set_test_stage(0); 437 guest_cr0 = read_cr0(); 438 if (vmx_get_test_stage() == 1) 439 report_fail("Read through CR0"); 440 else 441 vmcall(); 442 vmx_set_test_stage(1); 443 guest_cr4 = read_cr4(); 444 if (vmx_get_test_stage() == 2) 445 report_fail("Read through CR4"); 446 else 447 vmcall(); 448 // Test write through 449 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 450 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 451 vmx_set_test_stage(2); 452 write_cr0(guest_cr0); 453 if (vmx_get_test_stage() == 3) 454 report_fail("Write throuth CR0"); 455 else 456 vmcall(); 457 vmx_set_test_stage(3); 458 write_cr4(guest_cr4); 459 if (vmx_get_test_stage() == 4) 460 report_fail("Write through CR4"); 461 else 462 vmcall(); 463 // Test read shadow 464 vmx_set_test_stage(4); 465 vmcall(); 466 cr0 = read_cr0(); 467 if (vmx_get_test_stage() != 5) 468 report(cr0 == guest_cr0, "Read shadowing CR0"); 469 vmx_set_test_stage(5); 470 cr4 = read_cr4(); 471 if (vmx_get_test_stage() != 6) 472 report(cr4 == guest_cr4, "Read shadowing CR4"); 473 // Test write shadow (same value with shadow) 474 vmx_set_test_stage(6); 475 write_cr0(guest_cr0); 476 if (vmx_get_test_stage() == 7) 477 report_fail("Write shadowing CR0 (same value with shadow)"); 478 else 479 vmcall(); 480 vmx_set_test_stage(7); 481 write_cr4(guest_cr4); 482 if (vmx_get_test_stage() == 8) 483 report_fail("Write shadowing CR4 (same value with shadow)"); 484 else 485 vmcall(); 486 // Test write shadow (different value) 487 vmx_set_test_stage(8); 488 tmp = guest_cr0 ^ X86_CR0_TS; 489 asm volatile("mov %0, %%rsi\n\t" 490 "mov %%rsi, %%cr0\n\t" 491 ::"m"(tmp) 492 :"rsi", "memory", "cc"); 493 report(vmx_get_test_stage() == 9, 494 "Write shadowing different X86_CR0_TS"); 495 vmx_set_test_stage(9); 496 tmp = guest_cr0 ^ X86_CR0_MP; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 10, 502 "Write shadowing different X86_CR0_MP"); 503 vmx_set_test_stage(10); 504 tmp = guest_cr4 ^ X86_CR4_TSD; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr4\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 11, 510 "Write shadowing different X86_CR4_TSD"); 511 vmx_set_test_stage(11); 512 tmp = guest_cr4 ^ X86_CR4_DE; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 12, 518 "Write shadowing different X86_CR4_DE"); 519 } 520 521 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 522 { 523 u64 guest_rip; 524 u32 insn_len; 525 u32 exit_qual; 526 527 guest_rip = vmcs_read(GUEST_RIP); 528 insn_len = vmcs_read(EXI_INST_LEN); 529 exit_qual = vmcs_read(EXI_QUALIFICATION); 530 switch (exit_reason.basic) { 531 case VMX_VMCALL: 532 switch (vmx_get_test_stage()) { 533 case 0: 534 report(guest_cr0 == vmcs_read(GUEST_CR0), 535 "Read through CR0"); 536 break; 537 case 1: 538 report(guest_cr4 == vmcs_read(GUEST_CR4), 539 "Read through CR4"); 540 break; 541 case 2: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Write through CR0"); 544 break; 545 case 3: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Write through CR4"); 548 break; 549 case 4: 550 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 551 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 552 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 553 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 554 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 556 break; 557 case 6: 558 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 559 "Write shadowing CR0 (same value)"); 560 break; 561 case 7: 562 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 563 "Write shadowing CR4 (same value)"); 564 break; 565 default: 566 // Should not reach here 567 report_fail("unexpected stage, %d", 568 vmx_get_test_stage()); 569 print_vmexit_info(exit_reason); 570 return VMX_TEST_VMEXIT; 571 } 572 vmcs_write(GUEST_RIP, guest_rip + insn_len); 573 return VMX_TEST_RESUME; 574 case VMX_CR: 575 switch (vmx_get_test_stage()) { 576 case 4: 577 report_fail("Read shadowing CR0"); 578 vmx_inc_test_stage(); 579 break; 580 case 5: 581 report_fail("Read shadowing CR4"); 582 vmx_inc_test_stage(); 583 break; 584 case 6: 585 report_fail("Write shadowing CR0 (same value)"); 586 vmx_inc_test_stage(); 587 break; 588 case 7: 589 report_fail("Write shadowing CR4 (same value)"); 590 vmx_inc_test_stage(); 591 break; 592 case 8: 593 case 9: 594 // 0x600 encodes "mov %esi, %cr0" 595 if (exit_qual == 0x600) 596 vmx_inc_test_stage(); 597 break; 598 case 10: 599 case 11: 600 // 0x604 encodes "mov %esi, %cr4" 601 if (exit_qual == 0x604) 602 vmx_inc_test_stage(); 603 break; 604 default: 605 // Should not reach here 606 report_fail("unexpected stage, %d", 607 vmx_get_test_stage()); 608 print_vmexit_info(exit_reason); 609 return VMX_TEST_VMEXIT; 610 } 611 vmcs_write(GUEST_RIP, guest_rip + insn_len); 612 return VMX_TEST_RESUME; 613 default: 614 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 615 print_vmexit_info(exit_reason); 616 } 617 return VMX_TEST_VMEXIT; 618 } 619 620 static int iobmp_init(struct vmcs *vmcs) 621 { 622 u32 ctrl_cpu0; 623 624 io_bitmap_a = alloc_page(); 625 io_bitmap_b = alloc_page(); 626 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 627 ctrl_cpu0 |= CPU_IO_BITMAP; 628 ctrl_cpu0 &= (~CPU_IO); 629 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 630 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 631 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 632 return VMX_TEST_START; 633 } 634 635 static void iobmp_main(void) 636 { 637 // stage 0, test IO pass 638 vmx_set_test_stage(0); 639 inb(0x5000); 640 outb(0x0, 0x5000); 641 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 642 // test IO width, in/out 643 ((u8 *)io_bitmap_a)[0] = 0xFF; 644 vmx_set_test_stage(2); 645 inb(0x0); 646 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 647 vmx_set_test_stage(3); 648 outw(0x0, 0x0); 649 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 650 vmx_set_test_stage(4); 651 inl(0x0); 652 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 653 // test low/high IO port 654 vmx_set_test_stage(5); 655 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 656 inb(0x5000); 657 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 658 vmx_set_test_stage(6); 659 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 660 inb(0x9000); 661 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 662 // test partial pass 663 vmx_set_test_stage(7); 664 inl(0x4FFF); 665 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 666 // test overrun 667 vmx_set_test_stage(8); 668 memset(io_bitmap_a, 0x0, PAGE_SIZE); 669 memset(io_bitmap_b, 0x0, PAGE_SIZE); 670 inl(0xFFFF); 671 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 672 vmx_set_test_stage(9); 673 vmcall(); 674 outb(0x0, 0x0); 675 report(vmx_get_test_stage() == 9, 676 "I/O bitmap - ignore unconditional exiting"); 677 vmx_set_test_stage(10); 678 vmcall(); 679 outb(0x0, 0x0); 680 report(vmx_get_test_stage() == 11, 681 "I/O bitmap - unconditional exiting"); 682 } 683 684 static int iobmp_exit_handler(union exit_reason exit_reason) 685 { 686 u64 guest_rip; 687 ulong exit_qual; 688 u32 insn_len, ctrl_cpu0; 689 690 guest_rip = vmcs_read(GUEST_RIP); 691 exit_qual = vmcs_read(EXI_QUALIFICATION); 692 insn_len = vmcs_read(EXI_INST_LEN); 693 switch (exit_reason.basic) { 694 case VMX_IO: 695 switch (vmx_get_test_stage()) { 696 case 0: 697 case 1: 698 vmx_inc_test_stage(); 699 break; 700 case 2: 701 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 702 "I/O bitmap - I/O width, byte"); 703 report(exit_qual & VMX_IO_IN, 704 "I/O bitmap - I/O direction, in"); 705 vmx_inc_test_stage(); 706 break; 707 case 3: 708 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 709 "I/O bitmap - I/O width, word"); 710 report(!(exit_qual & VMX_IO_IN), 711 "I/O bitmap - I/O direction, out"); 712 vmx_inc_test_stage(); 713 break; 714 case 4: 715 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 716 "I/O bitmap - I/O width, long"); 717 vmx_inc_test_stage(); 718 break; 719 case 5: 720 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 721 vmx_inc_test_stage(); 722 break; 723 case 6: 724 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 725 vmx_inc_test_stage(); 726 break; 727 case 7: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 729 vmx_inc_test_stage(); 730 break; 731 case 8: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 733 vmx_inc_test_stage(); 734 break; 735 case 9: 736 case 10: 737 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 738 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 739 vmx_inc_test_stage(); 740 break; 741 default: 742 // Should not reach here 743 report_fail("unexpected stage, %d", 744 vmx_get_test_stage()); 745 print_vmexit_info(exit_reason); 746 return VMX_TEST_VMEXIT; 747 } 748 vmcs_write(GUEST_RIP, guest_rip + insn_len); 749 return VMX_TEST_RESUME; 750 case VMX_VMCALL: 751 switch (vmx_get_test_stage()) { 752 case 9: 753 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 754 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 755 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 756 break; 757 case 10: 758 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 759 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 760 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 761 break; 762 default: 763 // Should not reach here 764 report_fail("unexpected stage, %d", 765 vmx_get_test_stage()); 766 print_vmexit_info(exit_reason); 767 return VMX_TEST_VMEXIT; 768 } 769 vmcs_write(GUEST_RIP, guest_rip + insn_len); 770 return VMX_TEST_RESUME; 771 default: 772 printf("guest_rip = %#lx\n", guest_rip); 773 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 774 break; 775 } 776 return VMX_TEST_VMEXIT; 777 } 778 779 #define INSN_CPU0 0 780 #define INSN_CPU1 1 781 #define INSN_ALWAYS_TRAP 2 782 783 #define FIELD_EXIT_QUAL (1 << 0) 784 #define FIELD_INSN_INFO (1 << 1) 785 786 asm( 787 "insn_hlt: hlt;ret\n\t" 788 "insn_invlpg: invlpg 0x12345678;ret\n\t" 789 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 790 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 791 "insn_rdtsc: rdtsc;ret\n\t" 792 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 793 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 794 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 795 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 796 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 797 "insn_pause: pause;ret\n\t" 798 "insn_wbinvd: wbinvd;ret\n\t" 799 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 800 "insn_invd: invd;ret\n\t" 801 "insn_sgdt: sgdt gdt_descr;ret\n\t" 802 "insn_lgdt: lgdt gdt_descr;ret\n\t" 803 "insn_sidt: sidt idt_descr;ret\n\t" 804 "insn_lidt: lidt idt_descr;ret\n\t" 805 "insn_sldt: sldt %ax;ret\n\t" 806 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 807 "insn_str: str %ax;ret\n\t" 808 "insn_rdrand: rdrand %rax;ret\n\t" 809 "insn_rdseed: rdseed %rax;ret\n\t" 810 ); 811 extern void insn_hlt(void); 812 extern void insn_invlpg(void); 813 extern void insn_mwait(void); 814 extern void insn_rdpmc(void); 815 extern void insn_rdtsc(void); 816 extern void insn_cr3_load(void); 817 extern void insn_cr3_store(void); 818 extern void insn_cr8_load(void); 819 extern void insn_cr8_store(void); 820 extern void insn_monitor(void); 821 extern void insn_pause(void); 822 extern void insn_wbinvd(void); 823 extern void insn_sgdt(void); 824 extern void insn_lgdt(void); 825 extern void insn_sidt(void); 826 extern void insn_lidt(void); 827 extern void insn_sldt(void); 828 extern void insn_lldt(void); 829 extern void insn_str(void); 830 extern void insn_cpuid(void); 831 extern void insn_invd(void); 832 extern void insn_rdrand(void); 833 extern void insn_rdseed(void); 834 835 u32 cur_insn; 836 u64 cr3; 837 838 #define X86_FEATURE_MONITOR (1 << 3) 839 840 typedef bool (*supported_fn)(void); 841 842 static bool monitor_supported(void) 843 { 844 return this_cpu_has(X86_FEATURE_MWAIT); 845 } 846 847 struct insn_table { 848 const char *name; 849 u32 flag; 850 void (*insn_func)(void); 851 u32 type; 852 u32 reason; 853 ulong exit_qual; 854 u32 insn_info; 855 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 856 // which field need to be tested, reason is always tested 857 u32 test_field; 858 const supported_fn supported_fn; 859 u8 disabled; 860 }; 861 862 /* 863 * Add more test cases of instruction intercept here. Elements in this 864 * table is: 865 * name/control flag/insn function/type/exit reason/exit qulification/ 866 * instruction info/field to test 867 * The last field defines which fields (exit_qual and insn_info) need to be 868 * tested in exit handler. If set to 0, only "reason" is checked. 869 */ 870 static struct insn_table insn_table[] = { 871 // Flags for Primary Processor-Based VM-Execution Controls 872 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 873 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 874 0x12345678, 0, FIELD_EXIT_QUAL}, 875 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 876 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 877 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 878 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 879 FIELD_EXIT_QUAL}, 880 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 881 FIELD_EXIT_QUAL}, 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 887 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 888 // Flags for Secondary Processor-Based VM-Execution Controls 889 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 890 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 897 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 898 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 899 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 900 // Instructions always trap 901 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 902 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 903 // Instructions never trap 904 {NULL}, 905 }; 906 907 static int insn_intercept_init(struct vmcs *vmcs) 908 { 909 u32 ctrl_cpu, cur_insn; 910 911 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 912 ctrl_cpu &= ctrl_cpu_rev[0].clr; 913 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 914 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 915 cr3 = read_cr3(); 916 917 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 918 if (insn_table[cur_insn].supported_fn == NULL) 919 continue; 920 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 921 } 922 return VMX_TEST_START; 923 } 924 925 static void insn_intercept_main(void) 926 { 927 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 928 vmx_set_test_stage(cur_insn * 2); 929 if ((insn_table[cur_insn].type == INSN_CPU0 && 930 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 931 (insn_table[cur_insn].type == INSN_CPU1 && 932 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 933 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 934 insn_table[cur_insn].type - INSN_CPU0, 935 insn_table[cur_insn].name); 936 continue; 937 } 938 939 if (insn_table[cur_insn].disabled) { 940 printf("\tFeature required for %s is not supported.\n", 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if ((insn_table[cur_insn].type == INSN_CPU0 && 946 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 947 (insn_table[cur_insn].type == INSN_CPU1 && 948 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 949 /* skip hlt, it stalls the guest and is tested below */ 950 if (insn_table[cur_insn].insn_func != insn_hlt) 951 insn_table[cur_insn].insn_func(); 952 report(vmx_get_test_stage() == cur_insn * 2, 953 "execute %s", 954 insn_table[cur_insn].name); 955 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 956 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 957 insn_table[cur_insn].type - INSN_CPU0, 958 insn_table[cur_insn].name); 959 960 vmcall(); 961 962 insn_table[cur_insn].insn_func(); 963 report(vmx_get_test_stage() == cur_insn * 2 + 1, 964 "intercept %s", 965 insn_table[cur_insn].name); 966 967 vmx_set_test_stage(cur_insn * 2 + 1); 968 vmcall(); 969 } 970 } 971 972 static int insn_intercept_exit_handler(union exit_reason exit_reason) 973 { 974 u64 guest_rip; 975 ulong exit_qual; 976 u32 insn_len; 977 u32 insn_info; 978 bool pass; 979 980 guest_rip = vmcs_read(GUEST_RIP); 981 exit_qual = vmcs_read(EXI_QUALIFICATION); 982 insn_len = vmcs_read(EXI_INST_LEN); 983 insn_info = vmcs_read(EXI_INST_INFO); 984 985 if (exit_reason.basic == VMX_VMCALL) { 986 u32 val = 0; 987 988 if (insn_table[cur_insn].type == INSN_CPU0) 989 val = vmcs_read(CPU_EXEC_CTRL0); 990 else if (insn_table[cur_insn].type == INSN_CPU1) 991 val = vmcs_read(CPU_EXEC_CTRL1); 992 993 if (vmx_get_test_stage() & 1) 994 val &= ~insn_table[cur_insn].flag; 995 else 996 val |= insn_table[cur_insn].flag; 997 998 if (insn_table[cur_insn].type == INSN_CPU0) 999 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1000 else if (insn_table[cur_insn].type == INSN_CPU1) 1001 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1002 } else { 1003 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1004 insn_table[cur_insn].reason == exit_reason.full; 1005 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1006 insn_table[cur_insn].exit_qual != exit_qual) 1007 pass = false; 1008 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1009 insn_table[cur_insn].insn_info != insn_info) 1010 pass = false; 1011 if (pass) 1012 vmx_inc_test_stage(); 1013 } 1014 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1015 return VMX_TEST_RESUME; 1016 } 1017 1018 /** 1019 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1020 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1021 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1022 * 1023 * Returns 0 on success, 1 on failure. 1024 * 1025 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1026 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1027 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1028 */ 1029 static int __setup_ept(u64 hpa, bool enable_ad) 1030 { 1031 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1032 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1033 printf("\tEPT is not supported\n"); 1034 return 1; 1035 } 1036 if (!(ept_vpid.val & EPT_CAP_WB)) { 1037 printf("\tWB memtype for EPT walks not supported\n"); 1038 return 1; 1039 } 1040 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1041 printf("\tPWL4 is not supported\n"); 1042 return 1; 1043 } 1044 1045 eptp = EPT_MEM_TYPE_WB; 1046 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1047 eptp |= hpa; 1048 if (enable_ad) 1049 eptp |= EPTP_AD_FLAG; 1050 1051 vmcs_write(EPTP, eptp); 1052 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1053 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1060 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1061 * 1062 * Returns 0 on success, 1 on failure. 1063 * 1064 * This is the "real" function for setting up EPT tables, i.e. use this for 1065 * tests that need to run code in the guest with EPT enabled. 1066 */ 1067 static int setup_ept(bool enable_ad) 1068 { 1069 unsigned long end_of_memory; 1070 1071 pml4 = alloc_page(); 1072 1073 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1074 return 1; 1075 1076 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1077 if (end_of_memory < (1ul << 32)) 1078 end_of_memory = (1ul << 32); 1079 /* Cannot use large EPT pages if we need to track EPT 1080 * accessed/dirty bits at 4K granularity. 1081 */ 1082 setup_ept_range(pml4, 0, end_of_memory, 0, 1083 !enable_ad && ept_2m_supported(), 1084 EPT_WA | EPT_RA | EPT_EA); 1085 return 0; 1086 } 1087 1088 /** 1089 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1090 * 1091 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1092 * for use by tests that need EPT enabled to verify dependent VMCS controls 1093 * but never expect to fully enter the guest, i.e. don't need setup the actual 1094 * EPT tables. 1095 */ 1096 static void setup_dummy_ept(void) 1097 { 1098 if (__setup_ept(0, false)) 1099 report_abort("EPT setup unexpectedly failed"); 1100 } 1101 1102 static int enable_unrestricted_guest(bool need_valid_ept) 1103 { 1104 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1105 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1106 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1107 return 1; 1108 1109 if (need_valid_ept) 1110 setup_ept(false); 1111 else 1112 setup_dummy_ept(); 1113 1114 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1115 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1116 1117 return 0; 1118 } 1119 1120 static void ept_enable_ad_bits(void) 1121 { 1122 eptp |= EPTP_AD_FLAG; 1123 vmcs_write(EPTP, eptp); 1124 } 1125 1126 static void ept_disable_ad_bits(void) 1127 { 1128 eptp &= ~EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static int ept_ad_enabled(void) 1133 { 1134 return eptp & EPTP_AD_FLAG; 1135 } 1136 1137 static void ept_enable_ad_bits_or_skip_test(void) 1138 { 1139 if (!ept_ad_bits_supported()) 1140 test_skip("EPT AD bits not supported."); 1141 ept_enable_ad_bits(); 1142 } 1143 1144 static int apic_version; 1145 1146 static int ept_init_common(bool have_ad) 1147 { 1148 int ret; 1149 struct pci_dev pcidev; 1150 1151 /* INVEPT is required by the EPT violation handler. */ 1152 if (!is_invept_type_supported(INVEPT_SINGLE)) 1153 return VMX_TEST_EXIT; 1154 1155 if (setup_ept(have_ad)) 1156 return VMX_TEST_EXIT; 1157 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report_fail("EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report_pass("EPT basic framework"); 1194 else 1195 report_pass("EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report_fail("EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = __invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report_fail("unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 invept(INVEPT_SINGLE, eptp); 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report_fail("EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 invept(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 invept(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 invept(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 invept(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 invept(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report_fail("ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 invept(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report_fail("ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 invept(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 invept(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 invept(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 invept(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report_fail("ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if (!ept_ad_bits_supported()) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 #define TIMER_VECTOR 222 1549 1550 static volatile bool timer_fired; 1551 1552 static void timer_isr(isr_regs_t *regs) 1553 { 1554 timer_fired = true; 1555 apic_write(APIC_EOI, 0); 1556 } 1557 1558 static int interrupt_init(struct vmcs *vmcs) 1559 { 1560 msr_bmp_init(); 1561 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1562 handle_irq(TIMER_VECTOR, timer_isr); 1563 return VMX_TEST_START; 1564 } 1565 1566 static void interrupt_main(void) 1567 { 1568 long long start, loops; 1569 1570 vmx_set_test_stage(0); 1571 1572 apic_write(APIC_LVTT, TIMER_VECTOR); 1573 irq_enable(); 1574 1575 apic_write(APIC_TMICT, 1); 1576 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1577 asm volatile ("nop"); 1578 report(timer_fired, "direct interrupt while running guest"); 1579 1580 apic_write(APIC_TMICT, 0); 1581 irq_disable(); 1582 vmcall(); 1583 timer_fired = false; 1584 apic_write(APIC_TMICT, 1); 1585 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1586 asm volatile ("nop"); 1587 report(timer_fired, "intercepted interrupt while running guest"); 1588 1589 irq_enable(); 1590 apic_write(APIC_TMICT, 0); 1591 irq_disable(); 1592 vmcall(); 1593 timer_fired = false; 1594 start = rdtsc(); 1595 apic_write(APIC_TMICT, 1000000); 1596 1597 safe_halt(); 1598 1599 report(rdtsc() - start > 1000000 && timer_fired, 1600 "direct interrupt + hlt"); 1601 1602 apic_write(APIC_TMICT, 0); 1603 irq_disable(); 1604 vmcall(); 1605 timer_fired = false; 1606 start = rdtsc(); 1607 apic_write(APIC_TMICT, 1000000); 1608 1609 safe_halt(); 1610 1611 report(rdtsc() - start > 10000 && timer_fired, 1612 "intercepted interrupt + hlt"); 1613 1614 apic_write(APIC_TMICT, 0); 1615 irq_disable(); 1616 vmcall(); 1617 timer_fired = false; 1618 start = rdtsc(); 1619 apic_write(APIC_TMICT, 1000000); 1620 1621 irq_enable(); 1622 asm volatile ("nop"); 1623 vmcall(); 1624 1625 report(rdtsc() - start > 10000 && timer_fired, 1626 "direct interrupt + activity state hlt"); 1627 1628 apic_write(APIC_TMICT, 0); 1629 irq_disable(); 1630 vmcall(); 1631 timer_fired = false; 1632 start = rdtsc(); 1633 apic_write(APIC_TMICT, 1000000); 1634 1635 irq_enable(); 1636 asm volatile ("nop"); 1637 vmcall(); 1638 1639 report(rdtsc() - start > 10000 && timer_fired, 1640 "intercepted interrupt + activity state hlt"); 1641 1642 apic_write(APIC_TMICT, 0); 1643 irq_disable(); 1644 vmx_set_test_stage(7); 1645 vmcall(); 1646 timer_fired = false; 1647 apic_write(APIC_TMICT, 1); 1648 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1649 asm volatile ("nop"); 1650 report(timer_fired, 1651 "running a guest with interrupt acknowledgement set"); 1652 1653 apic_write(APIC_TMICT, 0); 1654 irq_enable(); 1655 timer_fired = false; 1656 vmcall(); 1657 report(timer_fired, "Inject an event to a halted guest"); 1658 } 1659 1660 static int interrupt_exit_handler(union exit_reason exit_reason) 1661 { 1662 u64 guest_rip = vmcs_read(GUEST_RIP); 1663 u32 insn_len = vmcs_read(EXI_INST_LEN); 1664 1665 switch (exit_reason.basic) { 1666 case VMX_VMCALL: 1667 switch (vmx_get_test_stage()) { 1668 case 0: 1669 case 2: 1670 case 5: 1671 vmcs_write(PIN_CONTROLS, 1672 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1673 break; 1674 case 7: 1675 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1676 vmcs_write(PIN_CONTROLS, 1677 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1678 break; 1679 case 1: 1680 case 3: 1681 vmcs_write(PIN_CONTROLS, 1682 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1683 break; 1684 case 4: 1685 case 6: 1686 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1687 break; 1688 1689 case 8: 1690 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1691 vmcs_write(ENT_INTR_INFO, 1692 TIMER_VECTOR | 1693 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1694 INTR_INFO_VALID_MASK); 1695 break; 1696 } 1697 vmx_inc_test_stage(); 1698 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1699 return VMX_TEST_RESUME; 1700 case VMX_EXTINT: 1701 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1702 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1703 handle_external_interrupt(vector); 1704 } else { 1705 irq_enable(); 1706 asm volatile ("nop"); 1707 irq_disable(); 1708 } 1709 if (vmx_get_test_stage() >= 2) 1710 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1711 return VMX_TEST_RESUME; 1712 default: 1713 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1714 print_vmexit_info(exit_reason); 1715 } 1716 1717 return VMX_TEST_VMEXIT; 1718 } 1719 1720 1721 static volatile int nmi_fired; 1722 1723 #define NMI_DELAY 100000000ULL 1724 1725 static void nmi_isr(isr_regs_t *regs) 1726 { 1727 nmi_fired = true; 1728 } 1729 1730 static int nmi_hlt_init(struct vmcs *vmcs) 1731 { 1732 msr_bmp_init(); 1733 handle_irq(NMI_VECTOR, nmi_isr); 1734 vmcs_write(PIN_CONTROLS, 1735 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1736 vmcs_write(PIN_CONTROLS, 1737 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1738 return VMX_TEST_START; 1739 } 1740 1741 static void nmi_message_thread(void *data) 1742 { 1743 while (vmx_get_test_stage() != 1) 1744 pause(); 1745 1746 delay(NMI_DELAY); 1747 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1748 1749 while (vmx_get_test_stage() != 2) 1750 pause(); 1751 1752 delay(NMI_DELAY); 1753 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1754 } 1755 1756 static void nmi_hlt_main(void) 1757 { 1758 long long start; 1759 1760 if (cpu_count() < 2) { 1761 report_skip(__func__); 1762 vmx_set_test_stage(-1); 1763 return; 1764 } 1765 1766 vmx_set_test_stage(0); 1767 on_cpu_async(1, nmi_message_thread, NULL); 1768 start = rdtsc(); 1769 vmx_set_test_stage(1); 1770 asm volatile ("hlt"); 1771 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1772 "direct NMI + hlt"); 1773 if (!nmi_fired) 1774 vmx_set_test_stage(-1); 1775 nmi_fired = false; 1776 1777 vmcall(); 1778 1779 start = rdtsc(); 1780 vmx_set_test_stage(2); 1781 asm volatile ("hlt"); 1782 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1783 "intercepted NMI + hlt"); 1784 if (nmi_fired) { 1785 report(!nmi_fired, "intercepted NMI was dispatched"); 1786 vmx_set_test_stage(-1); 1787 return; 1788 } 1789 vmx_set_test_stage(3); 1790 } 1791 1792 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1793 { 1794 u64 guest_rip = vmcs_read(GUEST_RIP); 1795 u32 insn_len = vmcs_read(EXI_INST_LEN); 1796 1797 switch (vmx_get_test_stage()) { 1798 case 1: 1799 if (exit_reason.basic != VMX_VMCALL) { 1800 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1801 exit_reason.full); 1802 print_vmexit_info(exit_reason); 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 vmcs_write(PIN_CONTROLS, 1807 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1808 vmcs_write(PIN_CONTROLS, 1809 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1810 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1811 break; 1812 1813 case 2: 1814 if (exit_reason.basic != VMX_EXC_NMI) { 1815 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1816 exit_reason.full); 1817 print_vmexit_info(exit_reason); 1818 return VMX_TEST_VMEXIT; 1819 } 1820 report_pass("NMI intercept while running guest"); 1821 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1822 break; 1823 1824 case 3: 1825 break; 1826 1827 default: 1828 return VMX_TEST_VMEXIT; 1829 } 1830 1831 if (vmx_get_test_stage() == 3) 1832 return VMX_TEST_VMEXIT; 1833 1834 return VMX_TEST_RESUME; 1835 } 1836 1837 1838 static int dbgctls_init(struct vmcs *vmcs) 1839 { 1840 u64 dr7 = 0x402; 1841 u64 zero = 0; 1842 1843 msr_bmp_init(); 1844 asm volatile( 1845 "mov %0,%%dr0\n\t" 1846 "mov %0,%%dr1\n\t" 1847 "mov %0,%%dr2\n\t" 1848 "mov %1,%%dr7\n\t" 1849 : : "r" (zero), "r" (dr7)); 1850 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1851 vmcs_write(GUEST_DR7, 0x404); 1852 vmcs_write(GUEST_DEBUGCTL, 0x2); 1853 1854 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1855 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1856 1857 return VMX_TEST_START; 1858 } 1859 1860 static void dbgctls_main(void) 1861 { 1862 u64 dr7, debugctl; 1863 1864 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1865 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1866 /* Commented out: KVM does not support DEBUGCTL so far */ 1867 (void)debugctl; 1868 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1869 1870 dr7 = 0x408; 1871 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1872 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1873 1874 vmx_set_test_stage(0); 1875 vmcall(); 1876 report(vmx_get_test_stage() == 1, "Save debug controls"); 1877 1878 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1879 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1880 printf("\tDebug controls are always loaded/saved\n"); 1881 return; 1882 } 1883 vmx_set_test_stage(2); 1884 vmcall(); 1885 1886 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1887 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1888 /* Commented out: KVM does not support DEBUGCTL so far */ 1889 (void)debugctl; 1890 report(dr7 == 0x402, 1891 "Guest=host debug controls" /* && debugctl == 0x1 */); 1892 1893 dr7 = 0x408; 1894 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1895 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1896 1897 vmx_set_test_stage(3); 1898 vmcall(); 1899 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1900 } 1901 1902 static int dbgctls_exit_handler(union exit_reason exit_reason) 1903 { 1904 u32 insn_len = vmcs_read(EXI_INST_LEN); 1905 u64 guest_rip = vmcs_read(GUEST_RIP); 1906 u64 dr7, debugctl; 1907 1908 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1909 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1910 1911 switch (exit_reason.basic) { 1912 case VMX_VMCALL: 1913 switch (vmx_get_test_stage()) { 1914 case 0: 1915 if (dr7 == 0x400 && debugctl == 0 && 1916 vmcs_read(GUEST_DR7) == 0x408 /* && 1917 Commented out: KVM does not support DEBUGCTL so far 1918 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1919 vmx_inc_test_stage(); 1920 break; 1921 case 2: 1922 dr7 = 0x402; 1923 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1924 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1925 vmcs_write(GUEST_DR7, 0x404); 1926 vmcs_write(GUEST_DEBUGCTL, 0x2); 1927 1928 vmcs_write(ENT_CONTROLS, 1929 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1930 vmcs_write(EXI_CONTROLS, 1931 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1932 break; 1933 case 3: 1934 if (dr7 == 0x400 && debugctl == 0 && 1935 vmcs_read(GUEST_DR7) == 0x404 /* && 1936 Commented out: KVM does not support DEBUGCTL so far 1937 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1938 vmx_inc_test_stage(); 1939 break; 1940 } 1941 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1942 return VMX_TEST_RESUME; 1943 default: 1944 report_fail("Unknown exit reason, %d", exit_reason.full); 1945 print_vmexit_info(exit_reason); 1946 } 1947 return VMX_TEST_VMEXIT; 1948 } 1949 1950 struct vmx_msr_entry { 1951 u32 index; 1952 u32 reserved; 1953 u64 value; 1954 } __attribute__((packed)); 1955 1956 #define MSR_MAGIC 0x31415926 1957 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1958 1959 static int msr_switch_init(struct vmcs *vmcs) 1960 { 1961 msr_bmp_init(); 1962 exit_msr_store = alloc_page(); 1963 exit_msr_load = alloc_page(); 1964 entry_msr_load = alloc_page(); 1965 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1966 entry_msr_load[0].value = MSR_MAGIC; 1967 1968 vmx_set_test_stage(1); 1969 vmcs_write(ENT_MSR_LD_CNT, 1); 1970 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1971 vmcs_write(EXI_MSR_ST_CNT, 1); 1972 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1973 vmcs_write(EXI_MSR_LD_CNT, 1); 1974 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1975 return VMX_TEST_START; 1976 } 1977 1978 static void msr_switch_main(void) 1979 { 1980 if (vmx_get_test_stage() == 1) { 1981 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1982 "VM entry MSR load"); 1983 vmx_set_test_stage(2); 1984 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1985 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1986 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1987 exit_msr_load[0].value = MSR_MAGIC + 2; 1988 } 1989 vmcall(); 1990 } 1991 1992 static int msr_switch_exit_handler(union exit_reason exit_reason) 1993 { 1994 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1995 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1996 "VM exit MSR store"); 1997 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1998 "VM exit MSR load"); 1999 vmx_set_test_stage(3); 2000 entry_msr_load[0].index = MSR_FS_BASE; 2001 return VMX_TEST_RESUME; 2002 } 2003 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2004 __func__, vmx_get_test_stage(), exit_reason.full); 2005 return VMX_TEST_EXIT; 2006 } 2007 2008 static int msr_switch_entry_failure(struct vmentry_result *result) 2009 { 2010 if (result->vm_fail) { 2011 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2012 return VMX_TEST_EXIT; 2013 } 2014 2015 if (result->exit_reason.failed_vmentry && 2016 result->exit_reason.basic == VMX_FAIL_MSR && 2017 vmx_get_test_stage() == 3) { 2018 report(vmcs_read(EXI_QUALIFICATION) == 1, 2019 "VM entry MSR load: try to load FS_BASE"); 2020 return VMX_TEST_VMEXIT; 2021 } 2022 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2023 __func__, vmx_get_test_stage(), result->exit_reason.full); 2024 return VMX_TEST_EXIT; 2025 } 2026 2027 static int vmmcall_init(struct vmcs *vmcs) 2028 { 2029 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2030 return VMX_TEST_START; 2031 } 2032 2033 static void vmmcall_main(void) 2034 { 2035 asm volatile( 2036 "mov $0xABCD, %%rax\n\t" 2037 "vmmcall\n\t" 2038 ::: "rax"); 2039 2040 report_fail("VMMCALL"); 2041 } 2042 2043 static int vmmcall_exit_handler(union exit_reason exit_reason) 2044 { 2045 switch (exit_reason.basic) { 2046 case VMX_VMCALL: 2047 printf("here\n"); 2048 report_fail("VMMCALL triggers #UD"); 2049 break; 2050 case VMX_EXC_NMI: 2051 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2052 "VMMCALL triggers #UD"); 2053 break; 2054 default: 2055 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2056 print_vmexit_info(exit_reason); 2057 } 2058 2059 return VMX_TEST_VMEXIT; 2060 } 2061 2062 static int disable_rdtscp_init(struct vmcs *vmcs) 2063 { 2064 u32 ctrl_cpu1; 2065 2066 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2067 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2068 ctrl_cpu1 &= ~CPU_RDTSCP; 2069 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2070 } 2071 2072 return VMX_TEST_START; 2073 } 2074 2075 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2076 { 2077 switch (vmx_get_test_stage()) { 2078 case 0: 2079 report_pass("RDTSCP triggers #UD"); 2080 vmx_inc_test_stage(); 2081 regs->rip += 3; 2082 break; 2083 case 2: 2084 report_pass("RDPID triggers #UD"); 2085 vmx_inc_test_stage(); 2086 regs->rip += 4; 2087 break; 2088 } 2089 return; 2090 2091 } 2092 2093 static void disable_rdtscp_main(void) 2094 { 2095 /* Test that #UD is properly injected in L2. */ 2096 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2097 2098 vmx_set_test_stage(0); 2099 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2100 vmcall(); 2101 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2102 2103 handle_exception(UD_VECTOR, 0); 2104 vmcall(); 2105 } 2106 2107 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2108 { 2109 switch (exit_reason.basic) { 2110 case VMX_VMCALL: 2111 switch (vmx_get_test_stage()) { 2112 case 0: 2113 report_fail("RDTSCP triggers #UD"); 2114 vmx_inc_test_stage(); 2115 /* fallthrough */ 2116 case 1: 2117 vmx_inc_test_stage(); 2118 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2119 return VMX_TEST_RESUME; 2120 case 2: 2121 report_fail("RDPID triggers #UD"); 2122 break; 2123 } 2124 break; 2125 2126 default: 2127 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2128 print_vmexit_info(exit_reason); 2129 } 2130 return VMX_TEST_VMEXIT; 2131 } 2132 2133 static int int3_init(struct vmcs *vmcs) 2134 { 2135 vmcs_write(EXC_BITMAP, ~0u); 2136 return VMX_TEST_START; 2137 } 2138 2139 static void int3_guest_main(void) 2140 { 2141 asm volatile ("int3"); 2142 } 2143 2144 static int int3_exit_handler(union exit_reason exit_reason) 2145 { 2146 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2147 2148 report(exit_reason.basic == VMX_EXC_NMI && 2149 (intr_info & INTR_INFO_VALID_MASK) && 2150 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2151 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2152 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2153 "L1 intercepts #BP"); 2154 2155 return VMX_TEST_VMEXIT; 2156 } 2157 2158 static int into_init(struct vmcs *vmcs) 2159 { 2160 vmcs_write(EXC_BITMAP, ~0u); 2161 return VMX_TEST_START; 2162 } 2163 2164 static void into_guest_main(void) 2165 { 2166 struct far_pointer32 fp = { 2167 .offset = (uintptr_t)&&into, 2168 .selector = KERNEL_CS32, 2169 }; 2170 uintptr_t rsp; 2171 2172 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2173 2174 if (fp.offset != (uintptr_t)&&into) { 2175 printf("Code address too high.\n"); 2176 return; 2177 } 2178 if ((u32)rsp != rsp) { 2179 printf("Stack address too high.\n"); 2180 return; 2181 } 2182 2183 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2184 return; 2185 into: 2186 asm volatile (".code32;" 2187 "movl $0x7fffffff, %eax;" 2188 "addl %eax, %eax;" 2189 "into;" 2190 "lret;" 2191 ".code64"); 2192 __builtin_unreachable(); 2193 } 2194 2195 static int into_exit_handler(union exit_reason exit_reason) 2196 { 2197 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2198 2199 report(exit_reason.basic == VMX_EXC_NMI && 2200 (intr_info & INTR_INFO_VALID_MASK) && 2201 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2202 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2203 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2204 "L1 intercepts #OF"); 2205 2206 return VMX_TEST_VMEXIT; 2207 } 2208 2209 static void exit_monitor_from_l2_main(void) 2210 { 2211 printf("Calling exit(0) from l2...\n"); 2212 exit(0); 2213 } 2214 2215 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2216 { 2217 report_fail("The guest should have killed the VMM"); 2218 return VMX_TEST_EXIT; 2219 } 2220 2221 static void assert_exit_reason(u64 expected) 2222 { 2223 u64 actual = vmcs_read(EXI_REASON); 2224 2225 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2226 exit_reason_description(expected), 2227 exit_reason_description(actual)); 2228 } 2229 2230 static void skip_exit_insn(void) 2231 { 2232 u64 guest_rip = vmcs_read(GUEST_RIP); 2233 u32 insn_len = vmcs_read(EXI_INST_LEN); 2234 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2235 } 2236 2237 static void skip_exit_vmcall(void) 2238 { 2239 assert_exit_reason(VMX_VMCALL); 2240 skip_exit_insn(); 2241 } 2242 2243 static void v2_null_test_guest(void) 2244 { 2245 } 2246 2247 static void v2_null_test(void) 2248 { 2249 test_set_guest(v2_null_test_guest); 2250 enter_guest(); 2251 report_pass(__func__); 2252 } 2253 2254 static void v2_multiple_entries_test_guest(void) 2255 { 2256 vmx_set_test_stage(1); 2257 vmcall(); 2258 vmx_set_test_stage(2); 2259 } 2260 2261 static void v2_multiple_entries_test(void) 2262 { 2263 test_set_guest(v2_multiple_entries_test_guest); 2264 enter_guest(); 2265 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2266 skip_exit_vmcall(); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2269 report_pass(__func__); 2270 } 2271 2272 static int fixture_test_data = 1; 2273 2274 static void fixture_test_teardown(void *data) 2275 { 2276 *((int *) data) = 1; 2277 } 2278 2279 static void fixture_test_guest(void) 2280 { 2281 fixture_test_data++; 2282 } 2283 2284 2285 static void fixture_test_setup(void) 2286 { 2287 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2288 "fixture_test_teardown didn't run?!"); 2289 fixture_test_data = 2; 2290 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2291 test_set_guest(fixture_test_guest); 2292 } 2293 2294 static void fixture_test_case1(void) 2295 { 2296 fixture_test_setup(); 2297 TEST_ASSERT_EQ(2, fixture_test_data); 2298 enter_guest(); 2299 TEST_ASSERT_EQ(3, fixture_test_data); 2300 report_pass(__func__); 2301 } 2302 2303 static void fixture_test_case2(void) 2304 { 2305 fixture_test_setup(); 2306 TEST_ASSERT_EQ(2, fixture_test_data); 2307 enter_guest(); 2308 TEST_ASSERT_EQ(3, fixture_test_data); 2309 report_pass(__func__); 2310 } 2311 2312 enum ept_access_op { 2313 OP_READ, 2314 OP_WRITE, 2315 OP_EXEC, 2316 OP_FLUSH_TLB, 2317 OP_EXIT, 2318 }; 2319 2320 static struct ept_access_test_data { 2321 unsigned long gpa; 2322 unsigned long *gva; 2323 unsigned long hpa; 2324 unsigned long *hva; 2325 enum ept_access_op op; 2326 } ept_access_test_data; 2327 2328 extern unsigned char ret42_start; 2329 extern unsigned char ret42_end; 2330 2331 /* Returns 42. */ 2332 asm( 2333 ".align 64\n" 2334 "ret42_start:\n" 2335 "mov $42, %eax\n" 2336 "ret\n" 2337 "ret42_end:\n" 2338 ); 2339 2340 static void 2341 diagnose_ept_violation_qual(u64 expected, u64 actual) 2342 { 2343 2344 #define DIAGNOSE(flag) \ 2345 do { \ 2346 if ((expected & flag) != (actual & flag)) \ 2347 printf(#flag " %sexpected\n", \ 2348 (expected & flag) ? "" : "un"); \ 2349 } while (0) 2350 2351 DIAGNOSE(EPT_VLT_RD); 2352 DIAGNOSE(EPT_VLT_WR); 2353 DIAGNOSE(EPT_VLT_FETCH); 2354 DIAGNOSE(EPT_VLT_PERM_RD); 2355 DIAGNOSE(EPT_VLT_PERM_WR); 2356 DIAGNOSE(EPT_VLT_PERM_EX); 2357 DIAGNOSE(EPT_VLT_LADDR_VLD); 2358 DIAGNOSE(EPT_VLT_PADDR); 2359 2360 #undef DIAGNOSE 2361 } 2362 2363 static void do_ept_access_op(enum ept_access_op op) 2364 { 2365 ept_access_test_data.op = op; 2366 enter_guest(); 2367 } 2368 2369 /* 2370 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2371 * needed by tests that modify guest PTEs. 2372 */ 2373 static void ept_access_test_guest_flush_tlb(void) 2374 { 2375 do_ept_access_op(OP_FLUSH_TLB); 2376 skip_exit_vmcall(); 2377 } 2378 2379 /* 2380 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2381 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2382 * a huge page. 2383 */ 2384 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2385 unsigned long clear, unsigned long set) 2386 { 2387 struct ept_access_test_data *data = &ept_access_test_data; 2388 unsigned long orig_pte; 2389 unsigned long pte; 2390 2391 /* Screw with the mapping at the requested level. */ 2392 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2393 pte = orig_pte; 2394 if (mkhuge) 2395 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2396 else 2397 pte = orig_pte; 2398 pte = (pte & ~clear) | set; 2399 set_ept_pte(pml4, gpa, level, pte); 2400 invept(INVEPT_SINGLE, eptp); 2401 2402 return orig_pte; 2403 } 2404 2405 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2406 { 2407 set_ept_pte(pml4, gpa, level, orig_pte); 2408 invept(INVEPT_SINGLE, eptp); 2409 } 2410 2411 static void do_ept_violation(bool leaf, enum ept_access_op op, 2412 u64 expected_qual, u64 expected_paddr) 2413 { 2414 u64 qual; 2415 2416 /* Try the access and observe the violation. */ 2417 do_ept_access_op(op); 2418 2419 assert_exit_reason(VMX_EPT_VIOLATION); 2420 2421 qual = vmcs_read(EXI_QUALIFICATION); 2422 2423 /* Mask undefined bits (which may later be defined in certain cases). */ 2424 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2425 EPT_VLT_PERM_USER_EX); 2426 2427 diagnose_ept_violation_qual(expected_qual, qual); 2428 TEST_EXPECT_EQ(expected_qual, qual); 2429 2430 #if 0 2431 /* Disable for now otherwise every test will fail */ 2432 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2433 (unsigned long) ( 2434 op == OP_EXEC ? data->gva + 1 : data->gva)); 2435 #endif 2436 /* 2437 * TODO: tests that probe expected_paddr in pages other than the one at 2438 * the beginning of the 1g region. 2439 */ 2440 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2441 } 2442 2443 static void 2444 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2445 unsigned long set, enum ept_access_op op, 2446 u64 expected_qual) 2447 { 2448 struct ept_access_test_data *data = &ept_access_test_data; 2449 unsigned long orig_pte; 2450 2451 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2452 2453 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2454 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2455 data->gpa); 2456 2457 /* Fix the violation and resume the op loop. */ 2458 ept_untwiddle(data->gpa, level, orig_pte); 2459 enter_guest(); 2460 skip_exit_vmcall(); 2461 } 2462 2463 static void 2464 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2465 enum ept_access_op op, u64 expected_qual) 2466 { 2467 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2468 expected_qual); 2469 if (ept_huge_pages_supported(level)) 2470 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2471 expected_qual); 2472 } 2473 2474 static void ept_violation(unsigned long clear, unsigned long set, 2475 enum ept_access_op op, u64 expected_qual) 2476 { 2477 ept_violation_at_level(1, clear, set, op, expected_qual); 2478 ept_violation_at_level(2, clear, set, op, expected_qual); 2479 ept_violation_at_level(3, clear, set, op, expected_qual); 2480 ept_violation_at_level(4, clear, set, op, expected_qual); 2481 } 2482 2483 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2484 u64 expected_qual) 2485 { 2486 ept_violation(EPT_PRESENT, access, op, 2487 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2488 } 2489 2490 /* 2491 * For translations that don't involve a GVA, that is physical address (paddr) 2492 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2493 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2494 * translations don't involve GVAs, such as when the hardware does the guest 2495 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2496 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2497 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2498 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2499 * 2500 * Note that paddr violations can also be triggered by loading PAE page tables 2501 * with wonky addresses. We don't test that yet. 2502 * 2503 * This function modifies the EPT entry that maps the GPA that the guest page 2504 * table entry mapping ept_access_test_data.gva resides on. 2505 * 2506 * @ept_access EPT permissions to set. Other permissions are cleared. 2507 * 2508 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2509 * 2510 * @op Guest operation to perform with 2511 * ept_access_test_data.gva. 2512 * 2513 * @expect_violation 2514 * Is a violation expected during the paddr access? 2515 * 2516 * @expected_qual Expected qualification for the EPT violation. 2517 * EPT_VLT_PADDR should be clear. 2518 */ 2519 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2520 enum ept_access_op op, bool expect_violation, 2521 u64 expected_qual) 2522 { 2523 struct ept_access_test_data *data = &ept_access_test_data; 2524 unsigned long *ptep; 2525 unsigned long gpa; 2526 unsigned long orig_epte; 2527 unsigned long epte; 2528 int i; 2529 2530 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2531 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2532 TEST_ASSERT(ptep); 2533 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2534 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2535 ept_access_test_guest_flush_tlb(); 2536 2537 /* 2538 * Now modify the access bits on the EPT entry for the GPA that the 2539 * guest PTE resides on. Note that by modifying a single EPT entry, 2540 * we're potentially affecting 512 guest PTEs. However, we've carefully 2541 * constructed our test such that those other 511 PTEs aren't used by 2542 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2543 * PTE we're modifying is at the beginning of a 4K page and the 2544 * following 511 entires are also under our control (and not touched by 2545 * the guest). 2546 */ 2547 gpa = virt_to_phys(ptep); 2548 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2549 /* 2550 * Make sure the guest page table page is mapped with a 4K EPT entry, 2551 * otherwise our level=1 twiddling below will fail. We use the 2552 * identity map (gpa = gpa) since page tables are shared with the host. 2553 */ 2554 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2555 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2556 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2557 2558 if (expect_violation) { 2559 do_ept_violation(/*leaf=*/true, op, 2560 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2561 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2562 do_ept_access_op(op); 2563 } else { 2564 do_ept_access_op(op); 2565 if (ept_ad_enabled()) { 2566 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2567 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2568 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2569 if (i == 1) 2570 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2571 else 2572 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2573 } 2574 } 2575 2576 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2577 } 2578 2579 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2580 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2581 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2582 2583 skip_exit_vmcall(); 2584 } 2585 2586 static void ept_access_allowed_paddr(unsigned long ept_access, 2587 unsigned long pte_ad, 2588 enum ept_access_op op) 2589 { 2590 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2591 /*expected_qual=*/-1); 2592 } 2593 2594 static void ept_access_violation_paddr(unsigned long ept_access, 2595 unsigned long pte_ad, 2596 enum ept_access_op op, 2597 u64 expected_qual) 2598 { 2599 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2600 expected_qual); 2601 } 2602 2603 2604 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2605 unsigned long clear, 2606 unsigned long set, 2607 enum ept_access_op op) 2608 { 2609 struct ept_access_test_data *data = &ept_access_test_data; 2610 unsigned long orig_pte; 2611 2612 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2613 2614 /* No violation. Should proceed to vmcall. */ 2615 do_ept_access_op(op); 2616 skip_exit_vmcall(); 2617 2618 ept_untwiddle(data->gpa, level, orig_pte); 2619 } 2620 2621 static void ept_allowed_at_level(int level, unsigned long clear, 2622 unsigned long set, enum ept_access_op op) 2623 { 2624 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2625 if (ept_huge_pages_supported(level)) 2626 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2627 } 2628 2629 static void ept_allowed(unsigned long clear, unsigned long set, 2630 enum ept_access_op op) 2631 { 2632 ept_allowed_at_level(1, clear, set, op); 2633 ept_allowed_at_level(2, clear, set, op); 2634 ept_allowed_at_level(3, clear, set, op); 2635 ept_allowed_at_level(4, clear, set, op); 2636 } 2637 2638 static void ept_ignored_bit(int bit) 2639 { 2640 /* Set the bit. */ 2641 ept_allowed(0, 1ul << bit, OP_READ); 2642 ept_allowed(0, 1ul << bit, OP_WRITE); 2643 ept_allowed(0, 1ul << bit, OP_EXEC); 2644 2645 /* Clear the bit. */ 2646 ept_allowed(1ul << bit, 0, OP_READ); 2647 ept_allowed(1ul << bit, 0, OP_WRITE); 2648 ept_allowed(1ul << bit, 0, OP_EXEC); 2649 } 2650 2651 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2652 { 2653 ept_allowed(EPT_PRESENT, access, op); 2654 } 2655 2656 2657 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2658 unsigned long clear, 2659 unsigned long set, 2660 enum ept_access_op op) 2661 { 2662 struct ept_access_test_data *data = &ept_access_test_data; 2663 unsigned long orig_pte; 2664 2665 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2666 2667 do_ept_access_op(op); 2668 assert_exit_reason(VMX_EPT_MISCONFIG); 2669 2670 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2671 #if 0 2672 /* broken: */ 2673 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2674 #endif 2675 #if 0 2676 /* 2677 * broken: 2678 * According to description of exit qual for EPT violation, 2679 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2680 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2681 * to be set for msiconfig. 2682 */ 2683 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2684 (unsigned long) ( 2685 op == OP_EXEC ? data->gva + 1 : data->gva)); 2686 #endif 2687 2688 /* Fix the violation and resume the op loop. */ 2689 ept_untwiddle(data->gpa, level, orig_pte); 2690 enter_guest(); 2691 skip_exit_vmcall(); 2692 } 2693 2694 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2695 unsigned long clear, 2696 unsigned long set) 2697 { 2698 /* The op shouldn't matter (read, write, exec), so try them all! */ 2699 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2700 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2701 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2702 } 2703 2704 static void ept_misconfig_at_level(int level, unsigned long clear, 2705 unsigned long set) 2706 { 2707 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2708 if (ept_huge_pages_supported(level)) 2709 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2710 } 2711 2712 static void ept_misconfig(unsigned long clear, unsigned long set) 2713 { 2714 ept_misconfig_at_level(1, clear, set); 2715 ept_misconfig_at_level(2, clear, set); 2716 ept_misconfig_at_level(3, clear, set); 2717 ept_misconfig_at_level(4, clear, set); 2718 } 2719 2720 static void ept_access_misconfig(unsigned long access) 2721 { 2722 ept_misconfig(EPT_PRESENT, access); 2723 } 2724 2725 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2726 { 2727 /* Setting the bit causes a misconfig. */ 2728 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2729 2730 /* Making the entry non-present turns reserved bits into ignored. */ 2731 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2732 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2733 } 2734 2735 static void ept_reserved_bit_at_level_huge(int level, int bit) 2736 { 2737 /* Setting the bit causes a misconfig. */ 2738 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2739 2740 /* Making the entry non-present turns reserved bits into ignored. */ 2741 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2742 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2743 } 2744 2745 static void ept_reserved_bit_at_level(int level, int bit) 2746 { 2747 /* Setting the bit causes a misconfig. */ 2748 ept_misconfig_at_level(level, 0, 1ul << bit); 2749 2750 /* Making the entry non-present turns reserved bits into ignored. */ 2751 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2752 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2753 } 2754 2755 static void ept_reserved_bit(int bit) 2756 { 2757 ept_reserved_bit_at_level(1, bit); 2758 ept_reserved_bit_at_level(2, bit); 2759 ept_reserved_bit_at_level(3, bit); 2760 ept_reserved_bit_at_level(4, bit); 2761 } 2762 2763 #define PAGE_2M_ORDER 9 2764 #define PAGE_1G_ORDER 18 2765 2766 static void *get_1g_page(void) 2767 { 2768 static void *alloc; 2769 2770 if (!alloc) 2771 alloc = alloc_pages(PAGE_1G_ORDER); 2772 return alloc; 2773 } 2774 2775 static void ept_access_test_teardown(void *unused) 2776 { 2777 /* Exit the guest cleanly. */ 2778 do_ept_access_op(OP_EXIT); 2779 } 2780 2781 static void ept_access_test_guest(void) 2782 { 2783 struct ept_access_test_data *data = &ept_access_test_data; 2784 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2785 2786 while (true) { 2787 switch (data->op) { 2788 case OP_READ: 2789 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2790 break; 2791 case OP_WRITE: 2792 *data->gva = MAGIC_VAL_2; 2793 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2794 *data->gva = MAGIC_VAL_1; 2795 break; 2796 case OP_EXEC: 2797 TEST_ASSERT_EQ(42, code()); 2798 break; 2799 case OP_FLUSH_TLB: 2800 write_cr3(read_cr3()); 2801 break; 2802 case OP_EXIT: 2803 return; 2804 default: 2805 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2806 } 2807 vmcall(); 2808 } 2809 } 2810 2811 static void ept_access_test_setup(void) 2812 { 2813 struct ept_access_test_data *data = &ept_access_test_data; 2814 unsigned long npages = 1ul << PAGE_1G_ORDER; 2815 unsigned long size = npages * PAGE_SIZE; 2816 unsigned long *page_table = current_page_table(); 2817 unsigned long pte; 2818 2819 if (setup_ept(false)) 2820 test_skip("EPT not supported"); 2821 2822 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2823 if (cpuid_maxphyaddr() < 40) 2824 test_skip("Test needs MAXPHYADDR >= 40"); 2825 2826 test_set_guest(ept_access_test_guest); 2827 test_add_teardown(ept_access_test_teardown, NULL); 2828 2829 data->hva = get_1g_page(); 2830 TEST_ASSERT(data->hva); 2831 data->hpa = virt_to_phys(data->hva); 2832 2833 data->gpa = 1ul << 39; 2834 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2835 size); 2836 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2837 install_pages(page_table, data->gpa, size, data->gva); 2838 2839 /* 2840 * Make sure nothing's mapped here so the tests that screw with the 2841 * pml4 entry don't inadvertently break something. 2842 */ 2843 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2844 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2845 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2846 2847 data->hva[0] = MAGIC_VAL_1; 2848 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2849 } 2850 2851 static void ept_access_test_not_present(void) 2852 { 2853 ept_access_test_setup(); 2854 /* --- */ 2855 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2856 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2857 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2858 } 2859 2860 static void ept_access_test_read_only(void) 2861 { 2862 ept_access_test_setup(); 2863 2864 /* r-- */ 2865 ept_access_allowed(EPT_RA, OP_READ); 2866 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2867 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2868 } 2869 2870 static void ept_access_test_write_only(void) 2871 { 2872 ept_access_test_setup(); 2873 /* -w- */ 2874 ept_access_misconfig(EPT_WA); 2875 } 2876 2877 static void ept_access_test_read_write(void) 2878 { 2879 ept_access_test_setup(); 2880 /* rw- */ 2881 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2882 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2883 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2884 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2885 } 2886 2887 2888 static void ept_access_test_execute_only(void) 2889 { 2890 ept_access_test_setup(); 2891 /* --x */ 2892 if (ept_execute_only_supported()) { 2893 ept_access_violation(EPT_EA, OP_READ, 2894 EPT_VLT_RD | EPT_VLT_PERM_EX); 2895 ept_access_violation(EPT_EA, OP_WRITE, 2896 EPT_VLT_WR | EPT_VLT_PERM_EX); 2897 ept_access_allowed(EPT_EA, OP_EXEC); 2898 } else { 2899 ept_access_misconfig(EPT_EA); 2900 } 2901 } 2902 2903 static void ept_access_test_read_execute(void) 2904 { 2905 ept_access_test_setup(); 2906 /* r-x */ 2907 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2908 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2909 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2910 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2911 } 2912 2913 static void ept_access_test_write_execute(void) 2914 { 2915 ept_access_test_setup(); 2916 /* -wx */ 2917 ept_access_misconfig(EPT_WA | EPT_EA); 2918 } 2919 2920 static void ept_access_test_read_write_execute(void) 2921 { 2922 ept_access_test_setup(); 2923 /* rwx */ 2924 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2925 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2926 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2927 } 2928 2929 static void ept_access_test_reserved_bits(void) 2930 { 2931 int i; 2932 int maxphyaddr; 2933 2934 ept_access_test_setup(); 2935 2936 /* Reserved bits above maxphyaddr. */ 2937 maxphyaddr = cpuid_maxphyaddr(); 2938 for (i = maxphyaddr; i <= 51; i++) { 2939 report_prefix_pushf("reserved_bit=%d", i); 2940 ept_reserved_bit(i); 2941 report_prefix_pop(); 2942 } 2943 2944 /* Level-specific reserved bits. */ 2945 ept_reserved_bit_at_level_nohuge(2, 3); 2946 ept_reserved_bit_at_level_nohuge(2, 4); 2947 ept_reserved_bit_at_level_nohuge(2, 5); 2948 ept_reserved_bit_at_level_nohuge(2, 6); 2949 /* 2M alignment. */ 2950 for (i = 12; i < 20; i++) { 2951 report_prefix_pushf("reserved_bit=%d", i); 2952 ept_reserved_bit_at_level_huge(2, i); 2953 report_prefix_pop(); 2954 } 2955 ept_reserved_bit_at_level_nohuge(3, 3); 2956 ept_reserved_bit_at_level_nohuge(3, 4); 2957 ept_reserved_bit_at_level_nohuge(3, 5); 2958 ept_reserved_bit_at_level_nohuge(3, 6); 2959 /* 1G alignment. */ 2960 for (i = 12; i < 29; i++) { 2961 report_prefix_pushf("reserved_bit=%d", i); 2962 ept_reserved_bit_at_level_huge(3, i); 2963 report_prefix_pop(); 2964 } 2965 ept_reserved_bit_at_level(4, 3); 2966 ept_reserved_bit_at_level(4, 4); 2967 ept_reserved_bit_at_level(4, 5); 2968 ept_reserved_bit_at_level(4, 6); 2969 ept_reserved_bit_at_level(4, 7); 2970 } 2971 2972 static void ept_access_test_ignored_bits(void) 2973 { 2974 ept_access_test_setup(); 2975 /* 2976 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2977 * far as translation is concerned even if AD bits are enabled in the 2978 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2979 * control is 0. 2980 */ 2981 ept_ignored_bit(8); 2982 ept_ignored_bit(9); 2983 ept_ignored_bit(10); 2984 ept_ignored_bit(11); 2985 ept_ignored_bit(52); 2986 ept_ignored_bit(53); 2987 ept_ignored_bit(54); 2988 ept_ignored_bit(55); 2989 ept_ignored_bit(56); 2990 ept_ignored_bit(57); 2991 ept_ignored_bit(58); 2992 ept_ignored_bit(59); 2993 ept_ignored_bit(60); 2994 ept_ignored_bit(61); 2995 ept_ignored_bit(62); 2996 ept_ignored_bit(63); 2997 } 2998 2999 static void ept_access_test_paddr_not_present_ad_disabled(void) 3000 { 3001 ept_access_test_setup(); 3002 ept_disable_ad_bits(); 3003 3004 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3005 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3006 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3007 } 3008 3009 static void ept_access_test_paddr_not_present_ad_enabled(void) 3010 { 3011 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3012 3013 ept_access_test_setup(); 3014 ept_enable_ad_bits_or_skip_test(); 3015 3016 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3017 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3018 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3019 } 3020 3021 static void ept_access_test_paddr_read_only_ad_disabled(void) 3022 { 3023 /* 3024 * When EPT AD bits are disabled, all accesses to guest paging 3025 * structures are reported separately as a read and (after 3026 * translation of the GPA to host physical address) a read+write 3027 * if the A/D bits have to be set. 3028 */ 3029 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3030 3031 ept_access_test_setup(); 3032 ept_disable_ad_bits(); 3033 3034 /* Can't update A bit, so all accesses fail. */ 3035 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3036 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3037 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3038 /* AD bits disabled, so only writes try to update the D bit. */ 3039 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3040 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3041 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3042 /* Both A and D already set, so read-only is OK. */ 3043 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3044 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3045 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3046 } 3047 3048 static void ept_access_test_paddr_read_only_ad_enabled(void) 3049 { 3050 /* 3051 * When EPT AD bits are enabled, all accesses to guest paging 3052 * structures are considered writes as far as EPT translation 3053 * is concerned. 3054 */ 3055 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3056 3057 ept_access_test_setup(); 3058 ept_enable_ad_bits_or_skip_test(); 3059 3060 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3063 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3064 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3065 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3066 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3069 } 3070 3071 static void ept_access_test_paddr_read_write(void) 3072 { 3073 ept_access_test_setup(); 3074 /* Read-write access to paging structure. */ 3075 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3076 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3077 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3078 } 3079 3080 static void ept_access_test_paddr_read_write_execute(void) 3081 { 3082 ept_access_test_setup(); 3083 /* RWX access to paging structure. */ 3084 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3085 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3086 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3087 } 3088 3089 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3090 { 3091 /* 3092 * When EPT AD bits are disabled, all accesses to guest paging 3093 * structures are reported separately as a read and (after 3094 * translation of the GPA to host physical address) a read+write 3095 * if the A/D bits have to be set. 3096 */ 3097 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3098 3099 ept_access_test_setup(); 3100 ept_disable_ad_bits(); 3101 3102 /* Can't update A bit, so all accesses fail. */ 3103 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3104 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3105 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3106 /* AD bits disabled, so only writes try to update the D bit. */ 3107 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3108 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3109 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3110 /* Both A and D already set, so read-only is OK. */ 3111 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3112 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3113 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3114 } 3115 3116 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3117 { 3118 /* 3119 * When EPT AD bits are enabled, all accesses to guest paging 3120 * structures are considered writes as far as EPT translation 3121 * is concerned. 3122 */ 3123 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3124 3125 ept_access_test_setup(); 3126 ept_enable_ad_bits_or_skip_test(); 3127 3128 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3129 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3130 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3131 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3132 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3133 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3134 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3135 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3137 } 3138 3139 static void ept_access_test_paddr_not_present_page_fault(void) 3140 { 3141 ept_access_test_setup(); 3142 /* 3143 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3144 * page is read-only in EPT but GVA is also mapped read only in PT. 3145 * Thus guest page fault before host takes EPT violation for trying to 3146 * update A bit. 3147 */ 3148 } 3149 3150 static void ept_access_test_force_2m_page(void) 3151 { 3152 ept_access_test_setup(); 3153 3154 TEST_ASSERT_EQ(ept_2m_supported(), true); 3155 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3156 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3157 EPT_VLT_WR | EPT_VLT_PERM_RD | 3158 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3159 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3160 } 3161 3162 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3163 { 3164 if (!is_invvpid_type_supported(type)) 3165 return false; 3166 3167 if (vpid >> 16) 3168 return false; 3169 3170 if (type != INVVPID_ALL && !vpid) 3171 return false; 3172 3173 if (type == INVVPID_ADDR && !is_canonical(gla)) 3174 return false; 3175 3176 return true; 3177 } 3178 3179 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3180 { 3181 int rc; 3182 bool valid = invvpid_valid(type, vpid, gla); 3183 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3184 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3185 /* 3186 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3187 * that we can tell if it is updated by INVVPID. 3188 */ 3189 vmcs_read(~0); 3190 rc = __invvpid(type, vpid, gla); 3191 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3192 vpid, gla, 3193 valid ? "passes" : "fails"); 3194 report(vmcs_read(VMX_INST_ERROR) == expected, 3195 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3196 rc ? "failed" : "successful", 3197 expected, vmcs_read(VMX_INST_ERROR)); 3198 } 3199 3200 static inline unsigned long get_first_supported_invvpid_type(void) 3201 { 3202 u64 type = ffs(ept_vpid.val >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3203 3204 __TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3205 return type; 3206 } 3207 3208 static void ds_invvpid(void *data) 3209 { 3210 asm volatile("invvpid %0, %1" 3211 : 3212 : "m"(*(struct invvpid_operand *)data), 3213 "r"(get_first_supported_invvpid_type())); 3214 } 3215 3216 /* 3217 * The SS override is ignored in 64-bit mode, so we use an addressing 3218 * mode with %rsp as the base register to generate an implicit SS 3219 * reference. 3220 */ 3221 static void ss_invvpid(void *data) 3222 { 3223 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3224 : "+r"(data) 3225 : "r"(get_first_supported_invvpid_type())); 3226 } 3227 3228 static void invvpid_test_gp(void) 3229 { 3230 bool fault; 3231 3232 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3233 (void *)NONCANONICAL); 3234 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3235 } 3236 3237 static void invvpid_test_ss(void) 3238 { 3239 bool fault; 3240 3241 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3242 (void *)NONCANONICAL); 3243 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3244 } 3245 3246 static void invvpid_test_pf(void) 3247 { 3248 void *vpage = alloc_vpage(); 3249 bool fault; 3250 3251 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3252 report(fault, "INVVPID with unmapped operand raises #PF"); 3253 } 3254 3255 static void try_compat_invvpid(void *unused) 3256 { 3257 struct far_pointer32 fp = { 3258 .offset = (uintptr_t)&&invvpid, 3259 .selector = KERNEL_CS32, 3260 }; 3261 uintptr_t rsp; 3262 3263 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3264 3265 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3266 "Code address too high."); 3267 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3268 3269 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3270 return; 3271 invvpid: 3272 asm volatile (".code32;" 3273 "invvpid (%eax), %eax;" 3274 "lret;" 3275 ".code64"); 3276 __builtin_unreachable(); 3277 } 3278 3279 static void invvpid_test_compatibility_mode(void) 3280 { 3281 bool fault; 3282 3283 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3284 report(fault, "Compatibility mode INVVPID raises #UD"); 3285 } 3286 3287 static void invvpid_test_not_in_vmx_operation(void) 3288 { 3289 bool fault; 3290 3291 TEST_ASSERT(!vmx_off()); 3292 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3293 report(fault, "INVVPID outside of VMX operation raises #UD"); 3294 TEST_ASSERT(!vmx_on()); 3295 } 3296 3297 /* 3298 * This does not test real-address mode, virtual-8086 mode, protected mode, 3299 * or CPL > 0. 3300 */ 3301 static void invvpid_test(void) 3302 { 3303 int i; 3304 unsigned types = 0; 3305 unsigned type; 3306 3307 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3308 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3309 test_skip("VPID not supported"); 3310 3311 if (!is_invvpid_supported()) 3312 test_skip("INVVPID not supported.\n"); 3313 3314 if (is_invvpid_type_supported(INVVPID_ADDR)) 3315 types |= 1u << INVVPID_ADDR; 3316 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3317 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3318 if (is_invvpid_type_supported(INVVPID_ALL)) 3319 types |= 1u << INVVPID_ALL; 3320 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3321 types |= 1u << INVVPID_CONTEXT_LOCAL; 3322 3323 if (!types) 3324 test_skip("No INVVPID types supported.\n"); 3325 3326 for (i = -127; i < 128; i++) 3327 try_invvpid(i, 0xffff, 0); 3328 3329 /* 3330 * VPID must not be more than 16 bits. 3331 */ 3332 for (i = 0; i < 64; i++) 3333 for (type = 0; type < 4; type++) 3334 if (types & (1u << type)) 3335 try_invvpid(type, 1ul << i, 0); 3336 3337 /* 3338 * VPID must not be zero, except for "all contexts." 3339 */ 3340 for (type = 0; type < 4; type++) 3341 if (types & (1u << type)) 3342 try_invvpid(type, 0, 0); 3343 3344 /* 3345 * The gla operand is only validated for single-address INVVPID. 3346 */ 3347 if (types & (1u << INVVPID_ADDR)) 3348 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3349 3350 invvpid_test_gp(); 3351 invvpid_test_ss(); 3352 invvpid_test_pf(); 3353 invvpid_test_compatibility_mode(); 3354 invvpid_test_not_in_vmx_operation(); 3355 } 3356 3357 /* 3358 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3359 * at least as far as the guest-state checks. Returns false if the 3360 * VMLAUNCH fails early and execution falls through to the next 3361 * instruction. 3362 */ 3363 static bool vmlaunch_succeeds(void) 3364 { 3365 u32 exit_reason; 3366 3367 /* 3368 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3369 * unsupported VMCS component"). The caller can then check 3370 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3371 */ 3372 vmcs_write(~0u, 0); 3373 3374 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3375 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3376 : 3377 : "r" ((u64)HOST_RSP) 3378 : "cc", "memory" 3379 : success); 3380 return false; 3381 success: 3382 exit_reason = vmcs_read(EXI_REASON); 3383 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3384 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3385 return true; 3386 } 3387 3388 /* 3389 * Try to launch the current VMCS. 3390 */ 3391 static void test_vmx_vmlaunch(u32 xerror) 3392 { 3393 bool success = vmlaunch_succeeds(); 3394 u32 vmx_inst_err; 3395 3396 report(success == !xerror, "vmlaunch %s", 3397 !xerror ? "succeeds" : "fails"); 3398 if (!success && xerror) { 3399 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3400 report(vmx_inst_err == xerror, 3401 "VMX inst error is %d (actual %d)", xerror, 3402 vmx_inst_err); 3403 } 3404 } 3405 3406 /* 3407 * Try to launch the current VMCS, and expect one of two possible 3408 * errors (or success) codes. 3409 */ 3410 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3411 { 3412 bool success = vmlaunch_succeeds(); 3413 u32 vmx_inst_err; 3414 3415 if (!xerror1 == !xerror2) 3416 report(success == !xerror1, "vmlaunch %s", 3417 !xerror1 ? "succeeds" : "fails"); 3418 3419 if (!success && (xerror1 || xerror2)) { 3420 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3421 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3422 "VMX inst error is %d or %d (actual %d)", xerror1, 3423 xerror2, vmx_inst_err); 3424 } 3425 } 3426 3427 static void test_vmx_invalid_controls(void) 3428 { 3429 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3430 } 3431 3432 static void test_vmx_valid_controls(void) 3433 { 3434 test_vmx_vmlaunch(0); 3435 } 3436 3437 /* 3438 * Test a particular value of a VM-execution control bit, if the value 3439 * is required or if the value is zero. 3440 */ 3441 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3442 enum Encoding encoding, unsigned bit, 3443 unsigned val) 3444 { 3445 u32 mask = 1u << bit; 3446 bool expected; 3447 u32 controls; 3448 3449 if (msr.set & mask) 3450 TEST_ASSERT(msr.clr & mask); 3451 3452 /* 3453 * We can't arbitrarily turn on a control bit, because it may 3454 * introduce dependencies on other VMCS fields. So, we only 3455 * test turning on bits that have a required setting. 3456 */ 3457 if (val && (msr.clr & mask) && !(msr.set & mask)) 3458 return; 3459 3460 report_prefix_pushf("%s %s bit %d", 3461 val ? "Set" : "Clear", name, bit); 3462 3463 controls = vmcs_read(encoding); 3464 if (val) { 3465 vmcs_write(encoding, msr.set | mask); 3466 expected = (msr.clr & mask); 3467 } else { 3468 vmcs_write(encoding, msr.set & ~mask); 3469 expected = !(msr.set & mask); 3470 } 3471 if (expected) 3472 test_vmx_valid_controls(); 3473 else 3474 test_vmx_invalid_controls(); 3475 vmcs_write(encoding, controls); 3476 report_prefix_pop(); 3477 } 3478 3479 /* 3480 * Test reserved values of a VM-execution control bit, based on the 3481 * allowed bit settings from the corresponding VMX capability MSR. 3482 */ 3483 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3484 enum Encoding encoding, unsigned bit) 3485 { 3486 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3487 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3488 } 3489 3490 /* 3491 * Reserved bits in the pin-based VM-execution controls must be set 3492 * properly. Software may consult the VMX capability MSRs to determine 3493 * the proper settings. 3494 * [Intel SDM] 3495 */ 3496 static void test_pin_based_ctls(void) 3497 { 3498 unsigned bit; 3499 3500 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3501 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3502 for (bit = 0; bit < 32; bit++) 3503 test_rsvd_ctl_bit("pin-based controls", 3504 ctrl_pin_rev, PIN_CONTROLS, bit); 3505 } 3506 3507 /* 3508 * Reserved bits in the primary processor-based VM-execution controls 3509 * must be set properly. Software may consult the VMX capability MSRs 3510 * to determine the proper settings. 3511 * [Intel SDM] 3512 */ 3513 static void test_primary_processor_based_ctls(void) 3514 { 3515 unsigned bit; 3516 3517 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3518 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3519 for (bit = 0; bit < 32; bit++) 3520 test_rsvd_ctl_bit("primary processor-based controls", 3521 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3522 } 3523 3524 /* 3525 * If the "activate secondary controls" primary processor-based 3526 * VM-execution control is 1, reserved bits in the secondary 3527 * processor-based VM-execution controls must be cleared. Software may 3528 * consult the VMX capability MSRs to determine which bits are 3529 * reserved. 3530 * If the "activate secondary controls" primary processor-based 3531 * VM-execution control is 0 (or if the processor does not support the 3532 * 1-setting of that control), no checks are performed on the 3533 * secondary processor-based VM-execution controls. 3534 * [Intel SDM] 3535 */ 3536 static void test_secondary_processor_based_ctls(void) 3537 { 3538 u32 primary; 3539 u32 secondary; 3540 unsigned bit; 3541 3542 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3543 return; 3544 3545 primary = vmcs_read(CPU_EXEC_CTRL0); 3546 secondary = vmcs_read(CPU_EXEC_CTRL1); 3547 3548 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3549 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3550 for (bit = 0; bit < 32; bit++) 3551 test_rsvd_ctl_bit("secondary processor-based controls", 3552 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3553 3554 /* 3555 * When the "activate secondary controls" VM-execution control 3556 * is clear, there are no checks on the secondary controls. 3557 */ 3558 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3559 vmcs_write(CPU_EXEC_CTRL1, ~0); 3560 report(vmlaunch_succeeds(), 3561 "Secondary processor-based controls ignored"); 3562 vmcs_write(CPU_EXEC_CTRL1, secondary); 3563 vmcs_write(CPU_EXEC_CTRL0, primary); 3564 } 3565 3566 static void try_cr3_target_count(unsigned i, unsigned max) 3567 { 3568 report_prefix_pushf("CR3 target count 0x%x", i); 3569 vmcs_write(CR3_TARGET_COUNT, i); 3570 if (i <= max) 3571 test_vmx_valid_controls(); 3572 else 3573 test_vmx_invalid_controls(); 3574 report_prefix_pop(); 3575 } 3576 3577 /* 3578 * The CR3-target count must not be greater than 4. Future processors 3579 * may support a different number of CR3-target values. Software 3580 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3581 * number of values supported. 3582 * [Intel SDM] 3583 */ 3584 static void test_cr3_targets(void) 3585 { 3586 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3587 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3588 unsigned i; 3589 3590 printf("\nSupported CR3 targets: %d\n", supported_targets); 3591 TEST_ASSERT(supported_targets <= 256); 3592 3593 try_cr3_target_count(-1u, supported_targets); 3594 try_cr3_target_count(0x80000000, supported_targets); 3595 try_cr3_target_count(0x7fffffff, supported_targets); 3596 for (i = 0; i <= supported_targets + 1; i++) 3597 try_cr3_target_count(i, supported_targets); 3598 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3599 3600 /* VMWRITE to nonexistent target fields should fail. */ 3601 for (i = supported_targets; i < 256; i++) 3602 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3603 } 3604 3605 /* 3606 * Test a particular address setting in the VMCS 3607 */ 3608 static void test_vmcs_addr(const char *name, 3609 enum Encoding encoding, 3610 u64 align, 3611 bool ignored, 3612 bool skip_beyond_mapped_ram, 3613 u64 addr) 3614 { 3615 report_prefix_pushf("%s = %lx", name, addr); 3616 vmcs_write(encoding, addr); 3617 if (skip_beyond_mapped_ram && 3618 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3619 addr < (1ul << cpuid_maxphyaddr())) 3620 printf("Skipping physical address beyond mapped RAM\n"); 3621 else if (ignored || (IS_ALIGNED(addr, align) && 3622 addr < (1ul << cpuid_maxphyaddr()))) 3623 test_vmx_valid_controls(); 3624 else 3625 test_vmx_invalid_controls(); 3626 report_prefix_pop(); 3627 } 3628 3629 /* 3630 * Test interesting values for a VMCS address 3631 */ 3632 static void test_vmcs_addr_values(const char *name, 3633 enum Encoding encoding, 3634 u64 align, 3635 bool ignored, 3636 bool skip_beyond_mapped_ram, 3637 u32 bit_start, u32 bit_end) 3638 { 3639 unsigned i; 3640 u64 orig_val = vmcs_read(encoding); 3641 3642 for (i = bit_start; i <= bit_end; i++) 3643 test_vmcs_addr(name, encoding, align, ignored, 3644 skip_beyond_mapped_ram, 1ul << i); 3645 3646 test_vmcs_addr(name, encoding, align, ignored, 3647 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3648 test_vmcs_addr(name, encoding, align, ignored, 3649 skip_beyond_mapped_ram, PAGE_SIZE); 3650 test_vmcs_addr(name, encoding, align, ignored, 3651 skip_beyond_mapped_ram, 3652 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3653 test_vmcs_addr(name, encoding, align, ignored, 3654 skip_beyond_mapped_ram, -1ul); 3655 3656 vmcs_write(encoding, orig_val); 3657 } 3658 3659 /* 3660 * Test a physical address reference in the VMCS, when the corresponding 3661 * feature is enabled and when the corresponding feature is disabled. 3662 */ 3663 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3664 const char *field_name, 3665 const char *control_name, u64 align, 3666 bool skip_beyond_mapped_ram, 3667 bool control_primary) 3668 { 3669 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3670 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3671 u64 page_addr; 3672 3673 if (control_primary) { 3674 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3675 return; 3676 } else { 3677 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3678 return; 3679 } 3680 3681 page_addr = vmcs_read(field); 3682 3683 report_prefix_pushf("%s enabled", control_name); 3684 if (control_primary) { 3685 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3686 } else { 3687 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3688 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3689 } 3690 3691 test_vmcs_addr_values(field_name, field, align, false, 3692 skip_beyond_mapped_ram, 0, 63); 3693 report_prefix_pop(); 3694 3695 report_prefix_pushf("%s disabled", control_name); 3696 if (control_primary) { 3697 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3698 } else { 3699 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3700 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3701 } 3702 3703 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3704 report_prefix_pop(); 3705 3706 vmcs_write(field, page_addr); 3707 vmcs_write(CPU_EXEC_CTRL0, primary); 3708 vmcs_write(CPU_EXEC_CTRL1, secondary); 3709 } 3710 3711 /* 3712 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3713 * each I/O-bitmap address must be 0. Neither address should set any 3714 * bits beyond the processor's physical-address width. 3715 * [Intel SDM] 3716 */ 3717 static void test_io_bitmaps(void) 3718 { 3719 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3720 "I/O bitmap A", "Use I/O bitmaps", 3721 PAGE_SIZE, false, true); 3722 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3723 "I/O bitmap B", "Use I/O bitmaps", 3724 PAGE_SIZE, false, true); 3725 } 3726 3727 /* 3728 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3729 * the MSR-bitmap address must be 0. The address should not set any 3730 * bits beyond the processor's physical-address width. 3731 * [Intel SDM] 3732 */ 3733 static void test_msr_bitmap(void) 3734 { 3735 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3736 "MSR bitmap", "Use MSR bitmaps", 3737 PAGE_SIZE, false, true); 3738 } 3739 3740 /* 3741 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3742 * address must satisfy the following checks: 3743 * - Bits 11:0 of the address must be 0. 3744 * - The address should not set any bits beyond the processor's 3745 * physical-address width. 3746 * [Intel SDM] 3747 */ 3748 static void test_apic_virt_addr(void) 3749 { 3750 /* 3751 * Ensure the processor will never use the virtual-APIC page, since 3752 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3753 * what we're trying to achieve and fails vmentry. 3754 */ 3755 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3756 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3757 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3758 "virtual-APIC address", "Use TPR shadow", 3759 PAGE_SIZE, false, true); 3760 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3761 } 3762 3763 /* 3764 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3765 * APIC-access address must satisfy the following checks: 3766 * - Bits 11:0 of the address must be 0. 3767 * - The address should not set any bits beyond the processor's 3768 * physical-address width. 3769 * [Intel SDM] 3770 */ 3771 static void test_apic_access_addr(void) 3772 { 3773 void *apic_access_page = alloc_page(); 3774 3775 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3776 3777 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3778 "APIC-access address", 3779 "virtualize APIC-accesses", PAGE_SIZE, 3780 true, false); 3781 } 3782 3783 static bool set_bit_pattern(u8 mask, u32 *secondary) 3784 { 3785 u8 i; 3786 bool flag = false; 3787 u32 test_bits[3] = { 3788 CPU_VIRT_X2APIC, 3789 CPU_APIC_REG_VIRT, 3790 CPU_VINTD 3791 }; 3792 3793 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3794 if ((mask & (1u << i)) && 3795 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3796 *secondary |= test_bits[i]; 3797 flag = true; 3798 } 3799 } 3800 3801 return (flag); 3802 } 3803 3804 /* 3805 * If the "use TPR shadow" VM-execution control is 0, the following 3806 * VM-execution controls must also be 0: 3807 * - virtualize x2APIC mode 3808 * - APIC-register virtualization 3809 * - virtual-interrupt delivery 3810 * [Intel SDM] 3811 * 3812 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3813 * "virtualize APIC accesses" VM-execution control must be 0. 3814 * [Intel SDM] 3815 */ 3816 static void test_apic_virtual_ctls(void) 3817 { 3818 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3819 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3820 u32 primary = saved_primary; 3821 u32 secondary = saved_secondary; 3822 bool ctrl = false; 3823 char str[10] = "disabled"; 3824 u8 i = 0, j; 3825 3826 /* 3827 * First test 3828 */ 3829 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3830 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3831 return; 3832 3833 primary |= CPU_SECONDARY; 3834 primary &= ~CPU_TPR_SHADOW; 3835 vmcs_write(CPU_EXEC_CTRL0, primary); 3836 3837 while (1) { 3838 for (j = 1; j < 8; j++) { 3839 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3840 if (primary & CPU_TPR_SHADOW) { 3841 ctrl = true; 3842 } else { 3843 if (! set_bit_pattern(j, &secondary)) 3844 ctrl = true; 3845 else 3846 ctrl = false; 3847 } 3848 3849 vmcs_write(CPU_EXEC_CTRL1, secondary); 3850 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3851 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3852 if (ctrl) 3853 test_vmx_valid_controls(); 3854 else 3855 test_vmx_invalid_controls(); 3856 report_prefix_pop(); 3857 } 3858 3859 if (i == 1) 3860 break; 3861 i++; 3862 3863 primary |= CPU_TPR_SHADOW; 3864 vmcs_write(CPU_EXEC_CTRL0, primary); 3865 strcpy(str, "enabled"); 3866 } 3867 3868 /* 3869 * Second test 3870 */ 3871 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3872 3873 primary = saved_primary; 3874 secondary = saved_secondary; 3875 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3876 return; 3877 3878 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3879 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3880 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3881 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3882 test_vmx_valid_controls(); 3883 report_prefix_pop(); 3884 3885 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3886 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3887 test_vmx_valid_controls(); 3888 report_prefix_pop(); 3889 3890 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3891 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3892 test_vmx_invalid_controls(); 3893 report_prefix_pop(); 3894 3895 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3896 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3897 test_vmx_valid_controls(); 3898 report_prefix_pop(); 3899 3900 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3901 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3902 } 3903 3904 /* 3905 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3906 * "external-interrupt exiting" VM-execution control must be 1. 3907 * [Intel SDM] 3908 */ 3909 static void test_virtual_intr_ctls(void) 3910 { 3911 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3912 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3913 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3914 u32 primary = saved_primary; 3915 u32 secondary = saved_secondary; 3916 u32 pin = saved_pin; 3917 3918 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3919 (ctrl_pin_rev.clr & PIN_EXTINT))) 3920 return; 3921 3922 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3923 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3924 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3925 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3926 test_vmx_valid_controls(); 3927 report_prefix_pop(); 3928 3929 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3930 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3931 test_vmx_invalid_controls(); 3932 report_prefix_pop(); 3933 3934 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3935 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3936 test_vmx_valid_controls(); 3937 report_prefix_pop(); 3938 3939 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3940 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3941 test_vmx_invalid_controls(); 3942 report_prefix_pop(); 3943 3944 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3945 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3946 vmcs_write(PIN_CONTROLS, saved_pin); 3947 } 3948 3949 static void test_pi_desc_addr(u64 addr, bool ctrl) 3950 { 3951 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3952 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3953 if (ctrl) 3954 test_vmx_valid_controls(); 3955 else 3956 test_vmx_invalid_controls(); 3957 report_prefix_pop(); 3958 } 3959 3960 /* 3961 * If the "process posted interrupts" VM-execution control is 1, the 3962 * following must be true: 3963 * 3964 * - The "virtual-interrupt delivery" VM-execution control is 1. 3965 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3966 * - The posted-interrupt notification vector has a value in the 3967 * - range 0 - 255 (bits 15:8 are all 0). 3968 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3969 * - The posted-interrupt descriptor address does not set any bits 3970 * beyond the processor's physical-address width. 3971 * [Intel SDM] 3972 */ 3973 static void test_posted_intr(void) 3974 { 3975 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3976 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3977 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3978 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3979 u32 primary = saved_primary; 3980 u32 secondary = saved_secondary; 3981 u32 pin = saved_pin; 3982 u32 exit_ctl = exit_ctl_saved; 3983 u16 vec; 3984 int i; 3985 3986 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3987 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3988 (ctrl_exit_rev.clr & EXI_INTA))) 3989 return; 3990 3991 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3992 3993 /* 3994 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3995 */ 3996 pin |= PIN_POST_INTR; 3997 vmcs_write(PIN_CONTROLS, pin); 3998 secondary &= ~CPU_VINTD; 3999 vmcs_write(CPU_EXEC_CTRL1, secondary); 4000 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4001 test_vmx_invalid_controls(); 4002 report_prefix_pop(); 4003 4004 secondary |= CPU_VINTD; 4005 vmcs_write(CPU_EXEC_CTRL1, secondary); 4006 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4007 test_vmx_invalid_controls(); 4008 report_prefix_pop(); 4009 4010 exit_ctl &= ~EXI_INTA; 4011 vmcs_write(EXI_CONTROLS, exit_ctl); 4012 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4013 test_vmx_invalid_controls(); 4014 report_prefix_pop(); 4015 4016 exit_ctl |= EXI_INTA; 4017 vmcs_write(EXI_CONTROLS, exit_ctl); 4018 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4019 test_vmx_valid_controls(); 4020 report_prefix_pop(); 4021 4022 secondary &= ~CPU_VINTD; 4023 vmcs_write(CPU_EXEC_CTRL1, secondary); 4024 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4025 test_vmx_invalid_controls(); 4026 report_prefix_pop(); 4027 4028 secondary |= CPU_VINTD; 4029 vmcs_write(CPU_EXEC_CTRL1, secondary); 4030 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4031 test_vmx_valid_controls(); 4032 report_prefix_pop(); 4033 4034 /* 4035 * Test posted-interrupt notification vector 4036 */ 4037 for (i = 0; i < 8; i++) { 4038 vec = (1ul << i); 4039 vmcs_write(PINV, vec); 4040 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4041 test_vmx_valid_controls(); 4042 report_prefix_pop(); 4043 } 4044 for (i = 8; i < 16; i++) { 4045 vec = (1ul << i); 4046 vmcs_write(PINV, vec); 4047 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4048 test_vmx_invalid_controls(); 4049 report_prefix_pop(); 4050 } 4051 4052 vec &= ~(0xff << 8); 4053 vmcs_write(PINV, vec); 4054 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4055 test_vmx_valid_controls(); 4056 report_prefix_pop(); 4057 4058 /* 4059 * Test posted-interrupt descriptor addresss 4060 */ 4061 for (i = 0; i < 6; i++) { 4062 test_pi_desc_addr(1ul << i, false); 4063 } 4064 4065 test_pi_desc_addr(0xf0, false); 4066 test_pi_desc_addr(0xff, false); 4067 test_pi_desc_addr(0x0f, false); 4068 test_pi_desc_addr(0x8000, true); 4069 test_pi_desc_addr(0x00, true); 4070 test_pi_desc_addr(0xc000, true); 4071 4072 test_vmcs_addr_values("process-posted interrupts", 4073 POSTED_INTR_DESC_ADDR, 64, 4074 false, false, 0, 63); 4075 4076 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4077 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4078 vmcs_write(PIN_CONTROLS, saved_pin); 4079 } 4080 4081 static void test_apic_ctls(void) 4082 { 4083 test_apic_virt_addr(); 4084 test_apic_access_addr(); 4085 test_apic_virtual_ctls(); 4086 test_virtual_intr_ctls(); 4087 test_posted_intr(); 4088 } 4089 4090 /* 4091 * If the "enable VPID" VM-execution control is 1, the value of the 4092 * of the VPID VM-execution control field must not be 0000H. 4093 * [Intel SDM] 4094 */ 4095 static void test_vpid(void) 4096 { 4097 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4098 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4099 u16 vpid = 0x0000; 4100 int i; 4101 4102 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4103 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4104 printf("Secondary controls and/or VPID not supported\n"); 4105 return; 4106 } 4107 4108 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4109 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4110 vmcs_write(VPID, vpid); 4111 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4112 test_vmx_valid_controls(); 4113 report_prefix_pop(); 4114 4115 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4116 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4117 test_vmx_invalid_controls(); 4118 report_prefix_pop(); 4119 4120 for (i = 0; i < 16; i++) { 4121 vpid = (short)1 << i;; 4122 vmcs_write(VPID, vpid); 4123 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4124 test_vmx_valid_controls(); 4125 report_prefix_pop(); 4126 } 4127 4128 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4129 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4130 } 4131 4132 static void set_vtpr(unsigned vtpr) 4133 { 4134 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4135 } 4136 4137 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4138 { 4139 bool valid = true; 4140 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4141 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4142 4143 if ((primary & CPU_TPR_SHADOW) && 4144 (!(primary & CPU_SECONDARY) || 4145 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4146 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4147 4148 set_vtpr(vtpr); 4149 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4150 threshold, (vtpr >> 4) & 0xf); 4151 if (valid) 4152 test_vmx_valid_controls(); 4153 else 4154 test_vmx_invalid_controls(); 4155 report_prefix_pop(); 4156 } 4157 4158 static void test_invalid_event_injection(void) 4159 { 4160 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4161 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4162 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4163 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4164 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4165 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4166 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4167 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4168 u32 cnt; 4169 4170 /* Setup */ 4171 report_prefix_push("invalid event injection"); 4172 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4173 vmcs_write(ENT_INST_LEN, 0x00000001); 4174 4175 /* The field's interruption type is not set to a reserved value. */ 4176 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4177 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4178 "RESERVED interruption type invalid [-]", 4179 ent_intr_info); 4180 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4181 test_vmx_invalid_controls(); 4182 report_prefix_pop(); 4183 4184 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4185 DE_VECTOR; 4186 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4187 "RESERVED interruption type invalid [+]", 4188 ent_intr_info); 4189 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4190 test_vmx_valid_controls(); 4191 report_prefix_pop(); 4192 4193 /* If the interruption type is other event, the vector is 0. */ 4194 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4195 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4196 "(OTHER EVENT && vector != 0) invalid [-]", 4197 ent_intr_info); 4198 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4199 test_vmx_invalid_controls(); 4200 report_prefix_pop(); 4201 4202 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4203 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4204 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4205 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4206 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4207 test_vmx_invalid_controls(); 4208 report_prefix_pop(); 4209 4210 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4211 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4212 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4213 "(NMI && vector == 2) valid [+]", ent_intr_info); 4214 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4215 test_vmx_valid_controls(); 4216 report_prefix_pop(); 4217 4218 /* 4219 * If the interruption type 4220 * is HW exception, the vector is at most 31. 4221 */ 4222 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4223 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4224 "(HW exception && vector > 31) invalid [-]", 4225 ent_intr_info); 4226 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4227 test_vmx_invalid_controls(); 4228 report_prefix_pop(); 4229 4230 /* 4231 * deliver-error-code is 1 iff either 4232 * (a) the "unrestricted guest" VM-execution control is 0 4233 * (b) CR0.PE is set. 4234 */ 4235 4236 /* Assert that unrestricted guest is disabled or unsupported */ 4237 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4238 !(secondary_save & CPU_URG)); 4239 4240 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4241 GP_VECTOR; 4242 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4243 "error code <-> (!URG || prot_mode) [-]", 4244 ent_intr_info); 4245 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4246 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4247 test_vmx_invalid_controls(); 4248 report_prefix_pop(); 4249 4250 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4251 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4252 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4253 "error code <-> (!URG || prot_mode) [+]", 4254 ent_intr_info); 4255 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4256 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4257 test_vmx_valid_controls(); 4258 report_prefix_pop(); 4259 4260 if (enable_unrestricted_guest(false)) 4261 goto skip_unrestricted_guest; 4262 4263 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4264 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4265 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4266 "error code <-> (!URG || prot_mode) [-]", 4267 ent_intr_info); 4268 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4269 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4270 test_vmx_invalid_controls(); 4271 report_prefix_pop(); 4272 4273 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4274 GP_VECTOR; 4275 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4276 "error code <-> (!URG || prot_mode) [-]", 4277 ent_intr_info); 4278 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4279 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4280 test_vmx_invalid_controls(); 4281 report_prefix_pop(); 4282 4283 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4284 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4285 4286 skip_unrestricted_guest: 4287 vmcs_write(GUEST_CR0, guest_cr0_save); 4288 4289 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4290 report_prefix_push("error code <-> HW exception"); 4291 for (cnt = 0; cnt < 8; cnt++) { 4292 u32 exception_type_mask = cnt << 8; 4293 u32 deliver_error_code_mask = 4294 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4295 INTR_INFO_DELIVER_CODE_MASK : 0; 4296 4297 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4298 exception_type_mask | GP_VECTOR; 4299 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4300 ent_intr_info); 4301 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4302 test_vmx_invalid_controls(); 4303 report_prefix_pop(); 4304 } 4305 report_prefix_pop(); 4306 4307 /* 4308 * deliver-error-code is 1 iff the the vector 4309 * indicates an exception that would normally deliver an error code 4310 */ 4311 report_prefix_push("error code <-> vector delivers error code"); 4312 for (cnt = 0; cnt < 32; cnt++) { 4313 bool has_error_code = false; 4314 u32 deliver_error_code_mask; 4315 4316 switch (cnt) { 4317 case DF_VECTOR: 4318 case TS_VECTOR: 4319 case NP_VECTOR: 4320 case SS_VECTOR: 4321 case GP_VECTOR: 4322 case PF_VECTOR: 4323 case AC_VECTOR: 4324 has_error_code = true; 4325 case CP_VECTOR: 4326 /* Some CPUs have error code and some do not, skip */ 4327 continue; 4328 } 4329 4330 /* Negative case */ 4331 deliver_error_code_mask = has_error_code ? 4332 0 : 4333 INTR_INFO_DELIVER_CODE_MASK; 4334 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4335 INTR_TYPE_HARD_EXCEPTION | cnt; 4336 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4337 ent_intr_info); 4338 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4339 test_vmx_invalid_controls(); 4340 report_prefix_pop(); 4341 4342 /* Positive case */ 4343 deliver_error_code_mask = has_error_code ? 4344 INTR_INFO_DELIVER_CODE_MASK : 4345 0; 4346 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4347 INTR_TYPE_HARD_EXCEPTION | cnt; 4348 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4349 ent_intr_info); 4350 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4351 test_vmx_valid_controls(); 4352 report_prefix_pop(); 4353 } 4354 report_prefix_pop(); 4355 4356 /* Reserved bits in the field (30:12) are 0. */ 4357 report_prefix_push("reserved bits clear"); 4358 for (cnt = 12; cnt <= 30; cnt++) { 4359 ent_intr_info = ent_intr_info_base | 4360 INTR_INFO_DELIVER_CODE_MASK | 4361 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4362 (1U << cnt); 4363 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4364 ent_intr_info); 4365 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4366 test_vmx_invalid_controls(); 4367 report_prefix_pop(); 4368 } 4369 report_prefix_pop(); 4370 4371 /* 4372 * If deliver-error-code is 1 4373 * bits 31:16 of the VM-entry exception error-code field are 0. 4374 */ 4375 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4376 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4377 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4378 "VM-entry exception error code[31:16] clear", 4379 ent_intr_info); 4380 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4381 for (cnt = 16; cnt <= 31; cnt++) { 4382 ent_intr_err = 1U << cnt; 4383 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4384 ent_intr_err); 4385 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4386 test_vmx_invalid_controls(); 4387 report_prefix_pop(); 4388 } 4389 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4390 report_prefix_pop(); 4391 4392 /* 4393 * If the interruption type is software interrupt, software exception, 4394 * or privileged software exception, the VM-entry instruction-length 4395 * field is in the range 0 - 15. 4396 */ 4397 4398 for (cnt = 0; cnt < 3; cnt++) { 4399 switch (cnt) { 4400 case 0: 4401 ent_intr_info = ent_intr_info_base | 4402 INTR_TYPE_SOFT_INTR; 4403 break; 4404 case 1: 4405 ent_intr_info = ent_intr_info_base | 4406 INTR_TYPE_SOFT_EXCEPTION; 4407 break; 4408 case 2: 4409 ent_intr_info = ent_intr_info_base | 4410 INTR_TYPE_PRIV_SW_EXCEPTION; 4411 break; 4412 } 4413 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4414 "VM-entry instruction-length check", 4415 ent_intr_info); 4416 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4417 4418 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4419 ent_intr_len = -1; 4420 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4421 ent_intr_len); 4422 vmcs_write(ENT_INST_LEN, ent_intr_len); 4423 test_vmx_invalid_controls(); 4424 report_prefix_pop(); 4425 4426 /* Instruction length set to 16 should fail */ 4427 ent_intr_len = 0x00000010; 4428 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4429 ent_intr_len); 4430 vmcs_write(ENT_INST_LEN, 0x00000010); 4431 test_vmx_invalid_controls(); 4432 report_prefix_pop(); 4433 4434 report_prefix_pop(); 4435 } 4436 4437 /* Cleanup */ 4438 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4439 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4440 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4441 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4442 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4443 vmcs_write(GUEST_CR0, guest_cr0_save); 4444 report_prefix_pop(); 4445 } 4446 4447 /* 4448 * Test interesting vTPR values for a given TPR threshold. 4449 */ 4450 static void test_vtpr_values(unsigned threshold) 4451 { 4452 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4453 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4454 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4455 } 4456 4457 static void try_tpr_threshold(unsigned threshold) 4458 { 4459 bool valid = true; 4460 4461 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4462 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4463 4464 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4465 (secondary & CPU_VINTD))) 4466 valid = !(threshold >> 4); 4467 4468 set_vtpr(-1); 4469 vmcs_write(TPR_THRESHOLD, threshold); 4470 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4471 if (valid) 4472 test_vmx_valid_controls(); 4473 else 4474 test_vmx_invalid_controls(); 4475 report_prefix_pop(); 4476 4477 if (valid) 4478 test_vtpr_values(threshold); 4479 } 4480 4481 /* 4482 * Test interesting TPR threshold values. 4483 */ 4484 static void test_tpr_threshold_values(void) 4485 { 4486 unsigned i; 4487 4488 for (i = 0; i < 0x10; i++) 4489 try_tpr_threshold(i); 4490 for (i = 4; i < 32; i++) 4491 try_tpr_threshold(1u << i); 4492 try_tpr_threshold(-1u); 4493 try_tpr_threshold(0x7fffffff); 4494 } 4495 4496 /* 4497 * This test covers the following two VM entry checks: 4498 * 4499 * i) If the "use TPR shadow" VM-execution control is 1 and the 4500 * "virtual-interrupt delivery" VM-execution control is 0, bits 4501 * 31:4 of the TPR threshold VM-execution control field must 4502 be 0. 4503 * [Intel SDM] 4504 * 4505 * ii) If the "use TPR shadow" VM-execution control is 1, the 4506 * "virtual-interrupt delivery" VM-execution control is 0 4507 * and the "virtualize APIC accesses" VM-execution control 4508 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4509 * control field must not be greater than the value of bits 4510 * 7:4 of VTPR. 4511 * [Intel SDM] 4512 */ 4513 static void test_tpr_threshold(void) 4514 { 4515 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4516 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4517 u64 threshold = vmcs_read(TPR_THRESHOLD); 4518 void *virtual_apic_page; 4519 4520 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4521 return; 4522 4523 virtual_apic_page = alloc_page(); 4524 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4525 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4526 4527 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4528 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4529 test_tpr_threshold_values(); 4530 report_prefix_pop(); 4531 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4532 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4533 test_tpr_threshold_values(); 4534 report_prefix_pop(); 4535 4536 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4537 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4538 goto out; 4539 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4540 4541 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4542 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4543 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4544 test_tpr_threshold_values(); 4545 report_prefix_pop(); 4546 4547 vmcs_write(CPU_EXEC_CTRL0, 4548 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4549 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4550 test_tpr_threshold_values(); 4551 report_prefix_pop(); 4552 } 4553 4554 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4555 vmcs_write(CPU_EXEC_CTRL0, 4556 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4557 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4558 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4559 test_tpr_threshold_values(); 4560 report_prefix_pop(); 4561 4562 vmcs_write(CPU_EXEC_CTRL0, 4563 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4564 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4565 test_tpr_threshold_values(); 4566 report_prefix_pop(); 4567 } 4568 4569 if ((ctrl_cpu_rev[1].clr & 4570 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4571 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4572 vmcs_write(CPU_EXEC_CTRL0, 4573 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4574 vmcs_write(CPU_EXEC_CTRL1, 4575 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4576 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4577 test_tpr_threshold_values(); 4578 report_prefix_pop(); 4579 4580 vmcs_write(CPU_EXEC_CTRL0, 4581 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4582 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4583 test_tpr_threshold_values(); 4584 report_prefix_pop(); 4585 } 4586 4587 vmcs_write(CPU_EXEC_CTRL1, secondary); 4588 out: 4589 vmcs_write(TPR_THRESHOLD, threshold); 4590 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4591 vmcs_write(CPU_EXEC_CTRL0, primary); 4592 } 4593 4594 /* 4595 * This test verifies the following two vmentry checks: 4596 * 4597 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4598 * VM-execution control must be 0. 4599 * [Intel SDM] 4600 * 4601 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4602 * exiting" VM-execution control must be 0. 4603 * [Intel SDM] 4604 */ 4605 static void test_nmi_ctrls(void) 4606 { 4607 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4608 4609 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4610 (PIN_NMI | PIN_VIRT_NMI)) { 4611 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4612 return; 4613 } 4614 4615 /* Save the controls so that we can restore them after our tests */ 4616 pin_ctrls = vmcs_read(PIN_CONTROLS); 4617 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4618 4619 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4620 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4621 4622 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4623 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4624 test_vmx_valid_controls(); 4625 report_prefix_pop(); 4626 4627 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4628 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4629 test_vmx_invalid_controls(); 4630 report_prefix_pop(); 4631 4632 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4633 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4634 test_vmx_valid_controls(); 4635 report_prefix_pop(); 4636 4637 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4638 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4639 test_vmx_valid_controls(); 4640 report_prefix_pop(); 4641 4642 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4643 report_info("NMI-window exiting is not supported, skipping..."); 4644 goto done; 4645 } 4646 4647 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4648 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4649 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4650 test_vmx_invalid_controls(); 4651 report_prefix_pop(); 4652 4653 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4654 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4655 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4656 test_vmx_valid_controls(); 4657 report_prefix_pop(); 4658 4659 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4660 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4661 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4662 test_vmx_valid_controls(); 4663 report_prefix_pop(); 4664 4665 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4666 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4667 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4668 test_vmx_valid_controls(); 4669 report_prefix_pop(); 4670 4671 /* Restore the controls to their original values */ 4672 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4673 done: 4674 vmcs_write(PIN_CONTROLS, pin_ctrls); 4675 } 4676 4677 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4678 { 4679 vmcs_write(EPTP, eptp); 4680 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4681 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4682 if (ctrl) 4683 test_vmx_valid_controls(); 4684 else 4685 test_vmx_invalid_controls(); 4686 report_prefix_pop(); 4687 4688 } 4689 4690 /* 4691 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4692 * control field must satisfy the following checks: 4693 * 4694 * - The EPT memory type (bits 2:0) must be a value supported by the 4695 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4696 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4697 * supported EPT page-walk length. 4698 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4699 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4700 * indicating that the processor does not support accessed and dirty 4701 * dirty flags for EPT. 4702 * - Reserved bits 11:7 and 63:N (where N is the processor's 4703 * physical-address width) must all be 0. 4704 * 4705 * 2. If the "unrestricted guest" VM-execution control is 1, the 4706 * "enable EPT" VM-execution control must also be 1. 4707 */ 4708 static void test_ept_eptp(void) 4709 { 4710 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4711 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4712 u64 eptp_saved = vmcs_read(EPTP); 4713 u32 primary = primary_saved; 4714 u32 secondary = secondary_saved; 4715 u64 msr, eptp = eptp_saved; 4716 bool un_cache = false; 4717 bool wr_bk = false; 4718 bool ctrl; 4719 u32 i, maxphysaddr; 4720 u64 j, resv_bits_mask = 0; 4721 4722 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4723 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4724 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4725 return; 4726 } 4727 4728 /* 4729 * Memory type (bits 2:0) 4730 */ 4731 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4732 if (msr & EPT_CAP_UC) 4733 un_cache = true; 4734 if (msr & EPT_CAP_WB) 4735 wr_bk = true; 4736 4737 /* Support for 4-level EPT is mandatory. */ 4738 report(is_4_level_ept_supported(), "4-level EPT support check"); 4739 4740 primary |= CPU_SECONDARY; 4741 vmcs_write(CPU_EXEC_CTRL0, primary); 4742 secondary |= CPU_EPT; 4743 vmcs_write(CPU_EXEC_CTRL1, secondary); 4744 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4745 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4746 vmcs_write(EPTP, eptp); 4747 4748 for (i = 0; i < 8; i++) { 4749 if (i == 0) { 4750 if (un_cache) { 4751 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4752 ctrl = true; 4753 } else { 4754 ctrl = false; 4755 } 4756 } else if (i == 6) { 4757 if (wr_bk) { 4758 report_info("EPT paging structure memory-type is Write-back\n"); 4759 ctrl = true; 4760 } else { 4761 ctrl = false; 4762 } 4763 } else { 4764 ctrl = false; 4765 } 4766 4767 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4768 vmcs_write(EPTP, eptp); 4769 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4770 eptp & EPT_MEM_TYPE_MASK); 4771 if (ctrl) 4772 test_vmx_valid_controls(); 4773 else 4774 test_vmx_invalid_controls(); 4775 report_prefix_pop(); 4776 } 4777 4778 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4779 4780 /* 4781 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4782 * less than the EPT page-walk length". 4783 */ 4784 for (i = 0; i < 8; i++) { 4785 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4786 (i << EPTP_PG_WALK_LEN_SHIFT); 4787 if (i == 3 || (i == 4 && is_5_level_ept_supported())) 4788 ctrl = true; 4789 else 4790 ctrl = false; 4791 4792 vmcs_write(EPTP, eptp); 4793 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4794 eptp & EPTP_PG_WALK_LEN_MASK); 4795 if (ctrl) 4796 test_vmx_valid_controls(); 4797 else 4798 test_vmx_invalid_controls(); 4799 report_prefix_pop(); 4800 } 4801 4802 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4803 3ul << EPTP_PG_WALK_LEN_SHIFT; 4804 4805 /* 4806 * Accessed and dirty flag (bit 6) 4807 */ 4808 if (ept_ad_bits_supported()) { 4809 report_info("Processor supports accessed and dirty flag"); 4810 eptp &= ~EPTP_AD_FLAG; 4811 test_eptp_ad_bit(eptp, true); 4812 4813 eptp |= EPTP_AD_FLAG; 4814 test_eptp_ad_bit(eptp, true); 4815 } else { 4816 report_info("Processor does not supports accessed and dirty flag"); 4817 eptp &= ~EPTP_AD_FLAG; 4818 test_eptp_ad_bit(eptp, true); 4819 4820 eptp |= EPTP_AD_FLAG; 4821 test_eptp_ad_bit(eptp, false); 4822 } 4823 4824 /* 4825 * Reserved bits [11:7] and [63:N] 4826 */ 4827 for (i = 0; i < 32; i++) { 4828 eptp = (eptp & 4829 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4830 (i << EPTP_RESERV_BITS_SHIFT); 4831 vmcs_write(EPTP, eptp); 4832 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4833 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4834 EPTP_RESERV_BITS_MASK); 4835 if (i == 0) 4836 test_vmx_valid_controls(); 4837 else 4838 test_vmx_invalid_controls(); 4839 report_prefix_pop(); 4840 } 4841 4842 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4843 4844 maxphysaddr = cpuid_maxphyaddr(); 4845 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4846 resv_bits_mask |= 1ul << i; 4847 } 4848 4849 for (j = maxphysaddr - 1; j <= 63; j++) { 4850 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4851 (j < maxphysaddr ? 0 : 1ul << j); 4852 vmcs_write(EPTP, eptp); 4853 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4854 (eptp >> maxphysaddr) & resv_bits_mask); 4855 if (j < maxphysaddr) 4856 test_vmx_valid_controls(); 4857 else 4858 test_vmx_invalid_controls(); 4859 report_prefix_pop(); 4860 } 4861 4862 secondary &= ~(CPU_EPT | CPU_URG); 4863 vmcs_write(CPU_EXEC_CTRL1, secondary); 4864 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4865 test_vmx_valid_controls(); 4866 report_prefix_pop(); 4867 4868 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4869 goto skip_unrestricted_guest; 4870 4871 secondary |= CPU_URG; 4872 vmcs_write(CPU_EXEC_CTRL1, secondary); 4873 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4874 test_vmx_invalid_controls(); 4875 report_prefix_pop(); 4876 4877 secondary |= CPU_EPT; 4878 setup_dummy_ept(); 4879 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4880 test_vmx_valid_controls(); 4881 report_prefix_pop(); 4882 4883 skip_unrestricted_guest: 4884 secondary &= ~CPU_URG; 4885 vmcs_write(CPU_EXEC_CTRL1, secondary); 4886 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4887 test_vmx_valid_controls(); 4888 report_prefix_pop(); 4889 4890 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4891 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4892 vmcs_write(EPTP, eptp_saved); 4893 } 4894 4895 /* 4896 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4897 * VM-execution control must also be 1. In addition, the PML address 4898 * must satisfy the following checks: 4899 * 4900 * * Bits 11:0 of the address must be 0. 4901 * * The address should not set any bits beyond the processor's 4902 * physical-address width. 4903 * 4904 * [Intel SDM] 4905 */ 4906 static void test_pml(void) 4907 { 4908 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4909 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4910 u32 primary = primary_saved; 4911 u32 secondary = secondary_saved; 4912 4913 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4914 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4915 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4916 return; 4917 } 4918 4919 primary |= CPU_SECONDARY; 4920 vmcs_write(CPU_EXEC_CTRL0, primary); 4921 secondary &= ~(CPU_PML | CPU_EPT); 4922 vmcs_write(CPU_EXEC_CTRL1, secondary); 4923 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4924 test_vmx_valid_controls(); 4925 report_prefix_pop(); 4926 4927 secondary |= CPU_PML; 4928 vmcs_write(CPU_EXEC_CTRL1, secondary); 4929 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4930 test_vmx_invalid_controls(); 4931 report_prefix_pop(); 4932 4933 secondary |= CPU_EPT; 4934 setup_dummy_ept(); 4935 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4936 test_vmx_valid_controls(); 4937 report_prefix_pop(); 4938 4939 secondary &= ~CPU_PML; 4940 vmcs_write(CPU_EXEC_CTRL1, secondary); 4941 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4942 test_vmx_valid_controls(); 4943 report_prefix_pop(); 4944 4945 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4946 PAGE_SIZE, false, false); 4947 4948 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4949 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4950 } 4951 4952 /* 4953 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4954 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4955 * 4956 * [Intel SDM] 4957 */ 4958 static void test_vmx_preemption_timer(void) 4959 { 4960 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4961 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4962 u32 pin = saved_pin; 4963 u32 exit = saved_exit; 4964 4965 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4966 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4967 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4968 return; 4969 } 4970 4971 pin |= PIN_PREEMPT; 4972 vmcs_write(PIN_CONTROLS, pin); 4973 exit &= ~EXI_SAVE_PREEMPT; 4974 vmcs_write(EXI_CONTROLS, exit); 4975 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4976 test_vmx_valid_controls(); 4977 report_prefix_pop(); 4978 4979 exit |= EXI_SAVE_PREEMPT; 4980 vmcs_write(EXI_CONTROLS, exit); 4981 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4982 test_vmx_valid_controls(); 4983 report_prefix_pop(); 4984 4985 pin &= ~PIN_PREEMPT; 4986 vmcs_write(PIN_CONTROLS, pin); 4987 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4988 test_vmx_invalid_controls(); 4989 report_prefix_pop(); 4990 4991 exit &= ~EXI_SAVE_PREEMPT; 4992 vmcs_write(EXI_CONTROLS, exit); 4993 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4994 test_vmx_valid_controls(); 4995 report_prefix_pop(); 4996 4997 vmcs_write(PIN_CONTROLS, saved_pin); 4998 vmcs_write(EXI_CONTROLS, saved_exit); 4999 } 5000 5001 extern unsigned char test_mtf1; 5002 extern unsigned char test_mtf2; 5003 extern unsigned char test_mtf3; 5004 extern unsigned char test_mtf4; 5005 5006 static void test_mtf_guest(void) 5007 { 5008 asm ("vmcall;\n\t" 5009 "out %al, $0x80;\n\t" 5010 "test_mtf1:\n\t" 5011 "vmcall;\n\t" 5012 "out %al, $0x80;\n\t" 5013 "test_mtf2:\n\t" 5014 /* 5015 * Prepare for the 'MOV CR3' test. Attempt to induce a 5016 * general-protection fault by moving a non-canonical address into 5017 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 5018 * so we must MOV the desired value into a register first. 5019 * 5020 * MOV RAX is done before the VMCALL such that MTF is only enabled 5021 * for the instruction under test. 5022 */ 5023 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 5024 "vmcall;\n\t" 5025 "mov %rax, %cr3;\n\t" 5026 "test_mtf3:\n\t" 5027 "vmcall;\n\t" 5028 /* 5029 * ICEBP/INT1 instruction. Though the instruction is now 5030 * documented, don't rely on assemblers enumerating the 5031 * instruction. Resort to hand assembly. 5032 */ 5033 ".byte 0xf1;\n\t" 5034 "vmcall;\n\t" 5035 "test_mtf4:\n\t" 5036 "mov $0, %eax;\n\t"); 5037 } 5038 5039 static void test_mtf_gp_handler(struct ex_regs *regs) 5040 { 5041 regs->rip = (unsigned long) &test_mtf3; 5042 } 5043 5044 static void test_mtf_db_handler(struct ex_regs *regs) 5045 { 5046 } 5047 5048 static void enable_mtf(void) 5049 { 5050 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5051 5052 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5053 } 5054 5055 static void disable_mtf(void) 5056 { 5057 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5058 5059 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5060 } 5061 5062 static void enable_tf(void) 5063 { 5064 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5065 5066 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5067 } 5068 5069 static void disable_tf(void) 5070 { 5071 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5072 5073 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5074 } 5075 5076 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5077 { 5078 unsigned long rip = vmcs_read(GUEST_RIP); 5079 5080 assert_exit_reason(VMX_MTF); 5081 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5082 insn_name, rip, exp_rip); 5083 } 5084 5085 static void vmx_mtf_test(void) 5086 { 5087 unsigned long pending_dbg; 5088 handler old_gp, old_db; 5089 5090 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5091 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5092 return; 5093 } 5094 5095 test_set_guest(test_mtf_guest); 5096 5097 /* Expect an MTF VM-exit after OUT instruction */ 5098 enter_guest(); 5099 skip_exit_vmcall(); 5100 5101 enable_mtf(); 5102 enter_guest(); 5103 report_mtf("OUT", (unsigned long) &test_mtf1); 5104 disable_mtf(); 5105 5106 /* 5107 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5108 * VM-exit with populated 'pending debug exceptions' VMCS field. 5109 */ 5110 enter_guest(); 5111 skip_exit_vmcall(); 5112 5113 enable_mtf(); 5114 enable_tf(); 5115 5116 enter_guest(); 5117 report_mtf("OUT", (unsigned long) &test_mtf2); 5118 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5119 report(pending_dbg & DR_STEP, 5120 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5121 pending_dbg, (unsigned long) DR_STEP); 5122 5123 disable_mtf(); 5124 disable_tf(); 5125 vmcs_write(GUEST_PENDING_DEBUG, 0); 5126 5127 /* 5128 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5129 * advanced to first instruction of #GP handler. 5130 */ 5131 enter_guest(); 5132 skip_exit_vmcall(); 5133 5134 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5135 5136 enable_mtf(); 5137 enter_guest(); 5138 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5139 disable_mtf(); 5140 5141 /* 5142 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5143 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5144 * provide clear indication of the relative priority. 5145 */ 5146 enter_guest(); 5147 skip_exit_vmcall(); 5148 5149 handle_exception(GP_VECTOR, old_gp); 5150 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5151 5152 enable_mtf(); 5153 enter_guest(); 5154 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5155 disable_mtf(); 5156 5157 enter_guest(); 5158 skip_exit_vmcall(); 5159 handle_exception(DB_VECTOR, old_db); 5160 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5161 enter_guest(); 5162 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5163 enter_guest(); 5164 } 5165 5166 extern char vmx_mtf_pdpte_guest_begin; 5167 extern char vmx_mtf_pdpte_guest_end; 5168 5169 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5170 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5171 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5172 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5173 "vmcall\n\t" 5174 "retq\n\t" 5175 "vmx_mtf_pdpte_guest_end:"); 5176 5177 static void vmx_mtf_pdpte_test(void) 5178 { 5179 void *test_mtf_pdpte_guest; 5180 pteval_t *pdpt; 5181 u32 guest_ar_cs; 5182 u64 guest_efer; 5183 pteval_t *pte; 5184 u64 guest_cr0; 5185 u64 guest_cr3; 5186 u64 guest_cr4; 5187 u64 ent_ctls; 5188 int i; 5189 5190 if (setup_ept(false)) 5191 return; 5192 5193 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5194 printf("CPU does not support 'monitor trap flag.'\n"); 5195 return; 5196 } 5197 5198 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5199 printf("CPU does not support 'unrestricted guest.'\n"); 5200 return; 5201 } 5202 5203 vmcs_write(EXC_BITMAP, ~0); 5204 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5205 5206 /* 5207 * Copy the guest code to an identity-mapped page. 5208 */ 5209 test_mtf_pdpte_guest = alloc_page(); 5210 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5211 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5212 5213 test_set_guest(test_mtf_pdpte_guest); 5214 5215 enter_guest(); 5216 skip_exit_vmcall(); 5217 5218 /* 5219 * Put the guest in non-paged 32-bit protected mode, ready to enter 5220 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5221 * when the guest started out in long mode. 5222 */ 5223 ent_ctls = vmcs_read(ENT_CONTROLS); 5224 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5225 5226 guest_efer = vmcs_read(GUEST_EFER); 5227 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5228 5229 /* 5230 * Set CS access rights bits for 32-bit protected mode: 5231 * 3:0 B execute/read/accessed 5232 * 4 1 code or data 5233 * 6:5 0 descriptor privilege level 5234 * 7 1 present 5235 * 11:8 0 reserved 5236 * 12 0 available for use by system software 5237 * 13 0 64 bit mode not active 5238 * 14 1 default operation size 32-bit segment 5239 * 15 1 page granularity: segment limit in 4K units 5240 * 16 0 segment usable 5241 * 31:17 0 reserved 5242 */ 5243 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5244 vmcs_write(GUEST_AR_CS, 0xc09b); 5245 5246 guest_cr0 = vmcs_read(GUEST_CR0); 5247 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5248 5249 guest_cr4 = vmcs_read(GUEST_CR4); 5250 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5251 5252 guest_cr3 = vmcs_read(GUEST_CR3); 5253 5254 /* 5255 * Turn the 4-level page table into a PAE page table by following the 0th 5256 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5257 * page. 5258 * 5259 * Why does this work? 5260 * 5261 * PAE uses 32-bit addressing which implies: 5262 * Bits 11:0 page offset 5263 * Bits 20:12 entry into 512-entry page table 5264 * Bits 29:21 entry into a 512-entry directory table 5265 * Bits 31:30 entry into the page directory pointer table. 5266 * Bits 63:32 zero 5267 * 5268 * As only 2 bits are needed to select the PDPTEs for the entire 5269 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5270 * directory pointer table. It doesn't matter which of these PDPTEs 5271 * are present because they must cover the guest code given that it 5272 * has already run successfully. 5273 * 5274 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5275 */ 5276 pte = get_pte_level( 5277 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5278 PDPT_LEVEL); 5279 5280 /* 5281 * Need some memory for the 4-entry PAE page directory pointer 5282 * table. Use the end of the identity-mapped page where the guest code 5283 * is stored. There is definitely space as the guest code is only a 5284 * few bytes. 5285 */ 5286 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5287 5288 /* 5289 * Copy the first four PDPTEs into the PAE page table with reserved 5290 * bits cleared. Note that permission bits from the PML4E and PDPTE 5291 * are not propagated. 5292 */ 5293 for (i = 0; i < 4; i++) { 5294 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5295 "PDPTE has invalid reserved bits"); 5296 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5297 "Cannot use 1GB super pages for PAE"); 5298 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5299 } 5300 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5301 5302 enable_mtf(); 5303 enter_guest(); 5304 assert_exit_reason(VMX_MTF); 5305 disable_mtf(); 5306 5307 /* 5308 * The four PDPTEs should have been loaded into the VMCS when 5309 * the guest set CR0.PG to enter PAE mode. 5310 */ 5311 for (i = 0; i < 4; i++) { 5312 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5313 5314 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5315 i, pdpte, pdpt[i]); 5316 } 5317 5318 /* 5319 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5320 * vmcs are wrong, this will fail. 5321 */ 5322 enter_guest(); 5323 skip_exit_vmcall(); 5324 5325 /* 5326 * Return guest to 64-bit mode and wrap up. 5327 */ 5328 vmcs_write(ENT_CONTROLS, ent_ctls); 5329 vmcs_write(GUEST_EFER, guest_efer); 5330 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5331 vmcs_write(GUEST_CR0, guest_cr0); 5332 vmcs_write(GUEST_CR4, guest_cr4); 5333 vmcs_write(GUEST_CR3, guest_cr3); 5334 5335 enter_guest(); 5336 } 5337 5338 /* 5339 * Tests for VM-execution control fields 5340 */ 5341 static void test_vm_execution_ctls(void) 5342 { 5343 test_pin_based_ctls(); 5344 test_primary_processor_based_ctls(); 5345 test_secondary_processor_based_ctls(); 5346 test_cr3_targets(); 5347 test_io_bitmaps(); 5348 test_msr_bitmap(); 5349 test_apic_ctls(); 5350 test_tpr_threshold(); 5351 test_nmi_ctrls(); 5352 test_pml(); 5353 test_vpid(); 5354 test_ept_eptp(); 5355 test_vmx_preemption_timer(); 5356 } 5357 5358 /* 5359 * The following checks are performed for the VM-entry MSR-load address if 5360 * the VM-entry MSR-load count field is non-zero: 5361 * 5362 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5363 * The address should not set any bits beyond the processor's 5364 * physical-address width. 5365 * 5366 * - The address of the last byte in the VM-entry MSR-load area 5367 * should not set any bits beyond the processor's physical-address 5368 * width. The address of this last byte is VM-entry MSR-load address 5369 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5370 * uses more bits than the processor's physical-address width.) 5371 * 5372 * 5373 * [Intel SDM] 5374 */ 5375 static void test_entry_msr_load(void) 5376 { 5377 entry_msr_load = alloc_page(); 5378 u64 tmp; 5379 u32 entry_msr_ld_cnt = 1; 5380 int i; 5381 u32 addr_len = 64; 5382 5383 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5384 5385 /* Check first 4 bits of VM-entry MSR-load address */ 5386 for (i = 0; i < 4; i++) { 5387 tmp = (u64)entry_msr_load | 1ull << i; 5388 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5389 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5390 tmp & 0xf); 5391 test_vmx_invalid_controls(); 5392 report_prefix_pop(); 5393 } 5394 5395 if (basic.val & (1ul << 48)) 5396 addr_len = 32; 5397 5398 test_vmcs_addr_values("VM-entry-MSR-load address", 5399 ENTER_MSR_LD_ADDR, 16, false, false, 5400 4, addr_len - 1); 5401 5402 /* 5403 * Check last byte of VM-entry MSR-load address 5404 */ 5405 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5406 5407 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5408 i < 64; i++) { 5409 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5410 1ul << i; 5411 vmcs_write(ENTER_MSR_LD_ADDR, 5412 tmp - (entry_msr_ld_cnt * 16 - 1)); 5413 test_vmx_invalid_controls(); 5414 } 5415 5416 vmcs_write(ENT_MSR_LD_CNT, 2); 5417 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5418 test_vmx_invalid_controls(); 5419 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5420 test_vmx_valid_controls(); 5421 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5422 test_vmx_valid_controls(); 5423 } 5424 5425 static struct vmx_state_area_test_data { 5426 u32 msr; 5427 u64 exp; 5428 bool enabled; 5429 } vmx_state_area_test_data; 5430 5431 static void guest_state_test_main(void) 5432 { 5433 u64 obs; 5434 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5435 5436 while (1) { 5437 if (vmx_get_test_stage() == 2) 5438 break; 5439 5440 if (data->enabled) { 5441 obs = rdmsr(data->msr); 5442 report(data->exp == obs, 5443 "Guest state is 0x%lx (expected 0x%lx)", 5444 obs, data->exp); 5445 } 5446 5447 vmcall(); 5448 } 5449 5450 asm volatile("fnop"); 5451 } 5452 5453 static void test_guest_state(const char *test, bool xfail, u64 field, 5454 const char * field_name) 5455 { 5456 struct vmentry_result result; 5457 u8 abort_flags; 5458 5459 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5460 if (!xfail) 5461 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5462 5463 __enter_guest(abort_flags, &result); 5464 5465 report(result.exit_reason.failed_vmentry == xfail && 5466 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5467 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5468 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5469 "%s, %s = %lx", test, field_name, field); 5470 5471 if (!result.exit_reason.failed_vmentry) 5472 skip_exit_insn(); 5473 } 5474 5475 /* 5476 * Tests for VM-entry control fields 5477 */ 5478 static void test_vm_entry_ctls(void) 5479 { 5480 test_invalid_event_injection(); 5481 test_entry_msr_load(); 5482 } 5483 5484 /* 5485 * The following checks are performed for the VM-exit MSR-store address if 5486 * the VM-exit MSR-store count field is non-zero: 5487 * 5488 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5489 * The address should not set any bits beyond the processor's 5490 * physical-address width. 5491 * 5492 * - The address of the last byte in the VM-exit MSR-store area 5493 * should not set any bits beyond the processor's physical-address 5494 * width. The address of this last byte is VM-exit MSR-store address 5495 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5496 * uses more bits than the processor's physical-address width.) 5497 * 5498 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5499 * in the range 63:32. 5500 * 5501 * [Intel SDM] 5502 */ 5503 static void test_exit_msr_store(void) 5504 { 5505 exit_msr_store = alloc_page(); 5506 u64 tmp; 5507 u32 exit_msr_st_cnt = 1; 5508 int i; 5509 u32 addr_len = 64; 5510 5511 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5512 5513 /* Check first 4 bits of VM-exit MSR-store address */ 5514 for (i = 0; i < 4; i++) { 5515 tmp = (u64)exit_msr_store | 1ull << i; 5516 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5517 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5518 tmp & 0xf); 5519 test_vmx_invalid_controls(); 5520 report_prefix_pop(); 5521 } 5522 5523 if (basic.val & (1ul << 48)) 5524 addr_len = 32; 5525 5526 test_vmcs_addr_values("VM-exit-MSR-store address", 5527 EXIT_MSR_ST_ADDR, 16, false, false, 5528 4, addr_len - 1); 5529 5530 /* 5531 * Check last byte of VM-exit MSR-store address 5532 */ 5533 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5534 5535 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5536 i < 64; i++) { 5537 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5538 1ul << i; 5539 vmcs_write(EXIT_MSR_ST_ADDR, 5540 tmp - (exit_msr_st_cnt * 16 - 1)); 5541 test_vmx_invalid_controls(); 5542 } 5543 5544 vmcs_write(EXI_MSR_ST_CNT, 2); 5545 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5546 test_vmx_invalid_controls(); 5547 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5548 test_vmx_valid_controls(); 5549 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5550 test_vmx_valid_controls(); 5551 } 5552 5553 /* 5554 * Tests for VM-exit controls 5555 */ 5556 static void test_vm_exit_ctls(void) 5557 { 5558 test_exit_msr_store(); 5559 } 5560 5561 /* 5562 * Check that the virtual CPU checks all of the VMX controls as 5563 * documented in the Intel SDM. 5564 */ 5565 static void vmx_controls_test(void) 5566 { 5567 /* 5568 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5569 * fail due to invalid guest state, should we make it that 5570 * far. 5571 */ 5572 vmcs_write(GUEST_RFLAGS, 0); 5573 5574 test_vm_execution_ctls(); 5575 test_vm_exit_ctls(); 5576 test_vm_entry_ctls(); 5577 } 5578 5579 struct apic_reg_virt_config { 5580 bool apic_register_virtualization; 5581 bool use_tpr_shadow; 5582 bool virtualize_apic_accesses; 5583 bool virtualize_x2apic_mode; 5584 bool activate_secondary_controls; 5585 }; 5586 5587 struct apic_reg_test { 5588 const char *name; 5589 struct apic_reg_virt_config apic_reg_virt_config; 5590 }; 5591 5592 struct apic_reg_virt_expectation { 5593 enum Reason rd_exit_reason; 5594 enum Reason wr_exit_reason; 5595 u32 val; 5596 u32 (*virt_fn)(u32); 5597 5598 /* 5599 * If false, accessing the APIC access address from L2 is treated as a 5600 * normal memory operation, rather than triggering virtualization. 5601 */ 5602 bool virtualize_apic_accesses; 5603 }; 5604 5605 static u32 apic_virt_identity(u32 val) 5606 { 5607 return val; 5608 } 5609 5610 static u32 apic_virt_nibble1(u32 val) 5611 { 5612 return val & 0xf0; 5613 } 5614 5615 static u32 apic_virt_byte3(u32 val) 5616 { 5617 return val & (0xff << 24); 5618 } 5619 5620 static bool apic_reg_virt_exit_expectation( 5621 u32 reg, struct apic_reg_virt_config *config, 5622 struct apic_reg_virt_expectation *expectation) 5623 { 5624 /* Good configs, where some L2 APIC accesses are virtualized. */ 5625 bool virtualize_apic_accesses_only = 5626 config->virtualize_apic_accesses && 5627 !config->use_tpr_shadow && 5628 !config->apic_register_virtualization && 5629 !config->virtualize_x2apic_mode && 5630 config->activate_secondary_controls; 5631 bool virtualize_apic_accesses_and_use_tpr_shadow = 5632 config->virtualize_apic_accesses && 5633 config->use_tpr_shadow && 5634 !config->apic_register_virtualization && 5635 !config->virtualize_x2apic_mode && 5636 config->activate_secondary_controls; 5637 bool apic_register_virtualization = 5638 config->virtualize_apic_accesses && 5639 config->use_tpr_shadow && 5640 config->apic_register_virtualization && 5641 !config->virtualize_x2apic_mode && 5642 config->activate_secondary_controls; 5643 5644 expectation->val = MAGIC_VAL_1; 5645 expectation->virt_fn = apic_virt_identity; 5646 expectation->virtualize_apic_accesses = 5647 config->virtualize_apic_accesses && 5648 config->activate_secondary_controls; 5649 if (virtualize_apic_accesses_only) { 5650 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5651 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5652 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5653 switch (reg) { 5654 case APIC_TASKPRI: 5655 expectation->rd_exit_reason = VMX_VMCALL; 5656 expectation->wr_exit_reason = VMX_VMCALL; 5657 expectation->virt_fn = apic_virt_nibble1; 5658 break; 5659 default: 5660 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5661 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5662 } 5663 } else if (apic_register_virtualization) { 5664 expectation->rd_exit_reason = VMX_VMCALL; 5665 5666 switch (reg) { 5667 case APIC_ID: 5668 case APIC_EOI: 5669 case APIC_LDR: 5670 case APIC_DFR: 5671 case APIC_SPIV: 5672 case APIC_ESR: 5673 case APIC_ICR: 5674 case APIC_LVTT: 5675 case APIC_LVTTHMR: 5676 case APIC_LVTPC: 5677 case APIC_LVT0: 5678 case APIC_LVT1: 5679 case APIC_LVTERR: 5680 case APIC_TMICT: 5681 case APIC_TDCR: 5682 expectation->wr_exit_reason = VMX_APIC_WRITE; 5683 break; 5684 case APIC_LVR: 5685 case APIC_ISR ... APIC_ISR + 0x70: 5686 case APIC_TMR ... APIC_TMR + 0x70: 5687 case APIC_IRR ... APIC_IRR + 0x70: 5688 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5689 break; 5690 case APIC_TASKPRI: 5691 expectation->wr_exit_reason = VMX_VMCALL; 5692 expectation->virt_fn = apic_virt_nibble1; 5693 break; 5694 case APIC_ICR2: 5695 expectation->wr_exit_reason = VMX_VMCALL; 5696 expectation->virt_fn = apic_virt_byte3; 5697 break; 5698 default: 5699 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5700 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5701 } 5702 } else if (!expectation->virtualize_apic_accesses) { 5703 /* 5704 * No APIC registers are directly virtualized. This includes 5705 * VTPR, which can be virtualized through MOV to/from CR8 via 5706 * the use TPR shadow control, but not through directly 5707 * accessing VTPR. 5708 */ 5709 expectation->rd_exit_reason = VMX_VMCALL; 5710 expectation->wr_exit_reason = VMX_VMCALL; 5711 } else { 5712 printf("Cannot parse APIC register virtualization config:\n" 5713 "\tvirtualize_apic_accesses: %d\n" 5714 "\tuse_tpr_shadow: %d\n" 5715 "\tapic_register_virtualization: %d\n" 5716 "\tvirtualize_x2apic_mode: %d\n" 5717 "\tactivate_secondary_controls: %d\n", 5718 config->virtualize_apic_accesses, 5719 config->use_tpr_shadow, 5720 config->apic_register_virtualization, 5721 config->virtualize_x2apic_mode, 5722 config->activate_secondary_controls); 5723 5724 return false; 5725 } 5726 5727 return true; 5728 } 5729 5730 struct apic_reg_test apic_reg_tests[] = { 5731 /* Good configs, where some L2 APIC accesses are virtualized. */ 5732 { 5733 .name = "Virtualize APIC accesses", 5734 .apic_reg_virt_config = { 5735 .virtualize_apic_accesses = true, 5736 .use_tpr_shadow = false, 5737 .apic_register_virtualization = false, 5738 .virtualize_x2apic_mode = false, 5739 .activate_secondary_controls = true, 5740 }, 5741 }, 5742 { 5743 .name = "Virtualize APIC accesses + Use TPR shadow", 5744 .apic_reg_virt_config = { 5745 .virtualize_apic_accesses = true, 5746 .use_tpr_shadow = true, 5747 .apic_register_virtualization = false, 5748 .virtualize_x2apic_mode = false, 5749 .activate_secondary_controls = true, 5750 }, 5751 }, 5752 { 5753 .name = "APIC-register virtualization", 5754 .apic_reg_virt_config = { 5755 .virtualize_apic_accesses = true, 5756 .use_tpr_shadow = true, 5757 .apic_register_virtualization = true, 5758 .virtualize_x2apic_mode = false, 5759 .activate_secondary_controls = true, 5760 }, 5761 }, 5762 5763 /* 5764 * Test that the secondary processor-based VM-execution controls are 5765 * correctly ignored when "activate secondary controls" is disabled. 5766 */ 5767 { 5768 .name = "Activate secondary controls off", 5769 .apic_reg_virt_config = { 5770 .virtualize_apic_accesses = true, 5771 .use_tpr_shadow = false, 5772 .apic_register_virtualization = true, 5773 .virtualize_x2apic_mode = true, 5774 .activate_secondary_controls = false, 5775 }, 5776 }, 5777 { 5778 .name = "Activate secondary controls off + Use TPR shadow", 5779 .apic_reg_virt_config = { 5780 .virtualize_apic_accesses = true, 5781 .use_tpr_shadow = true, 5782 .apic_register_virtualization = true, 5783 .virtualize_x2apic_mode = true, 5784 .activate_secondary_controls = false, 5785 }, 5786 }, 5787 5788 /* 5789 * Test that the APIC access address is treated like an arbitrary memory 5790 * address when "virtualize APIC accesses" is disabled. 5791 */ 5792 { 5793 .name = "Virtualize APIC accesses off + Use TPR shadow", 5794 .apic_reg_virt_config = { 5795 .virtualize_apic_accesses = false, 5796 .use_tpr_shadow = true, 5797 .apic_register_virtualization = true, 5798 .virtualize_x2apic_mode = true, 5799 .activate_secondary_controls = true, 5800 }, 5801 }, 5802 5803 /* 5804 * Test that VM entry fails due to invalid controls when 5805 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5806 * disabled. 5807 */ 5808 { 5809 .name = "APIC-register virtualization + Use TPR shadow off", 5810 .apic_reg_virt_config = { 5811 .virtualize_apic_accesses = true, 5812 .use_tpr_shadow = false, 5813 .apic_register_virtualization = true, 5814 .virtualize_x2apic_mode = false, 5815 .activate_secondary_controls = true, 5816 }, 5817 }, 5818 5819 /* 5820 * Test that VM entry fails due to invalid controls when 5821 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5822 * disabled. 5823 */ 5824 { 5825 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5826 .apic_reg_virt_config = { 5827 .virtualize_apic_accesses = false, 5828 .use_tpr_shadow = false, 5829 .apic_register_virtualization = false, 5830 .virtualize_x2apic_mode = true, 5831 .activate_secondary_controls = true, 5832 }, 5833 }, 5834 { 5835 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5836 .apic_reg_virt_config = { 5837 .virtualize_apic_accesses = false, 5838 .use_tpr_shadow = false, 5839 .apic_register_virtualization = true, 5840 .virtualize_x2apic_mode = true, 5841 .activate_secondary_controls = true, 5842 }, 5843 }, 5844 5845 /* 5846 * Test that VM entry fails due to invalid controls when 5847 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5848 * is enabled. 5849 */ 5850 { 5851 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5852 .apic_reg_virt_config = { 5853 .virtualize_apic_accesses = true, 5854 .use_tpr_shadow = true, 5855 .apic_register_virtualization = false, 5856 .virtualize_x2apic_mode = true, 5857 .activate_secondary_controls = true, 5858 }, 5859 }, 5860 { 5861 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5862 .apic_reg_virt_config = { 5863 .virtualize_apic_accesses = true, 5864 .use_tpr_shadow = true, 5865 .apic_register_virtualization = true, 5866 .virtualize_x2apic_mode = true, 5867 .activate_secondary_controls = true, 5868 }, 5869 }, 5870 }; 5871 5872 enum Apic_op { 5873 APIC_OP_XAPIC_RD, 5874 APIC_OP_XAPIC_WR, 5875 TERMINATE, 5876 }; 5877 5878 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5879 { 5880 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5881 } 5882 5883 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5884 { 5885 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5886 } 5887 5888 struct apic_reg_virt_guest_args { 5889 enum Apic_op op; 5890 u32 *apic_access_address; 5891 u32 reg; 5892 u32 val; 5893 bool check_rd; 5894 u32 (*virt_fn)(u32); 5895 } apic_reg_virt_guest_args; 5896 5897 static void apic_reg_virt_guest(void) 5898 { 5899 volatile struct apic_reg_virt_guest_args *args = 5900 &apic_reg_virt_guest_args; 5901 5902 for (;;) { 5903 enum Apic_op op = args->op; 5904 u32 *apic_access_address = args->apic_access_address; 5905 u32 reg = args->reg; 5906 u32 val = args->val; 5907 bool check_rd = args->check_rd; 5908 u32 (*virt_fn)(u32) = args->virt_fn; 5909 5910 if (op == TERMINATE) 5911 break; 5912 5913 if (op == APIC_OP_XAPIC_RD) { 5914 u32 ret = vmx_xapic_read(apic_access_address, reg); 5915 5916 if (check_rd) { 5917 u32 want = virt_fn(val); 5918 u32 got = virt_fn(ret); 5919 5920 report(got == want, 5921 "read 0x%x, expected 0x%x.", got, want); 5922 } 5923 } else if (op == APIC_OP_XAPIC_WR) { 5924 vmx_xapic_write(apic_access_address, reg, val); 5925 } 5926 5927 /* 5928 * The L1 should always execute a vmcall after it's done testing 5929 * an individual APIC operation. This helps to validate that the 5930 * L1 and L2 are in sync with each other, as expected. 5931 */ 5932 vmcall(); 5933 } 5934 } 5935 5936 static void test_xapic_rd( 5937 u32 reg, struct apic_reg_virt_expectation *expectation, 5938 u32 *apic_access_address, u32 *virtual_apic_page) 5939 { 5940 u32 val = expectation->val; 5941 u32 exit_reason_want = expectation->rd_exit_reason; 5942 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5943 5944 report_prefix_pushf("xapic - reading 0x%03x", reg); 5945 5946 /* Configure guest to do an xapic read */ 5947 args->op = APIC_OP_XAPIC_RD; 5948 args->apic_access_address = apic_access_address; 5949 args->reg = reg; 5950 args->val = val; 5951 args->check_rd = exit_reason_want == VMX_VMCALL; 5952 args->virt_fn = expectation->virt_fn; 5953 5954 /* Setup virtual APIC page */ 5955 if (!expectation->virtualize_apic_accesses) { 5956 apic_access_address[apic_reg_index(reg)] = val; 5957 virtual_apic_page[apic_reg_index(reg)] = 0; 5958 } else if (exit_reason_want == VMX_VMCALL) { 5959 apic_access_address[apic_reg_index(reg)] = 0; 5960 virtual_apic_page[apic_reg_index(reg)] = val; 5961 } 5962 5963 /* Enter guest */ 5964 enter_guest(); 5965 5966 /* 5967 * Validate the behavior and 5968 * pass a magic value back to the guest. 5969 */ 5970 if (exit_reason_want == VMX_APIC_ACCESS) { 5971 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5972 5973 assert_exit_reason(exit_reason_want); 5974 report(apic_page_offset == reg, 5975 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5976 apic_page_offset, reg); 5977 skip_exit_insn(); 5978 5979 /* Reenter guest so it can consume/check rcx and exit again. */ 5980 enter_guest(); 5981 } else if (exit_reason_want != VMX_VMCALL) { 5982 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5983 } 5984 5985 skip_exit_vmcall(); 5986 report_prefix_pop(); 5987 } 5988 5989 static void test_xapic_wr( 5990 u32 reg, struct apic_reg_virt_expectation *expectation, 5991 u32 *apic_access_address, u32 *virtual_apic_page) 5992 { 5993 u32 val = expectation->val; 5994 u32 exit_reason_want = expectation->wr_exit_reason; 5995 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5996 bool virtualized = 5997 expectation->virtualize_apic_accesses && 5998 (exit_reason_want == VMX_APIC_WRITE || 5999 exit_reason_want == VMX_VMCALL); 6000 bool checked = false; 6001 6002 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 6003 6004 /* Configure guest to do an xapic read */ 6005 args->op = APIC_OP_XAPIC_WR; 6006 args->apic_access_address = apic_access_address; 6007 args->reg = reg; 6008 args->val = val; 6009 6010 /* Setup virtual APIC page */ 6011 if (virtualized || !expectation->virtualize_apic_accesses) { 6012 apic_access_address[apic_reg_index(reg)] = 0; 6013 virtual_apic_page[apic_reg_index(reg)] = 0; 6014 } 6015 6016 /* Enter guest */ 6017 enter_guest(); 6018 6019 /* 6020 * Validate the behavior and 6021 * pass a magic value back to the guest. 6022 */ 6023 if (exit_reason_want == VMX_APIC_ACCESS) { 6024 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6025 6026 assert_exit_reason(exit_reason_want); 6027 report(apic_page_offset == reg, 6028 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6029 apic_page_offset, reg); 6030 skip_exit_insn(); 6031 6032 /* Reenter guest so it can consume/check rcx and exit again. */ 6033 enter_guest(); 6034 } else if (exit_reason_want == VMX_APIC_WRITE) { 6035 assert_exit_reason(exit_reason_want); 6036 report(virtual_apic_page[apic_reg_index(reg)] == val, 6037 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6038 apic_reg_index(reg), 6039 virtual_apic_page[apic_reg_index(reg)], val); 6040 checked = true; 6041 6042 /* Reenter guest so it can consume/check rcx and exit again. */ 6043 enter_guest(); 6044 } else if (exit_reason_want != VMX_VMCALL) { 6045 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6046 } 6047 6048 assert_exit_reason(VMX_VMCALL); 6049 if (virtualized && !checked) { 6050 u32 want = expectation->virt_fn(val); 6051 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6052 got = expectation->virt_fn(got); 6053 6054 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6055 got, want); 6056 } else if (!expectation->virtualize_apic_accesses && !checked) { 6057 u32 got = apic_access_address[apic_reg_index(reg)]; 6058 6059 report(got == val, 6060 "non-virtualized write; val is 0x%x, want 0x%x", got, 6061 val); 6062 } else if (!expectation->virtualize_apic_accesses && checked) { 6063 report_fail("Non-virtualized write was prematurely checked!"); 6064 } 6065 6066 skip_exit_vmcall(); 6067 report_prefix_pop(); 6068 } 6069 6070 enum Config_type { 6071 CONFIG_TYPE_GOOD, 6072 CONFIG_TYPE_UNSUPPORTED, 6073 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6074 }; 6075 6076 static enum Config_type configure_apic_reg_virt_test( 6077 struct apic_reg_virt_config *apic_reg_virt_config) 6078 { 6079 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6080 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6081 /* Configs where L2 entry fails early, due to invalid controls. */ 6082 bool use_tpr_shadow_incorrectly_off = 6083 !apic_reg_virt_config->use_tpr_shadow && 6084 (apic_reg_virt_config->apic_register_virtualization || 6085 apic_reg_virt_config->virtualize_x2apic_mode) && 6086 apic_reg_virt_config->activate_secondary_controls; 6087 bool virtualize_apic_accesses_incorrectly_on = 6088 apic_reg_virt_config->virtualize_apic_accesses && 6089 apic_reg_virt_config->virtualize_x2apic_mode && 6090 apic_reg_virt_config->activate_secondary_controls; 6091 bool vmentry_fails_early = 6092 use_tpr_shadow_incorrectly_off || 6093 virtualize_apic_accesses_incorrectly_on; 6094 6095 if (apic_reg_virt_config->activate_secondary_controls) { 6096 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6097 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6098 return CONFIG_TYPE_UNSUPPORTED; 6099 } 6100 cpu_exec_ctrl0 |= CPU_SECONDARY; 6101 } else { 6102 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6103 } 6104 6105 if (apic_reg_virt_config->virtualize_apic_accesses) { 6106 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6107 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6108 return CONFIG_TYPE_UNSUPPORTED; 6109 } 6110 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6111 } else { 6112 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6113 } 6114 6115 if (apic_reg_virt_config->use_tpr_shadow) { 6116 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6117 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6118 return CONFIG_TYPE_UNSUPPORTED; 6119 } 6120 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6121 } else { 6122 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6123 } 6124 6125 if (apic_reg_virt_config->apic_register_virtualization) { 6126 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6127 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6128 return CONFIG_TYPE_UNSUPPORTED; 6129 } 6130 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6131 } else { 6132 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6133 } 6134 6135 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6136 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6137 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6138 return CONFIG_TYPE_UNSUPPORTED; 6139 } 6140 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6141 } else { 6142 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6143 } 6144 6145 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6146 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6147 6148 if (vmentry_fails_early) 6149 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6150 6151 return CONFIG_TYPE_GOOD; 6152 } 6153 6154 static bool cpu_has_apicv(void) 6155 { 6156 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6157 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6158 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6159 } 6160 6161 /* Validates APIC register access across valid virtualization configurations. */ 6162 static void apic_reg_virt_test(void) 6163 { 6164 u32 *apic_access_address; 6165 u32 *virtual_apic_page; 6166 u64 control; 6167 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6168 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6169 int i; 6170 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6171 6172 if (!cpu_has_apicv()) { 6173 report_skip(__func__); 6174 return; 6175 } 6176 6177 control = cpu_exec_ctrl1; 6178 control &= ~CPU_VINTD; 6179 vmcs_write(CPU_EXEC_CTRL1, control); 6180 6181 test_set_guest(apic_reg_virt_guest); 6182 6183 /* 6184 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6185 * VM-execution is guaranteed to apply only if translations to the 6186 * APIC-access address use a 4-KByte page. 6187 */ 6188 apic_access_address = alloc_page(); 6189 force_4k_page(apic_access_address); 6190 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6191 6192 virtual_apic_page = alloc_page(); 6193 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6194 6195 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6196 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6197 struct apic_reg_virt_config *apic_reg_virt_config = 6198 &apic_reg_test->apic_reg_virt_config; 6199 enum Config_type config_type; 6200 u32 reg; 6201 6202 printf("--- %s test ---\n", apic_reg_test->name); 6203 config_type = 6204 configure_apic_reg_virt_test(apic_reg_virt_config); 6205 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6206 printf("Skip because of missing features.\n"); 6207 continue; 6208 } 6209 6210 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6211 enter_guest_with_bad_controls(); 6212 continue; 6213 } 6214 6215 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6216 struct apic_reg_virt_expectation expectation = {}; 6217 bool ok; 6218 6219 ok = apic_reg_virt_exit_expectation( 6220 reg, apic_reg_virt_config, &expectation); 6221 if (!ok) { 6222 report_fail("Malformed test."); 6223 break; 6224 } 6225 6226 test_xapic_rd(reg, &expectation, apic_access_address, 6227 virtual_apic_page); 6228 test_xapic_wr(reg, &expectation, apic_access_address, 6229 virtual_apic_page); 6230 } 6231 } 6232 6233 /* Terminate the guest */ 6234 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6235 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6236 args->op = TERMINATE; 6237 enter_guest(); 6238 assert_exit_reason(VMX_VMCALL); 6239 } 6240 6241 struct virt_x2apic_mode_config { 6242 struct apic_reg_virt_config apic_reg_virt_config; 6243 bool virtual_interrupt_delivery; 6244 bool use_msr_bitmaps; 6245 bool disable_x2apic_msr_intercepts; 6246 bool disable_x2apic; 6247 }; 6248 6249 struct virt_x2apic_mode_test_case { 6250 const char *name; 6251 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6252 }; 6253 6254 enum Virt_x2apic_mode_behavior_type { 6255 X2APIC_ACCESS_VIRTUALIZED, 6256 X2APIC_ACCESS_PASSED_THROUGH, 6257 X2APIC_ACCESS_TRIGGERS_GP, 6258 }; 6259 6260 struct virt_x2apic_mode_expectation { 6261 enum Reason rd_exit_reason; 6262 enum Reason wr_exit_reason; 6263 6264 /* 6265 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6266 * the x2APIC registers are 32 bits. Notice: 6267 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6268 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6269 */ 6270 u64 rd_val; 6271 u64 wr_val; 6272 6273 /* 6274 * Compares input to virtualized output; 6275 * 1st arg is pointer to return expected virtualization output. 6276 */ 6277 u64 (*virt_fn)(u64); 6278 6279 enum Virt_x2apic_mode_behavior_type rd_behavior; 6280 enum Virt_x2apic_mode_behavior_type wr_behavior; 6281 bool wr_only; 6282 }; 6283 6284 static u64 virt_x2apic_mode_identity(u64 val) 6285 { 6286 return val; 6287 } 6288 6289 static u64 virt_x2apic_mode_nibble1(u64 val) 6290 { 6291 return val & 0xf0; 6292 } 6293 6294 static void virt_x2apic_mode_rd_expectation( 6295 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6296 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6297 struct virt_x2apic_mode_expectation *expectation) 6298 { 6299 bool readable = 6300 !x2apic_reg_reserved(reg) && 6301 reg != APIC_EOI; 6302 6303 expectation->rd_exit_reason = VMX_VMCALL; 6304 expectation->virt_fn = virt_x2apic_mode_identity; 6305 if (virt_x2apic_mode_on && apic_register_virtualization) { 6306 expectation->rd_val = MAGIC_VAL_1; 6307 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6308 expectation->virt_fn = virt_x2apic_mode_nibble1; 6309 else if (reg == APIC_TASKPRI) 6310 expectation->virt_fn = virt_x2apic_mode_nibble1; 6311 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6312 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6313 reg == APIC_TASKPRI) { 6314 expectation->rd_val = MAGIC_VAL_1; 6315 expectation->virt_fn = virt_x2apic_mode_nibble1; 6316 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6317 } else if (!disable_x2apic && readable) { 6318 expectation->rd_val = apic_read(reg); 6319 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6320 } else { 6321 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6322 } 6323 } 6324 6325 /* 6326 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6327 * 6328 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6329 * val pointer arg and returns true. For non-writable registers, val is not 6330 * modified and get_x2apic_wr_val() returns false. 6331 */ 6332 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6333 { 6334 switch (reg) { 6335 case APIC_TASKPRI: 6336 /* Bits 31:8 are reserved. */ 6337 *val &= 0xff; 6338 break; 6339 case APIC_EOI: 6340 case APIC_ESR: 6341 case APIC_TMICT: 6342 /* 6343 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6344 * TMICT: A write of 0 to the initial-count register effectively 6345 * stops the local APIC timer, in both one-shot and 6346 * periodic mode. 6347 */ 6348 *val = 0; 6349 break; 6350 case APIC_SPIV: 6351 case APIC_LVTT: 6352 case APIC_LVTTHMR: 6353 case APIC_LVTPC: 6354 case APIC_LVT0: 6355 case APIC_LVT1: 6356 case APIC_LVTERR: 6357 case APIC_TDCR: 6358 /* 6359 * To avoid writing a 1 to a reserved bit or causing some other 6360 * unintended side effect, read the current value and use it as 6361 * the write value. 6362 */ 6363 *val = apic_read(reg); 6364 break; 6365 case APIC_CMCI: 6366 if (!apic_lvt_entry_supported(6)) 6367 return false; 6368 *val = apic_read(reg); 6369 break; 6370 case APIC_ICR: 6371 *val = 0x40000 | 0xf1; 6372 break; 6373 case APIC_SELF_IPI: 6374 /* 6375 * With special processing (i.e., virtualize x2APIC mode + 6376 * virtual interrupt delivery), writing zero causes an 6377 * APIC-write VM exit. We plan to add a test for enabling 6378 * "virtual-interrupt delivery" in VMCS12, and that's where we 6379 * will test a self IPI with special processing. 6380 */ 6381 *val = 0x0; 6382 break; 6383 default: 6384 return false; 6385 } 6386 6387 return true; 6388 } 6389 6390 static bool special_processing_applies(u32 reg, u64 *val, 6391 bool virt_int_delivery) 6392 { 6393 bool special_processing = 6394 (reg == APIC_TASKPRI) || 6395 (virt_int_delivery && 6396 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6397 6398 if (special_processing) { 6399 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6400 return true; 6401 } 6402 6403 return false; 6404 } 6405 6406 static void virt_x2apic_mode_wr_expectation( 6407 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6408 bool virt_int_delivery, 6409 struct virt_x2apic_mode_expectation *expectation) 6410 { 6411 expectation->wr_exit_reason = VMX_VMCALL; 6412 expectation->wr_val = MAGIC_VAL_1; 6413 expectation->wr_only = false; 6414 6415 if (virt_x2apic_mode_on && 6416 special_processing_applies(reg, &expectation->wr_val, 6417 virt_int_delivery)) { 6418 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6419 if (reg == APIC_SELF_IPI) 6420 expectation->wr_exit_reason = VMX_APIC_WRITE; 6421 } else if (!disable_x2apic && 6422 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6423 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6424 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6425 expectation->wr_only = true; 6426 if (reg == APIC_ICR) 6427 expectation->wr_exit_reason = VMX_EXTINT; 6428 } else { 6429 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6430 /* 6431 * Writing 1 to a reserved bit triggers a #GP. 6432 * Thus, set the write value to 0, which seems 6433 * the most likely to detect a missed #GP. 6434 */ 6435 expectation->wr_val = 0; 6436 } 6437 } 6438 6439 static void virt_x2apic_mode_exit_expectation( 6440 u32 reg, struct virt_x2apic_mode_config *config, 6441 struct virt_x2apic_mode_expectation *expectation) 6442 { 6443 struct apic_reg_virt_config *base_config = 6444 &config->apic_reg_virt_config; 6445 bool virt_x2apic_mode_on = 6446 base_config->virtualize_x2apic_mode && 6447 config->use_msr_bitmaps && 6448 config->disable_x2apic_msr_intercepts && 6449 base_config->activate_secondary_controls; 6450 6451 virt_x2apic_mode_wr_expectation( 6452 reg, virt_x2apic_mode_on, config->disable_x2apic, 6453 config->virtual_interrupt_delivery, expectation); 6454 virt_x2apic_mode_rd_expectation( 6455 reg, virt_x2apic_mode_on, config->disable_x2apic, 6456 base_config->apic_register_virtualization, 6457 config->virtual_interrupt_delivery, expectation); 6458 } 6459 6460 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6461 /* 6462 * Baseline "virtualize x2APIC mode" configuration: 6463 * - virtualize x2APIC mode 6464 * - virtual-interrupt delivery 6465 * - APIC-register virtualization 6466 * - x2APIC MSR intercepts disabled 6467 * 6468 * Reads come from virtual APIC page, special processing applies to 6469 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6470 * APIC. 6471 */ 6472 { 6473 .name = "Baseline", 6474 .virt_x2apic_mode_config = { 6475 .virtual_interrupt_delivery = true, 6476 .use_msr_bitmaps = true, 6477 .disable_x2apic_msr_intercepts = true, 6478 .disable_x2apic = false, 6479 .apic_reg_virt_config = { 6480 .apic_register_virtualization = true, 6481 .use_tpr_shadow = true, 6482 .virtualize_apic_accesses = false, 6483 .virtualize_x2apic_mode = true, 6484 .activate_secondary_controls = true, 6485 }, 6486 }, 6487 }, 6488 { 6489 .name = "Baseline w/ x2apic disabled", 6490 .virt_x2apic_mode_config = { 6491 .virtual_interrupt_delivery = true, 6492 .use_msr_bitmaps = true, 6493 .disable_x2apic_msr_intercepts = true, 6494 .disable_x2apic = true, 6495 .apic_reg_virt_config = { 6496 .apic_register_virtualization = true, 6497 .use_tpr_shadow = true, 6498 .virtualize_apic_accesses = false, 6499 .virtualize_x2apic_mode = true, 6500 .activate_secondary_controls = true, 6501 }, 6502 }, 6503 }, 6504 6505 /* 6506 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6507 * APIC page, special processing applies to VTPR, and all other writes 6508 * pass through to L1 APIC. 6509 */ 6510 { 6511 .name = "Baseline - virtual interrupt delivery", 6512 .virt_x2apic_mode_config = { 6513 .virtual_interrupt_delivery = false, 6514 .use_msr_bitmaps = true, 6515 .disable_x2apic_msr_intercepts = true, 6516 .disable_x2apic = false, 6517 .apic_reg_virt_config = { 6518 .apic_register_virtualization = true, 6519 .use_tpr_shadow = true, 6520 .virtualize_apic_accesses = false, 6521 .virtualize_x2apic_mode = true, 6522 .activate_secondary_controls = true, 6523 }, 6524 }, 6525 }, 6526 6527 /* 6528 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6529 * through to L1's APIC, unless reading VTPR 6530 */ 6531 { 6532 .name = "Virtualize x2APIC mode, no APIC reg virt", 6533 .virt_x2apic_mode_config = { 6534 .virtual_interrupt_delivery = true, 6535 .use_msr_bitmaps = true, 6536 .disable_x2apic_msr_intercepts = true, 6537 .disable_x2apic = false, 6538 .apic_reg_virt_config = { 6539 .apic_register_virtualization = false, 6540 .use_tpr_shadow = true, 6541 .virtualize_apic_accesses = false, 6542 .virtualize_x2apic_mode = true, 6543 .activate_secondary_controls = true, 6544 }, 6545 }, 6546 }, 6547 { 6548 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6549 .virt_x2apic_mode_config = { 6550 .virtual_interrupt_delivery = true, 6551 .use_msr_bitmaps = true, 6552 .disable_x2apic_msr_intercepts = true, 6553 .disable_x2apic = true, 6554 .apic_reg_virt_config = { 6555 .apic_register_virtualization = false, 6556 .use_tpr_shadow = true, 6557 .virtualize_apic_accesses = false, 6558 .virtualize_x2apic_mode = true, 6559 .activate_secondary_controls = true, 6560 }, 6561 }, 6562 }, 6563 6564 /* 6565 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6566 * and disable intercepts for the x2APIC MSRs, but fail to enable 6567 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6568 * MSRs). 6569 */ 6570 { 6571 .name = "Fail to enable activate secondary controls", 6572 .virt_x2apic_mode_config = { 6573 .virtual_interrupt_delivery = true, 6574 .use_msr_bitmaps = true, 6575 .disable_x2apic_msr_intercepts = true, 6576 .disable_x2apic = false, 6577 .apic_reg_virt_config = { 6578 .apic_register_virtualization = true, 6579 .use_tpr_shadow = true, 6580 .virtualize_apic_accesses = false, 6581 .virtualize_x2apic_mode = true, 6582 .activate_secondary_controls = false, 6583 }, 6584 }, 6585 }, 6586 6587 /* 6588 * Enable "APIC-register virtualization" and enable "activate secondary 6589 * controls" and disable intercepts for the x2APIC MSRs, but do not 6590 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6591 * gets access to L1's x2APIC MSRs). 6592 */ 6593 { 6594 .name = "Fail to enable virtualize x2APIC mode", 6595 .virt_x2apic_mode_config = { 6596 .virtual_interrupt_delivery = true, 6597 .use_msr_bitmaps = true, 6598 .disable_x2apic_msr_intercepts = true, 6599 .disable_x2apic = false, 6600 .apic_reg_virt_config = { 6601 .apic_register_virtualization = true, 6602 .use_tpr_shadow = true, 6603 .virtualize_apic_accesses = false, 6604 .virtualize_x2apic_mode = false, 6605 .activate_secondary_controls = true, 6606 }, 6607 }, 6608 }, 6609 6610 /* 6611 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6612 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6613 */ 6614 { 6615 .name = "Baseline", 6616 .virt_x2apic_mode_config = { 6617 .virtual_interrupt_delivery = true, 6618 .use_msr_bitmaps = true, 6619 .disable_x2apic_msr_intercepts = true, 6620 .disable_x2apic = false, 6621 .apic_reg_virt_config = { 6622 .apic_register_virtualization = true, 6623 .use_tpr_shadow = true, 6624 .virtualize_apic_accesses = false, 6625 .virtualize_x2apic_mode = false, 6626 .activate_secondary_controls = true, 6627 }, 6628 }, 6629 }, 6630 }; 6631 6632 enum X2apic_op { 6633 X2APIC_OP_RD, 6634 X2APIC_OP_WR, 6635 X2APIC_TERMINATE, 6636 }; 6637 6638 static u64 vmx_x2apic_read(u32 reg) 6639 { 6640 u32 msr_addr = x2apic_msr(reg); 6641 u64 val; 6642 6643 val = rdmsr(msr_addr); 6644 6645 return val; 6646 } 6647 6648 static void vmx_x2apic_write(u32 reg, u64 val) 6649 { 6650 u32 msr_addr = x2apic_msr(reg); 6651 6652 wrmsr(msr_addr, val); 6653 } 6654 6655 struct virt_x2apic_mode_guest_args { 6656 enum X2apic_op op; 6657 u32 reg; 6658 u64 val; 6659 bool should_gp; 6660 u64 (*virt_fn)(u64); 6661 } virt_x2apic_mode_guest_args; 6662 6663 static volatile bool handle_x2apic_gp_ran; 6664 static volatile u32 handle_x2apic_gp_insn_len; 6665 static void handle_x2apic_gp(struct ex_regs *regs) 6666 { 6667 handle_x2apic_gp_ran = true; 6668 regs->rip += handle_x2apic_gp_insn_len; 6669 } 6670 6671 static handler setup_x2apic_gp_handler(void) 6672 { 6673 handler old_handler; 6674 6675 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6676 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6677 handle_x2apic_gp_insn_len = 2; 6678 6679 return old_handler; 6680 } 6681 6682 static void teardown_x2apic_gp_handler(handler old_handler) 6683 { 6684 handle_exception(GP_VECTOR, old_handler); 6685 6686 /* 6687 * Defensively reset instruction length, so that if the handler is 6688 * incorrectly used, it will loop infinitely, rather than run off into 6689 * la la land. 6690 */ 6691 handle_x2apic_gp_insn_len = 0; 6692 handle_x2apic_gp_ran = false; 6693 } 6694 6695 static void virt_x2apic_mode_guest(void) 6696 { 6697 volatile struct virt_x2apic_mode_guest_args *args = 6698 &virt_x2apic_mode_guest_args; 6699 6700 for (;;) { 6701 enum X2apic_op op = args->op; 6702 u32 reg = args->reg; 6703 u64 val = args->val; 6704 bool should_gp = args->should_gp; 6705 u64 (*virt_fn)(u64) = args->virt_fn; 6706 handler old_handler; 6707 6708 if (op == X2APIC_TERMINATE) 6709 break; 6710 6711 if (should_gp) { 6712 TEST_ASSERT(!handle_x2apic_gp_ran); 6713 old_handler = setup_x2apic_gp_handler(); 6714 } 6715 6716 if (op == X2APIC_OP_RD) { 6717 u64 ret = vmx_x2apic_read(reg); 6718 6719 if (!should_gp) { 6720 u64 want = virt_fn(val); 6721 u64 got = virt_fn(ret); 6722 6723 report(got == want, 6724 "APIC read; got 0x%lx, want 0x%lx.", 6725 got, want); 6726 } 6727 } else if (op == X2APIC_OP_WR) { 6728 vmx_x2apic_write(reg, val); 6729 } 6730 6731 if (should_gp) { 6732 report(handle_x2apic_gp_ran, 6733 "x2APIC op triggered GP."); 6734 teardown_x2apic_gp_handler(old_handler); 6735 } 6736 6737 /* 6738 * The L1 should always execute a vmcall after it's done testing 6739 * an individual APIC operation. This helps to validate that the 6740 * L1 and L2 are in sync with each other, as expected. 6741 */ 6742 vmcall(); 6743 } 6744 } 6745 6746 static void test_x2apic_rd( 6747 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6748 u32 *virtual_apic_page) 6749 { 6750 u64 val = expectation->rd_val; 6751 u32 exit_reason_want = expectation->rd_exit_reason; 6752 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6753 6754 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6755 6756 /* Configure guest to do an x2apic read */ 6757 args->op = X2APIC_OP_RD; 6758 args->reg = reg; 6759 args->val = val; 6760 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6761 args->virt_fn = expectation->virt_fn; 6762 6763 /* Setup virtual APIC page */ 6764 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6765 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6766 6767 /* Enter guest */ 6768 enter_guest(); 6769 6770 if (exit_reason_want != VMX_VMCALL) { 6771 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6772 } 6773 6774 skip_exit_vmcall(); 6775 report_prefix_pop(); 6776 } 6777 6778 static volatile bool handle_x2apic_ipi_ran; 6779 static void handle_x2apic_ipi(isr_regs_t *regs) 6780 { 6781 handle_x2apic_ipi_ran = true; 6782 eoi(); 6783 } 6784 6785 static void test_x2apic_wr( 6786 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6787 u32 *virtual_apic_page) 6788 { 6789 u64 val = expectation->wr_val; 6790 u32 exit_reason_want = expectation->wr_exit_reason; 6791 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6792 int ipi_vector = 0xf1; 6793 u32 restore_val = 0; 6794 6795 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6796 6797 /* Configure guest to do an x2apic read */ 6798 args->op = X2APIC_OP_WR; 6799 args->reg = reg; 6800 args->val = val; 6801 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6802 6803 /* Setup virtual APIC page */ 6804 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6805 virtual_apic_page[apic_reg_index(reg)] = 0; 6806 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6807 restore_val = apic_read(reg); 6808 6809 /* Setup IPI handler */ 6810 handle_x2apic_ipi_ran = false; 6811 handle_irq(ipi_vector, handle_x2apic_ipi); 6812 6813 /* Enter guest */ 6814 enter_guest(); 6815 6816 /* 6817 * Validate the behavior and 6818 * pass a magic value back to the guest. 6819 */ 6820 if (exit_reason_want == VMX_EXTINT) { 6821 assert_exit_reason(exit_reason_want); 6822 6823 /* Clear the external interrupt. */ 6824 irq_enable(); 6825 asm volatile ("nop"); 6826 irq_disable(); 6827 report(handle_x2apic_ipi_ran, 6828 "Got pending interrupt after IRQ enabled."); 6829 6830 enter_guest(); 6831 } else if (exit_reason_want == VMX_APIC_WRITE) { 6832 assert_exit_reason(exit_reason_want); 6833 report(virtual_apic_page[apic_reg_index(reg)] == val, 6834 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6835 apic_reg_index(reg), 6836 virtual_apic_page[apic_reg_index(reg)], val); 6837 6838 /* Reenter guest so it can consume/check rcx and exit again. */ 6839 enter_guest(); 6840 } else if (exit_reason_want != VMX_VMCALL) { 6841 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6842 } 6843 6844 assert_exit_reason(VMX_VMCALL); 6845 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6846 u64 want = val; 6847 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6848 6849 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6850 want); 6851 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6852 if (!expectation->wr_only) { 6853 u32 got = apic_read(reg); 6854 bool ok; 6855 6856 /* 6857 * When L1's TPR is passed through to L2, the lower 6858 * nibble can be lost. For example, if L2 executes 6859 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6860 * 6861 * Here's how the lower nibble can get lost: 6862 * 1. L2 executes WRMSR(0x808, 0x78). 6863 * 2. L2 exits to L0 with a WRMSR exit. 6864 * 3. L0 emulates WRMSR, by writing L1's TPR. 6865 * 4. L0 re-enters L2. 6866 * 5. L2 exits to L0 (reason doesn't matter). 6867 * 6. L0 reflects L2's exit to L1. 6868 * 7. Before entering L1, L0 exits to user-space 6869 * (e.g., to satisfy TPR access reporting). 6870 * 8. User-space executes KVM_SET_REGS ioctl, which 6871 * clears the lower nibble of L1's TPR. 6872 */ 6873 if (reg == APIC_TASKPRI) { 6874 got = apic_virt_nibble1(got); 6875 val = apic_virt_nibble1(val); 6876 } 6877 6878 ok = got == val; 6879 report(ok, 6880 "non-virtualized write; val is 0x%x, want 0x%lx", 6881 got, val); 6882 apic_write(reg, restore_val); 6883 } else { 6884 report_pass("non-virtualized and write-only OK"); 6885 } 6886 } 6887 skip_exit_insn(); 6888 6889 report_prefix_pop(); 6890 } 6891 6892 static enum Config_type configure_virt_x2apic_mode_test( 6893 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6894 u8 *msr_bitmap_page) 6895 { 6896 int msr; 6897 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6898 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6899 6900 /* x2apic-specific VMCS config */ 6901 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6902 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6903 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6904 } else { 6905 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6906 } 6907 6908 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6909 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6910 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6911 return CONFIG_TYPE_UNSUPPORTED; 6912 } 6913 cpu_exec_ctrl1 |= CPU_VINTD; 6914 } else { 6915 cpu_exec_ctrl1 &= ~CPU_VINTD; 6916 } 6917 6918 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6919 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6920 6921 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6922 for (msr = 0x800; msr <= 0x8ff; msr++) { 6923 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6924 clear_bit(msr, msr_bitmap_page + 0x000); 6925 clear_bit(msr, msr_bitmap_page + 0x800); 6926 } else { 6927 set_bit(msr, msr_bitmap_page + 0x000); 6928 set_bit(msr, msr_bitmap_page + 0x800); 6929 } 6930 } 6931 6932 /* x2APIC mode can impact virtualization */ 6933 reset_apic(); 6934 if (!virt_x2apic_mode_config->disable_x2apic) 6935 enable_x2apic(); 6936 6937 return configure_apic_reg_virt_test( 6938 &virt_x2apic_mode_config->apic_reg_virt_config); 6939 } 6940 6941 static void virt_x2apic_mode_test(void) 6942 { 6943 u32 *virtual_apic_page; 6944 u8 *msr_bitmap_page; 6945 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6946 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6947 int i; 6948 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6949 6950 if (!cpu_has_apicv()) { 6951 report_skip(__func__); 6952 return; 6953 } 6954 6955 /* 6956 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6957 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6958 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6959 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6960 * "Virtualize x2APIC mod" control set, even when it didn't. 6961 */ 6962 if (has_spec_ctrl()) 6963 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6964 6965 /* 6966 * Check that VMCS12 supports: 6967 * - "Virtual-APIC address", indicated by "use TPR shadow" 6968 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6969 */ 6970 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6971 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6972 return; 6973 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6974 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6975 return; 6976 } 6977 6978 test_set_guest(virt_x2apic_mode_guest); 6979 6980 virtual_apic_page = alloc_page(); 6981 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6982 6983 msr_bitmap_page = alloc_page(); 6984 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6985 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6986 6987 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6988 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6989 &virt_x2apic_mode_tests[i]; 6990 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6991 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6992 enum Config_type config_type; 6993 u32 reg; 6994 6995 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6996 config_type = 6997 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 6998 msr_bitmap_page); 6999 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 7000 report_skip("Skip because of missing features.\n"); 7001 continue; 7002 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 7003 enter_guest_with_bad_controls(); 7004 continue; 7005 } 7006 7007 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 7008 struct virt_x2apic_mode_expectation expectation; 7009 7010 virt_x2apic_mode_exit_expectation( 7011 reg, virt_x2apic_mode_config, &expectation); 7012 7013 test_x2apic_rd(reg, &expectation, virtual_apic_page); 7014 test_x2apic_wr(reg, &expectation, virtual_apic_page); 7015 } 7016 } 7017 7018 7019 /* Terminate the guest */ 7020 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7021 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7022 args->op = X2APIC_TERMINATE; 7023 enter_guest(); 7024 assert_exit_reason(VMX_VMCALL); 7025 } 7026 7027 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 7028 { 7029 u64 val; 7030 u64 cr_saved = vmcs_read(cr); 7031 int i; 7032 7033 val = fixed0 & fixed1; 7034 if (cr == HOST_CR4) 7035 vmcs_write(cr, val | X86_CR4_PAE); 7036 else 7037 vmcs_write(cr, val); 7038 report_prefix_pushf("%s %lx", cr_name, val); 7039 if (val == fixed0) 7040 test_vmx_vmlaunch(0); 7041 else 7042 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7043 report_prefix_pop(); 7044 7045 for (i = 0; i < 64; i++) { 7046 7047 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7048 if ((fixed1 & (1ull << i)) == 0) { 7049 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7050 (1ull << i) & X86_CR4_SMAP)) 7051 continue; 7052 7053 vmcs_write(cr, cr_saved | (1ull << i)); 7054 report_prefix_pushf("%s %llx", cr_name, 7055 cr_saved | (1ull << i)); 7056 test_vmx_vmlaunch( 7057 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7058 report_prefix_pop(); 7059 } 7060 7061 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7062 if (fixed0 & (1ull << i)) { 7063 vmcs_write(cr, cr_saved & ~(1ull << i)); 7064 report_prefix_pushf("%s %llx", cr_name, 7065 cr_saved & ~(1ull << i)); 7066 test_vmx_vmlaunch( 7067 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7068 report_prefix_pop(); 7069 } 7070 } 7071 7072 vmcs_write(cr, cr_saved); 7073 } 7074 7075 /* 7076 * 1. The CR0 field must not set any bit to a value not supported in VMX 7077 * operation. 7078 * 2. The CR4 field must not set any bit to a value not supported in VMX 7079 * operation. 7080 * 3. On processors that support Intel 64 architecture, the CR3 field must 7081 * be such that bits 63:52 and bits in the range 51:32 beyond the 7082 * processor's physical-address width must be 0. 7083 * 7084 * [Intel SDM] 7085 */ 7086 static void test_host_ctl_regs(void) 7087 { 7088 u64 fixed0, fixed1, cr3, cr3_saved; 7089 int i; 7090 7091 /* Test CR0 */ 7092 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7093 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7094 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7095 7096 /* Test CR4 */ 7097 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7098 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7099 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7100 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7101 7102 /* Test CR3 */ 7103 cr3_saved = vmcs_read(HOST_CR3); 7104 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7105 cr3 = cr3_saved | (1ul << i); 7106 vmcs_write(HOST_CR3, cr3); 7107 report_prefix_pushf("HOST_CR3 %lx", cr3); 7108 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7109 report_prefix_pop(); 7110 } 7111 7112 vmcs_write(HOST_CR3, cr3_saved); 7113 } 7114 7115 static void test_efer_vmlaunch(u32 fld, bool ok) 7116 { 7117 if (fld == HOST_EFER) { 7118 if (ok) 7119 test_vmx_vmlaunch(0); 7120 else 7121 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7122 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7123 } else { 7124 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7125 } 7126 } 7127 7128 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7129 u32 ctrl_fld, u64 ctrl, 7130 int i, const char *efer_bit_name) 7131 { 7132 bool ok; 7133 7134 ok = true; 7135 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7136 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7137 ok = false; 7138 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7139 ok = false; 7140 } 7141 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7142 /* Check LMA too since CR0.PG is set. */ 7143 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7144 ok = false; 7145 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7146 ok = false; 7147 } 7148 7149 /* 7150 * Skip the test if it would enter the guest in 32-bit mode. 7151 * Perhaps write the test in assembly and make sure it 7152 * can be run in either mode? 7153 */ 7154 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7155 return; 7156 7157 vmcs_write(ctrl_fld, ctrl); 7158 vmcs_write(fld, efer); 7159 report_prefix_pushf("%s %s bit turned %s, controls %s", 7160 fld_name, efer_bit_name, 7161 (i & 1) ? "on" : "off", 7162 (i & 2) ? "on" : "off"); 7163 7164 test_efer_vmlaunch(fld, ok); 7165 report_prefix_pop(); 7166 } 7167 7168 static void test_efer_bit(u32 fld, const char * fld_name, 7169 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7170 const char *efer_bit_name) 7171 { 7172 u64 efer_saved = vmcs_read(fld); 7173 u32 ctrl_saved = vmcs_read(ctrl_fld); 7174 int i; 7175 7176 for (i = 0; i < 4; i++) { 7177 u64 efer = efer_saved & ~efer_bit; 7178 u64 ctrl = ctrl_saved & ~ctrl_bit; 7179 7180 if (i & 1) 7181 efer |= efer_bit; 7182 if (i & 2) 7183 ctrl |= ctrl_bit; 7184 7185 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7186 i, efer_bit_name); 7187 } 7188 7189 vmcs_write(ctrl_fld, ctrl_saved); 7190 vmcs_write(fld, efer_saved); 7191 } 7192 7193 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7194 u64 ctrl_bit1, u64 ctrl_bit2) 7195 { 7196 u64 efer_saved = vmcs_read(fld); 7197 u32 ctrl_saved = vmcs_read(ctrl_fld); 7198 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7199 u64 i; 7200 u64 efer; 7201 7202 if (cpu_has_efer_nx()) 7203 efer_reserved_bits &= ~EFER_NX; 7204 7205 if (!ctrl_bit1) { 7206 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7207 goto test_entry_exit_mode; 7208 } 7209 7210 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7211 test_efer_vmlaunch(fld, true); 7212 report_prefix_pop(); 7213 7214 /* 7215 * Check reserved bits 7216 */ 7217 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7218 for (i = 0; i < 64; i++) { 7219 if ((1ull << i) & efer_reserved_bits) { 7220 efer = efer_saved | (1ull << i); 7221 vmcs_write(fld, efer); 7222 report_prefix_pushf("%s %lx", fld_name, efer); 7223 test_efer_vmlaunch(fld, true); 7224 report_prefix_pop(); 7225 } 7226 } 7227 7228 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7229 for (i = 0; i < 64; i++) { 7230 if ((1ull << i) & efer_reserved_bits) { 7231 efer = efer_saved | (1ull << i); 7232 vmcs_write(fld, efer); 7233 report_prefix_pushf("%s %lx", fld_name, efer); 7234 test_efer_vmlaunch(fld, false); 7235 report_prefix_pop(); 7236 } 7237 } 7238 7239 vmcs_write(ctrl_fld, ctrl_saved); 7240 vmcs_write(fld, efer_saved); 7241 7242 /* 7243 * Check LMA and LME bits 7244 */ 7245 test_efer_bit(fld, fld_name, 7246 ctrl_fld, ctrl_bit1, 7247 EFER_LMA, 7248 "EFER_LMA"); 7249 test_efer_bit(fld, fld_name, 7250 ctrl_fld, ctrl_bit1, 7251 EFER_LME, 7252 "EFER_LME"); 7253 7254 test_entry_exit_mode: 7255 test_efer_bit(fld, fld_name, 7256 ctrl_fld, ctrl_bit2, 7257 EFER_LMA, 7258 "EFER_LMA"); 7259 test_efer_bit(fld, fld_name, 7260 ctrl_fld, ctrl_bit2, 7261 EFER_LME, 7262 "EFER_LME"); 7263 } 7264 7265 /* 7266 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7267 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7268 * the values of the LMA and LME bits in the field must each be that of 7269 * the 'host address-space size' VM-exit control. 7270 * 7271 * [Intel SDM] 7272 */ 7273 static void test_host_efer(void) 7274 { 7275 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7276 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7277 EXI_HOST_64); 7278 } 7279 7280 /* 7281 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7282 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7283 * the values of the LMA and LME bits in the field must each be that of 7284 * the 'IA32e-mode guest' VM-exit control. 7285 */ 7286 static void test_guest_efer(void) 7287 { 7288 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7289 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7290 return; 7291 } 7292 7293 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7294 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7295 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7296 ENT_GUEST_64); 7297 } 7298 7299 /* 7300 * PAT values higher than 8 are uninteresting since they're likely lumped 7301 * in with "8". We only test values above 8 one bit at a time, 7302 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7303 */ 7304 #define PAT_VAL_LIMIT 8 7305 7306 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7307 u64 ctrl_bit) 7308 { 7309 u32 ctrl_saved = vmcs_read(ctrl_field); 7310 u64 pat_saved = vmcs_read(field); 7311 u64 i, val; 7312 u32 j; 7313 int error; 7314 7315 vmcs_clear_bits(ctrl_field, ctrl_bit); 7316 7317 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7318 /* Test PAT0..PAT7 fields */ 7319 for (j = 0; j < (i ? 8 : 1); j++) { 7320 val = i << j * 8; 7321 vmcs_write(field, val); 7322 if (field == HOST_PAT) { 7323 report_prefix_pushf("%s %lx", field_name, val); 7324 test_vmx_vmlaunch(0); 7325 report_prefix_pop(); 7326 7327 } else { // GUEST_PAT 7328 test_guest_state("ENT_LOAD_PAT enabled", false, 7329 val, "GUEST_PAT"); 7330 } 7331 } 7332 } 7333 7334 vmcs_set_bits(ctrl_field, ctrl_bit); 7335 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7336 /* Test PAT0..PAT7 fields */ 7337 for (j = 0; j < (i ? 8 : 1); j++) { 7338 val = i << j * 8; 7339 vmcs_write(field, val); 7340 7341 if (field == HOST_PAT) { 7342 report_prefix_pushf("%s %lx", field_name, val); 7343 if (i == 0x2 || i == 0x3 || i >= 0x8) 7344 error = 7345 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7346 else 7347 error = 0; 7348 7349 test_vmx_vmlaunch(error); 7350 report_prefix_pop(); 7351 7352 } else { // GUEST_PAT 7353 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7354 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7355 val, "GUEST_PAT"); 7356 } 7357 7358 } 7359 } 7360 7361 vmcs_write(ctrl_field, ctrl_saved); 7362 vmcs_write(field, pat_saved); 7363 } 7364 7365 /* 7366 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7367 * for the IA32_PAT MSR must be one that could be written by WRMSR 7368 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7369 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7370 * 6 (WB), or 7 (UC-). 7371 * 7372 * [Intel SDM] 7373 */ 7374 static void test_load_host_pat(void) 7375 { 7376 /* 7377 * "load IA32_PAT" VM-exit control 7378 */ 7379 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7380 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7381 return; 7382 } 7383 7384 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7385 } 7386 7387 union cpuidA_eax { 7388 struct { 7389 unsigned int version_id:8; 7390 unsigned int num_counters_gp:8; 7391 unsigned int bit_width:8; 7392 unsigned int mask_length:8; 7393 } split; 7394 unsigned int full; 7395 }; 7396 7397 union cpuidA_edx { 7398 struct { 7399 unsigned int num_counters_fixed:5; 7400 unsigned int bit_width_fixed:8; 7401 unsigned int reserved:9; 7402 } split; 7403 unsigned int full; 7404 }; 7405 7406 static bool valid_pgc(u64 val) 7407 { 7408 struct cpuid id; 7409 union cpuidA_eax eax; 7410 union cpuidA_edx edx; 7411 u64 mask; 7412 7413 id = cpuid(0xA); 7414 eax.full = id.a; 7415 edx.full = id.d; 7416 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7417 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7418 7419 return !(val & mask); 7420 } 7421 7422 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7423 { 7424 u32 inst_err; 7425 u64 obs; 7426 bool success; 7427 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7428 7429 if (host) { 7430 success = vmlaunch_succeeds(); 7431 obs = rdmsr(data->msr); 7432 if (!success) { 7433 inst_err = vmcs_read(VMX_INST_ERROR); 7434 report(xerror == inst_err, "vmlaunch failed, " 7435 "VMX Inst Error is %d (expected %d)", 7436 inst_err, xerror); 7437 } else { 7438 report(!data->enabled || data->exp == obs, 7439 "Host state is 0x%lx (expected 0x%lx)", 7440 obs, data->exp); 7441 report(success != xfail, "vmlaunch succeeded"); 7442 } 7443 } else { 7444 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7445 GUEST_PERF_GLOBAL_CTRL, 7446 "GUEST_PERF_GLOBAL_CTRL"); 7447 } 7448 } 7449 7450 /* 7451 * test_load_perf_global_ctrl is a generic function for testing the 7452 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7453 * tests the provided ctrl_val when disabled and enabled. 7454 * 7455 * @nr: VMCS field number corresponding to the host/guest state field 7456 * @name: Name of the above VMCS field for printing in test report 7457 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7458 * @ctrl_val: Bit to set on the ctrl_field 7459 */ 7460 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7461 const char *ctrl_name, u64 ctrl_val) 7462 { 7463 u64 ctrl_saved = vmcs_read(ctrl_nr); 7464 u64 pgc_saved = vmcs_read(nr); 7465 u64 i, val; 7466 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7467 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7468 7469 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7470 msr_bmp_init(); 7471 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7472 data->enabled = false; 7473 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7474 ctrl_name); 7475 7476 for (i = 0; i < 64; i++) { 7477 val = 1ull << i; 7478 vmcs_write(nr, val); 7479 report_prefix_pushf("%s = 0x%lx", name, val); 7480 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7481 report_prefix_pop(); 7482 } 7483 report_prefix_pop(); 7484 7485 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7486 data->enabled = true; 7487 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7488 ctrl_name); 7489 for (i = 0; i < 64; i++) { 7490 val = 1ull << i; 7491 data->exp = val; 7492 vmcs_write(nr, val); 7493 report_prefix_pushf("%s = 0x%lx", name, val); 7494 if (valid_pgc(val)) { 7495 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7496 } else { 7497 if (host) 7498 test_pgc_vmlaunch( 7499 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7500 0, 7501 true, 7502 host); 7503 else 7504 test_pgc_vmlaunch( 7505 0, 7506 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7507 true, 7508 host); 7509 } 7510 report_prefix_pop(); 7511 } 7512 7513 data->enabled = false; 7514 report_prefix_pop(); 7515 vmcs_write(ctrl_nr, ctrl_saved); 7516 vmcs_write(nr, pgc_saved); 7517 } 7518 7519 static void test_load_host_perf_global_ctrl(void) 7520 { 7521 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7522 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7523 return; 7524 } 7525 7526 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7527 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7528 } 7529 7530 7531 static void test_load_guest_perf_global_ctrl(void) 7532 { 7533 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7534 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7535 return; 7536 } 7537 7538 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7539 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7540 } 7541 7542 7543 /* 7544 * test_vmcs_field - test a value for the given VMCS field 7545 * @field: VMCS field 7546 * @field_name: string name of VMCS field 7547 * @bit_start: starting bit 7548 * @bit_end: ending bit 7549 * @val: value that the bit range must or must not contain 7550 * @valid_val: whether value given in 'val' must be valid or not 7551 * @error: expected VMCS error when vmentry fails for an invalid value 7552 */ 7553 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7554 u32 bit_end, u64 val, bool valid_val, u32 error) 7555 { 7556 u64 field_saved = vmcs_read(field); 7557 u32 i; 7558 u64 tmp; 7559 u32 bit_on; 7560 u64 mask = ~0ull; 7561 7562 mask = (mask >> bit_end) << bit_end; 7563 mask = mask | ((1 << bit_start) - 1); 7564 tmp = (field_saved & mask) | (val << bit_start); 7565 7566 vmcs_write(field, tmp); 7567 report_prefix_pushf("%s %lx", field_name, tmp); 7568 if (valid_val) 7569 test_vmx_vmlaunch(0); 7570 else 7571 test_vmx_vmlaunch(error); 7572 report_prefix_pop(); 7573 7574 for (i = bit_start; i <= bit_end; i = i + 2) { 7575 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7576 if (bit_on) 7577 tmp = field_saved | (1ull << i); 7578 else 7579 tmp = field_saved & ~(1ull << i); 7580 vmcs_write(field, tmp); 7581 report_prefix_pushf("%s %lx", field_name, tmp); 7582 if (valid_val) 7583 test_vmx_vmlaunch(error); 7584 else 7585 test_vmx_vmlaunch(0); 7586 report_prefix_pop(); 7587 } 7588 7589 vmcs_write(field, field_saved); 7590 } 7591 7592 static void test_canonical(u64 field, const char * field_name, bool host) 7593 { 7594 u64 addr_saved = vmcs_read(field); 7595 7596 /* 7597 * Use the existing value if possible. Writing a random canonical 7598 * value is not an option as doing so would corrupt the field being 7599 * tested and likely hose the test. 7600 */ 7601 if (is_canonical(addr_saved)) { 7602 if (host) { 7603 report_prefix_pushf("%s %lx", field_name, addr_saved); 7604 test_vmx_vmlaunch(0); 7605 report_prefix_pop(); 7606 } else { 7607 test_guest_state("Test canonical address", false, 7608 addr_saved, field_name); 7609 } 7610 } 7611 7612 vmcs_write(field, NONCANONICAL); 7613 7614 if (host) { 7615 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7616 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7617 report_prefix_pop(); 7618 } else { 7619 test_guest_state("Test non-canonical address", true, 7620 NONCANONICAL, field_name); 7621 } 7622 7623 vmcs_write(field, addr_saved); 7624 } 7625 7626 #define TEST_RPL_TI_FLAGS(reg, name) \ 7627 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7628 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7629 7630 #define TEST_CS_TR_FLAGS(reg, name) \ 7631 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7632 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7633 7634 /* 7635 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7636 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7637 * 2. The selector fields for CS and TR cannot be 0000H. 7638 * 3. The selector field for SS cannot be 0000H if the "host address-space 7639 * size" VM-exit control is 0. 7640 * 4. On processors that support Intel 64 architecture, the base-address 7641 * fields for FS, GS and TR must contain canonical addresses. 7642 */ 7643 static void test_host_segment_regs(void) 7644 { 7645 u16 selector_saved; 7646 7647 /* 7648 * Test RPL and TI flags 7649 */ 7650 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7651 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7652 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7653 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7654 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7655 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7656 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7657 7658 /* 7659 * Test that CS and TR fields can not be 0x0000 7660 */ 7661 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7662 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7663 7664 /* 7665 * SS field can not be 0x0000 if "host address-space size" VM-exit 7666 * control is 0 7667 */ 7668 selector_saved = vmcs_read(HOST_SEL_SS); 7669 vmcs_write(HOST_SEL_SS, 0); 7670 report_prefix_pushf("HOST_SEL_SS 0"); 7671 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7672 test_vmx_vmlaunch(0); 7673 } else { 7674 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7675 } 7676 report_prefix_pop(); 7677 7678 vmcs_write(HOST_SEL_SS, selector_saved); 7679 7680 /* 7681 * Base address for FS, GS and TR must be canonical 7682 */ 7683 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7684 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7685 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7686 } 7687 7688 /* 7689 * On processors that support Intel 64 architecture, the base-address 7690 * fields for GDTR and IDTR must contain canonical addresses. 7691 */ 7692 static void test_host_desc_tables(void) 7693 { 7694 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7695 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7696 } 7697 7698 /* 7699 * If the "host address-space size" VM-exit control is 0, the following must 7700 * hold: 7701 * - The "IA-32e mode guest" VM-entry control is 0. 7702 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7703 * - Bits 63:32 in the RIP field are 0. 7704 * 7705 * If the "host address-space size" VM-exit control is 1, the following must 7706 * hold: 7707 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7708 * - The RIP field contains a canonical address. 7709 * 7710 */ 7711 static void test_host_addr_size(void) 7712 { 7713 u64 cr4_saved = vmcs_read(HOST_CR4); 7714 u64 rip_saved = vmcs_read(HOST_RIP); 7715 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7716 int i; 7717 u64 tmp; 7718 7719 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7720 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7721 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7722 test_vmx_vmlaunch(0); 7723 report_prefix_pop(); 7724 7725 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7726 report_prefix_pushf("\"CR4.PCIDE\" set"); 7727 test_vmx_vmlaunch(0); 7728 report_prefix_pop(); 7729 7730 for (i = 32; i <= 63; i = i + 4) { 7731 tmp = rip_saved | 1ull << i; 7732 vmcs_write(HOST_RIP, tmp); 7733 report_prefix_pushf("HOST_RIP %lx", tmp); 7734 test_vmx_vmlaunch(0); 7735 report_prefix_pop(); 7736 } 7737 7738 if (cr4_saved & X86_CR4_PAE) { 7739 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7740 report_prefix_pushf("\"CR4.PAE\" unset"); 7741 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7742 } else { 7743 report_prefix_pushf("\"CR4.PAE\" set"); 7744 test_vmx_vmlaunch(0); 7745 } 7746 report_prefix_pop(); 7747 7748 vmcs_write(HOST_RIP, NONCANONICAL); 7749 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7750 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7751 report_prefix_pop(); 7752 7753 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7754 vmcs_write(HOST_RIP, rip_saved); 7755 vmcs_write(HOST_CR4, cr4_saved); 7756 7757 /* Restore host's active RIP and CR4 values. */ 7758 report_prefix_pushf("restore host state"); 7759 test_vmx_vmlaunch(0); 7760 report_prefix_pop(); 7761 } 7762 } 7763 7764 /* 7765 * Check that the virtual CPU checks the VMX Host State Area as 7766 * documented in the Intel SDM. 7767 */ 7768 static void vmx_host_state_area_test(void) 7769 { 7770 /* 7771 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7772 * fail due to invalid guest state, should we make it that 7773 * far. 7774 */ 7775 vmcs_write(GUEST_RFLAGS, 0); 7776 7777 test_host_ctl_regs(); 7778 7779 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7780 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7781 7782 test_host_efer(); 7783 test_load_host_pat(); 7784 test_host_segment_regs(); 7785 test_host_desc_tables(); 7786 test_host_addr_size(); 7787 test_load_host_perf_global_ctrl(); 7788 } 7789 7790 /* 7791 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7792 * the DR7 field must be 0. 7793 * 7794 * [Intel SDM] 7795 */ 7796 static void test_guest_dr7(void) 7797 { 7798 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7799 u64 dr7_saved = vmcs_read(GUEST_DR7); 7800 u64 val; 7801 int i; 7802 7803 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7804 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7805 for (i = 0; i < 64; i++) { 7806 val = 1ull << i; 7807 vmcs_write(GUEST_DR7, val); 7808 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7809 val, "GUEST_DR7"); 7810 } 7811 } 7812 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7813 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7814 for (i = 0; i < 64; i++) { 7815 val = 1ull << i; 7816 vmcs_write(GUEST_DR7, val); 7817 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7818 val, "GUEST_DR7"); 7819 } 7820 } 7821 vmcs_write(GUEST_DR7, dr7_saved); 7822 vmcs_write(ENT_CONTROLS, ent_saved); 7823 } 7824 7825 /* 7826 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7827 * for the IA32_PAT MSR must be one that could be written by WRMSR 7828 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7829 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7830 * 6 (WB), or 7 (UC-). 7831 * 7832 * [Intel SDM] 7833 */ 7834 static void test_load_guest_pat(void) 7835 { 7836 /* 7837 * "load IA32_PAT" VM-entry control 7838 */ 7839 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7840 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7841 return; 7842 } 7843 7844 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7845 } 7846 7847 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7848 7849 /* 7850 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7851 * checks are performed on the field for the IA32_BNDCFGS MSR: 7852 * 7853 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7854 * - The linear address in bits 63:12 must be canonical. 7855 * 7856 * [Intel SDM] 7857 */ 7858 static void test_load_guest_bndcfgs(void) 7859 { 7860 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7861 u64 bndcfgs; 7862 7863 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7864 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7865 return; 7866 } 7867 7868 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7869 7870 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7871 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7872 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7873 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7874 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7875 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7876 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7877 7878 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7879 7880 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7881 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7882 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7883 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7884 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7885 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7886 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7887 7888 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7889 } 7890 7891 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7892 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7893 7894 7895 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7896 do { \ 7897 vmcs_write(sel, val); \ 7898 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7899 } while (0) 7900 7901 #define TEST_INVALID_SEG_SEL(sel, val) \ 7902 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7903 7904 #define TEST_VALID_SEG_SEL(sel, val) \ 7905 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7906 7907 /* 7908 * The following checks are done on the Selector field of the Guest Segment 7909 * Registers: 7910 * - TR. The TI flag (bit 2) must be 0. 7911 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7912 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7913 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7914 * the RPL of the selector field for CS. 7915 * 7916 * [Intel SDM] 7917 */ 7918 static void test_guest_segment_sel_fields(void) 7919 { 7920 u16 sel_saved; 7921 u32 ar_saved; 7922 u32 cpu_ctrl0_saved; 7923 u32 cpu_ctrl1_saved; 7924 u16 cs_rpl_bits; 7925 7926 /* 7927 * Test for GUEST_SEL_TR 7928 */ 7929 sel_saved = vmcs_read(GUEST_SEL_TR); 7930 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7931 vmcs_write(GUEST_SEL_TR, sel_saved); 7932 7933 /* 7934 * Test for GUEST_SEL_LDTR 7935 */ 7936 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7937 ar_saved = vmcs_read(GUEST_AR_LDTR); 7938 /* LDTR is set unusable */ 7939 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7940 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7941 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7942 /* LDTR is set usable */ 7943 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7944 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7945 7946 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7947 7948 vmcs_write(GUEST_AR_LDTR, ar_saved); 7949 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7950 7951 /* 7952 * Test for GUEST_SEL_SS 7953 */ 7954 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7955 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7956 ar_saved = vmcs_read(GUEST_AR_SS); 7957 /* Turn off "unrestricted guest" vm-execution control */ 7958 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7959 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7960 sel_saved = vmcs_read(GUEST_SEL_SS); 7961 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7962 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7963 /* Make SS usable if it's unusable or vice-versa */ 7964 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7965 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7966 else 7967 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7968 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7969 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7970 7971 /* Need a valid EPTP as the passing case fully enters the guest. */ 7972 if (enable_unrestricted_guest(true)) 7973 goto skip_ss_tests; 7974 7975 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7976 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7977 7978 /* Make SS usable if it's unusable or vice-versa */ 7979 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7980 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7981 else 7982 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7983 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7984 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7985 skip_ss_tests: 7986 7987 vmcs_write(GUEST_AR_SS, ar_saved); 7988 vmcs_write(GUEST_SEL_SS, sel_saved); 7989 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7990 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7991 } 7992 7993 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7994 do { \ 7995 addr_saved = vmcs_read(seg_base); \ 7996 for (i = 32; i < 63; i = i + 4) { \ 7997 addr = addr_saved | 1ull << i; \ 7998 vmcs_write(seg_base, addr); \ 7999 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 8000 xfail, addr, xstr(seg_base)); \ 8001 } \ 8002 vmcs_write(seg_base, addr_saved); \ 8003 } while (0) 8004 8005 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 8006 do { \ 8007 addr_saved = vmcs_read(seg_base); \ 8008 vmcs_write(seg_base, NONCANONICAL); \ 8009 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 8010 xfail, NONCANONICAL, xstr(seg_base)); \ 8011 vmcs_write(seg_base, addr_saved); \ 8012 } while (0) 8013 8014 /* 8015 * The following checks are done on the Base Address field of the Guest 8016 * Segment Registers on processors that support Intel 64 architecture: 8017 * - TR, FS, GS : The address must be canonical. 8018 * - LDTR : If LDTR is usable, the address must be canonical. 8019 * - CS : Bits 63:32 of the address must be zero. 8020 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 8021 * must be zero. 8022 * 8023 * [Intel SDM] 8024 */ 8025 static void test_guest_segment_base_addr_fields(void) 8026 { 8027 u64 addr_saved; 8028 u64 addr; 8029 u32 ar_saved; 8030 int i; 8031 8032 /* 8033 * The address of TR, FS, GS and LDTR must be canonical. 8034 */ 8035 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8036 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8037 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8038 ar_saved = vmcs_read(GUEST_AR_LDTR); 8039 /* Make LDTR unusable */ 8040 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8041 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8042 /* Make LDTR usable */ 8043 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8044 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8045 8046 vmcs_write(GUEST_AR_LDTR, ar_saved); 8047 8048 /* 8049 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8050 */ 8051 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8052 ar_saved = vmcs_read(GUEST_AR_SS); 8053 /* Make SS unusable */ 8054 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8055 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8056 /* Make SS usable */ 8057 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8058 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8059 vmcs_write(GUEST_AR_SS, ar_saved); 8060 8061 ar_saved = vmcs_read(GUEST_AR_DS); 8062 /* Make DS unusable */ 8063 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8064 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8065 /* Make DS usable */ 8066 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8067 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8068 vmcs_write(GUEST_AR_DS, ar_saved); 8069 8070 ar_saved = vmcs_read(GUEST_AR_ES); 8071 /* Make ES unusable */ 8072 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8073 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8074 /* Make ES usable */ 8075 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8076 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8077 vmcs_write(GUEST_AR_ES, ar_saved); 8078 } 8079 8080 /* 8081 * Check that the virtual CPU checks the VMX Guest State Area as 8082 * documented in the Intel SDM. 8083 */ 8084 static void vmx_guest_state_area_test(void) 8085 { 8086 vmx_set_test_stage(1); 8087 test_set_guest(guest_state_test_main); 8088 8089 /* 8090 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8091 * must each contain a canonical address. 8092 */ 8093 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8094 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8095 8096 test_guest_dr7(); 8097 test_load_guest_pat(); 8098 test_guest_efer(); 8099 test_load_guest_perf_global_ctrl(); 8100 test_load_guest_bndcfgs(); 8101 8102 test_guest_segment_sel_fields(); 8103 test_guest_segment_base_addr_fields(); 8104 8105 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8106 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8107 8108 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8109 int i; 8110 for (i = 16; i <= 31; i++) { 8111 u32 tmp = guest_desc_limit_saved | (1ull << i); 8112 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8113 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8114 } 8115 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8116 8117 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8118 for (i = 16; i <= 31; i++) { 8119 u32 tmp = guest_desc_limit_saved | (1ull << i); 8120 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8121 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8122 } 8123 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8124 8125 /* 8126 * Let the guest finish execution 8127 */ 8128 vmx_set_test_stage(2); 8129 enter_guest(); 8130 } 8131 8132 extern void unrestricted_guest_main(void); 8133 asm (".code32\n" 8134 "unrestricted_guest_main:\n" 8135 "vmcall\n" 8136 "nop\n" 8137 "mov $1, %edi\n" 8138 "call hypercall\n" 8139 ".code64\n"); 8140 8141 static void setup_unrestricted_guest(void) 8142 { 8143 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8144 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8145 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8146 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8147 } 8148 8149 static void unsetup_unrestricted_guest(void) 8150 { 8151 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8152 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8153 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8154 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8155 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8156 } 8157 8158 /* 8159 * If "unrestricted guest" secondary VM-execution control is set, guests 8160 * can run in unpaged protected mode. 8161 */ 8162 static void vmentry_unrestricted_guest_test(void) 8163 { 8164 if (enable_unrestricted_guest(true)) { 8165 report_skip("Unrestricted guest not supported"); 8166 return; 8167 } 8168 8169 test_set_guest(unrestricted_guest_main); 8170 setup_unrestricted_guest(); 8171 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8172 8173 /* 8174 * Let the guest finish execution as a regular guest 8175 */ 8176 unsetup_unrestricted_guest(); 8177 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8178 enter_guest(); 8179 } 8180 8181 static bool valid_vmcs_for_vmentry(void) 8182 { 8183 struct vmcs *current_vmcs = NULL; 8184 8185 if (vmcs_save(¤t_vmcs)) 8186 return false; 8187 8188 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8189 } 8190 8191 static void try_vmentry_in_movss_shadow(void) 8192 { 8193 u32 vm_inst_err; 8194 u32 flags; 8195 bool early_failure = false; 8196 u32 expected_flags = X86_EFLAGS_FIXED; 8197 bool valid_vmcs = valid_vmcs_for_vmentry(); 8198 8199 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8200 8201 /* 8202 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8203 * unsupported VMCS component"). 8204 */ 8205 vmcs_write(~0u, 0); 8206 8207 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8208 "vmwrite %%rsp, %%rdx;" 8209 "mov 0f, %%rax;" 8210 "mov %[host_rip], %%edx;" 8211 "vmwrite %%rax, %%rdx;" 8212 "mov $-1, %%ah;" 8213 "sahf;" 8214 "mov %%ss, %%ax;" 8215 "mov %%ax, %%ss;" 8216 "vmlaunch;" 8217 "mov $1, %[early_failure];" 8218 "0: lahf;" 8219 "movzbl %%ah, %[flags]" 8220 : [early_failure] "+r" (early_failure), 8221 [flags] "=&a" (flags) 8222 : [host_rsp] "i" (HOST_RSP), 8223 [host_rip] "i" (HOST_RIP) 8224 : "rdx", "cc", "memory"); 8225 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8226 8227 report(early_failure, "Early VM-entry failure"); 8228 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8229 expected_flags, flags); 8230 if (valid_vmcs) 8231 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8232 "VM-instruction error is %d (actual %d)", 8233 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8234 } 8235 8236 static void vmentry_movss_shadow_test(void) 8237 { 8238 struct vmcs *orig_vmcs; 8239 8240 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8241 8242 /* 8243 * Set the launched flag on the current VMCS to verify the correct 8244 * error priority, below. 8245 */ 8246 test_set_guest(v2_null_test_guest); 8247 enter_guest(); 8248 8249 /* 8250 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8251 * fail due to invalid guest state (if we make it that far). 8252 */ 8253 vmcs_write(GUEST_RFLAGS, 0); 8254 8255 /* 8256 * "VM entry with events blocked by MOV SS" takes precedence over 8257 * "VMLAUNCH with non-clear VMCS." 8258 */ 8259 report_prefix_push("valid current-VMCS"); 8260 try_vmentry_in_movss_shadow(); 8261 report_prefix_pop(); 8262 8263 /* 8264 * VMfailInvalid takes precedence over "VM entry with events 8265 * blocked by MOV SS." 8266 */ 8267 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8268 report_prefix_push("no current-VMCS"); 8269 try_vmentry_in_movss_shadow(); 8270 report_prefix_pop(); 8271 8272 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8273 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8274 } 8275 8276 static void vmx_ldtr_test_guest(void) 8277 { 8278 u16 ldtr = sldt(); 8279 8280 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8281 NP_SEL, ldtr); 8282 } 8283 8284 /* 8285 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8286 */ 8287 static void vmx_ldtr_test(void) 8288 { 8289 const u8 ldt_ar = 0x82; /* Present LDT */ 8290 u16 sel = FIRST_SPARE_SEL; 8291 8292 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8293 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8294 lldt(sel); 8295 8296 test_set_guest(vmx_ldtr_test_guest); 8297 /* 8298 * Set up a different LDTR for L2. The actual GDT contents are 8299 * irrelevant, since we stuff the hidden descriptor state 8300 * straight into the VMCS rather than reading it from the GDT. 8301 */ 8302 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8303 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8304 enter_guest(); 8305 8306 /* 8307 * VM-exit should clear LDTR (and make it unusable, but we 8308 * won't verify that here). 8309 */ 8310 sel = sldt(); 8311 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8312 } 8313 8314 static void vmx_single_vmcall_guest(void) 8315 { 8316 vmcall(); 8317 } 8318 8319 static void vmx_cr_load_test(void) 8320 { 8321 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8322 u32 ctrls[2] = {0}; 8323 pgd_t *pml5; 8324 8325 orig_cr4 = read_cr4(); 8326 orig_cr3 = read_cr3(); 8327 8328 if (!this_cpu_has(X86_FEATURE_PCID)) { 8329 report_skip("PCID not detected"); 8330 return; 8331 } 8332 if (!this_cpu_has(X86_FEATURE_MCE)) { 8333 report_skip("MCE not detected"); 8334 return; 8335 } 8336 8337 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8338 8339 /* Enable PCID for L1. */ 8340 cr4 = orig_cr4 | X86_CR4_PCIDE; 8341 cr3 = orig_cr3 | 0x1; 8342 TEST_ASSERT(!write_cr4_checking(cr4)); 8343 write_cr3(cr3); 8344 8345 test_set_guest(vmx_single_vmcall_guest); 8346 vmcs_write(HOST_CR4, cr4); 8347 vmcs_write(HOST_CR3, cr3); 8348 enter_guest(); 8349 8350 /* 8351 * No exception is expected. 8352 * 8353 * NB. KVM loads the last guest write to CR4 into CR4 read 8354 * shadow. In order to trigger an exit to KVM, we can toggle a 8355 * bit that is owned by KVM. We use CR4.MCE, which shall 8356 * have no side effect because normally no guest MCE (e.g., as the 8357 * result of bad memory) would happen during this test. 8358 */ 8359 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8360 8361 /* Cleanup L1 state. */ 8362 write_cr3(orig_cr3); 8363 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8364 8365 if (!this_cpu_has(X86_FEATURE_LA57)) 8366 goto done; 8367 8368 /* 8369 * Allocate a full page for PML5 to guarantee alignment, though only 8370 * the first entry needs to be filled (the test's virtual addresses 8371 * most definitely do not have any of bits 56:48 set). 8372 */ 8373 pml5 = alloc_page(); 8374 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8375 8376 /* 8377 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8378 * can't be toggled while long is active via MOV CR4, but there are no 8379 * such restrictions on VM-Exit. 8380 */ 8381 lol_5level: 8382 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8383 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8384 enter_guest(); 8385 8386 /* 8387 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8388 * e.g. uses the correct guest root level in gva_to_gpa(). 8389 */ 8390 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8391 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8392 8393 vmcs_write(HOST_CR4, orig_cr4); 8394 vmcs_write(HOST_CR3, orig_cr3); 8395 enter_guest(); 8396 8397 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8398 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8399 8400 /* 8401 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8402 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8403 * version shares an MMU between L1 and L2. 8404 * 8405 * If the saved execution controls are non-zero then the EPT version 8406 * has already run. In that case, restore the old controls. If EPT 8407 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8408 */ 8409 if (ctrls[0]) { 8410 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8411 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8412 } else if (!setup_ept(false)) { 8413 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8414 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8415 goto lol_5level; 8416 } 8417 8418 free_page(pml5); 8419 8420 done: 8421 skip_exit_vmcall(); 8422 enter_guest(); 8423 } 8424 8425 static void vmx_cr4_osxsave_test_guest(void) 8426 { 8427 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8428 } 8429 8430 /* 8431 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8432 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8433 * value than in L1. 8434 */ 8435 static void vmx_cr4_osxsave_test(void) 8436 { 8437 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8438 report_skip("XSAVE not detected"); 8439 return; 8440 } 8441 8442 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8443 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8444 8445 write_cr4(cr4); 8446 vmcs_write(GUEST_CR4, cr4); 8447 vmcs_write(HOST_CR4, cr4); 8448 } 8449 8450 TEST_ASSERT(cpuid_osxsave()); 8451 8452 test_set_guest(vmx_cr4_osxsave_test_guest); 8453 enter_guest(); 8454 8455 TEST_ASSERT(cpuid_osxsave()); 8456 } 8457 8458 static void vmx_nm_test_guest(void) 8459 { 8460 write_cr0(read_cr0() | X86_CR0_TS); 8461 asm volatile("fnop"); 8462 } 8463 8464 static void check_nm_exit(const char *test) 8465 { 8466 u32 reason = vmcs_read(EXI_REASON); 8467 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8468 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8469 NM_VECTOR; 8470 8471 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8472 } 8473 8474 /* 8475 * This test checks that: 8476 * 8477 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8478 * a subsequent #NM VM-exit is reflected to L1. 8479 * 8480 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8481 * subsequent #NM VM-exit is reflected to L1. 8482 */ 8483 static void vmx_nm_test(void) 8484 { 8485 unsigned long cr0 = read_cr0(); 8486 8487 test_set_guest(vmx_nm_test_guest); 8488 8489 /* 8490 * L1 wants to intercept #NM exceptions encountered in L2. 8491 */ 8492 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8493 8494 /* 8495 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8496 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8497 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8498 */ 8499 vmcs_write(CR0_MASK, 0); 8500 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8501 enter_guest(); 8502 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8503 8504 /* 8505 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8506 * CR0.EM set. The fnop will still raise #NM, and L0 should 8507 * reflect the #NM VM-exit to L1. 8508 */ 8509 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8510 enter_guest(); 8511 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8512 8513 /* 8514 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8515 * CR0.EM clear. There will be no #NM, and the L2 guest should 8516 * exit normally. 8517 */ 8518 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8519 enter_guest(); 8520 } 8521 8522 bool vmx_pending_event_ipi_fired; 8523 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8524 { 8525 vmx_pending_event_ipi_fired = true; 8526 eoi(); 8527 } 8528 8529 bool vmx_pending_event_guest_run; 8530 static void vmx_pending_event_guest(void) 8531 { 8532 vmcall(); 8533 vmx_pending_event_guest_run = true; 8534 } 8535 8536 static void vmx_pending_event_test_core(bool guest_hlt) 8537 { 8538 int ipi_vector = 0xf1; 8539 8540 vmx_pending_event_ipi_fired = false; 8541 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8542 8543 vmx_pending_event_guest_run = false; 8544 test_set_guest(vmx_pending_event_guest); 8545 8546 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8547 8548 enter_guest(); 8549 skip_exit_vmcall(); 8550 8551 if (guest_hlt) 8552 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8553 8554 irq_disable(); 8555 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8556 APIC_DM_FIXED | ipi_vector, 8557 0); 8558 8559 enter_guest(); 8560 8561 assert_exit_reason(VMX_EXTINT); 8562 report(!vmx_pending_event_guest_run, 8563 "Guest did not run before host received IPI"); 8564 8565 irq_enable(); 8566 asm volatile ("nop"); 8567 irq_disable(); 8568 report(vmx_pending_event_ipi_fired, 8569 "Got pending interrupt after IRQ enabled"); 8570 8571 if (guest_hlt) 8572 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8573 8574 enter_guest(); 8575 report(vmx_pending_event_guest_run, 8576 "Guest finished running when no interrupt"); 8577 } 8578 8579 static void vmx_pending_event_test(void) 8580 { 8581 vmx_pending_event_test_core(false); 8582 } 8583 8584 static void vmx_pending_event_hlt_test(void) 8585 { 8586 vmx_pending_event_test_core(true); 8587 } 8588 8589 static int vmx_window_test_db_count; 8590 8591 static void vmx_window_test_db_handler(struct ex_regs *regs) 8592 { 8593 vmx_window_test_db_count++; 8594 } 8595 8596 static void vmx_nmi_window_test_guest(void) 8597 { 8598 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8599 8600 asm volatile("vmcall\n\t" 8601 "nop\n\t"); 8602 8603 handle_exception(DB_VECTOR, NULL); 8604 } 8605 8606 static void verify_nmi_window_exit(u64 rip) 8607 { 8608 u32 exit_reason = vmcs_read(EXI_REASON); 8609 8610 report(exit_reason == VMX_NMI_WINDOW, 8611 "Exit reason (%d) is 'NMI window'", exit_reason); 8612 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8613 vmcs_read(GUEST_RIP), rip); 8614 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8615 } 8616 8617 static void vmx_nmi_window_test(void) 8618 { 8619 u64 nop_addr; 8620 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8621 8622 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8623 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8624 return; 8625 } 8626 8627 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8628 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8629 return; 8630 } 8631 8632 vmx_window_test_db_count = 0; 8633 8634 report_prefix_push("NMI-window"); 8635 test_set_guest(vmx_nmi_window_test_guest); 8636 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8637 enter_guest(); 8638 skip_exit_vmcall(); 8639 nop_addr = vmcs_read(GUEST_RIP); 8640 8641 /* 8642 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8643 * RIP will not advance. 8644 */ 8645 report_prefix_push("active, no blocking"); 8646 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8647 enter_guest(); 8648 verify_nmi_window_exit(nop_addr); 8649 report_prefix_pop(); 8650 8651 /* 8652 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8653 * a VM-exit on the next instruction after the nop. (The nop 8654 * is one byte.) 8655 */ 8656 report_prefix_push("active, blocking by MOV-SS"); 8657 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8658 enter_guest(); 8659 verify_nmi_window_exit(nop_addr + 1); 8660 report_prefix_pop(); 8661 8662 /* 8663 * Ask for "NMI-window exiting" (with event injection), and 8664 * expect a VM-exit after the event is injected. (RIP should 8665 * be at the address specified in the IDT entry for #DB.) 8666 */ 8667 report_prefix_push("active, no blocking, injecting #DB"); 8668 vmcs_write(ENT_INTR_INFO, 8669 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8670 enter_guest(); 8671 verify_nmi_window_exit((u64)db_fault_addr); 8672 report_prefix_pop(); 8673 8674 /* 8675 * Ask for "NMI-window exiting" with NMI blocking, and expect 8676 * a VM-exit after the next IRET (i.e. after the #DB handler 8677 * returns). So, RIP should be back at one byte past the nop. 8678 */ 8679 report_prefix_push("active, blocking by NMI"); 8680 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8681 enter_guest(); 8682 verify_nmi_window_exit(nop_addr + 1); 8683 report(vmx_window_test_db_count == 1, 8684 "#DB handler executed once (actual %d times)", 8685 vmx_window_test_db_count); 8686 report_prefix_pop(); 8687 8688 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8689 report_skip("CPU does not support activity state HLT."); 8690 } else { 8691 /* 8692 * Ask for "NMI-window exiting" when entering activity 8693 * state HLT, and expect an immediate VM-exit. RIP is 8694 * still one byte past the nop. 8695 */ 8696 report_prefix_push("halted, no blocking"); 8697 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8698 enter_guest(); 8699 verify_nmi_window_exit(nop_addr + 1); 8700 report_prefix_pop(); 8701 8702 /* 8703 * Ask for "NMI-window exiting" when entering activity 8704 * state HLT (with event injection), and expect a 8705 * VM-exit after the event is injected. (RIP should be 8706 * at the address specified in the IDT entry for #DB.) 8707 */ 8708 report_prefix_push("halted, no blocking, injecting #DB"); 8709 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8710 vmcs_write(ENT_INTR_INFO, 8711 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8712 DB_VECTOR); 8713 enter_guest(); 8714 verify_nmi_window_exit((u64)db_fault_addr); 8715 report_prefix_pop(); 8716 } 8717 8718 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8719 enter_guest(); 8720 report_prefix_pop(); 8721 } 8722 8723 static void vmx_intr_window_test_guest(void) 8724 { 8725 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8726 8727 /* 8728 * The two consecutive STIs are to ensure that only the first 8729 * one has a shadow. Note that NOP and STI are one byte 8730 * instructions. 8731 */ 8732 asm volatile("vmcall\n\t" 8733 "nop\n\t" 8734 "sti\n\t" 8735 "sti\n\t"); 8736 8737 handle_exception(DB_VECTOR, NULL); 8738 } 8739 8740 static void verify_intr_window_exit(u64 rip) 8741 { 8742 u32 exit_reason = vmcs_read(EXI_REASON); 8743 8744 report(exit_reason == VMX_INTR_WINDOW, 8745 "Exit reason (%d) is 'interrupt window'", exit_reason); 8746 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8747 vmcs_read(GUEST_RIP), rip); 8748 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8749 } 8750 8751 static void vmx_intr_window_test(void) 8752 { 8753 u64 vmcall_addr; 8754 u64 nop_addr; 8755 unsigned int orig_db_gate_type; 8756 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8757 8758 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8759 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8760 return; 8761 } 8762 8763 /* 8764 * Change the IDT entry for #DB from interrupt gate to trap gate, 8765 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8766 * be disabled after vectoring a #DB. 8767 */ 8768 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8769 boot_idt[DB_VECTOR].type = 15; 8770 8771 report_prefix_push("interrupt-window"); 8772 test_set_guest(vmx_intr_window_test_guest); 8773 enter_guest(); 8774 assert_exit_reason(VMX_VMCALL); 8775 vmcall_addr = vmcs_read(GUEST_RIP); 8776 8777 /* 8778 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8779 * no blocking; expect an immediate VM-exit. Note that we have 8780 * not advanced past the vmcall instruction yet, so RIP should 8781 * point to the vmcall instruction. 8782 */ 8783 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8784 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8785 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8786 enter_guest(); 8787 verify_intr_window_exit(vmcall_addr); 8788 report_prefix_pop(); 8789 8790 /* 8791 * Ask for "interrupt-window exiting" (with event injection) 8792 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8793 * the event is injected. That is, RIP should should be at the 8794 * address specified in the IDT entry for #DB. 8795 */ 8796 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8797 vmcs_write(ENT_INTR_INFO, 8798 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8799 vmcall_addr = vmcs_read(GUEST_RIP); 8800 enter_guest(); 8801 verify_intr_window_exit((u64)db_fault_addr); 8802 report_prefix_pop(); 8803 8804 /* 8805 * Let the L2 guest run through the IRET, back to the VMCALL. 8806 * We have to clear the "interrupt-window exiting" 8807 * VM-execution control, or it would just keep causing 8808 * VM-exits. Then, advance past the VMCALL and set the 8809 * "interrupt-window exiting" VM-execution control again. 8810 */ 8811 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8812 enter_guest(); 8813 skip_exit_vmcall(); 8814 nop_addr = vmcs_read(GUEST_RIP); 8815 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8816 8817 /* 8818 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8819 * RFLAGS.IF set, and expect a VM-exit on the next 8820 * instruction. (NOP is one byte.) 8821 */ 8822 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8823 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8824 enter_guest(); 8825 verify_intr_window_exit(nop_addr + 1); 8826 report_prefix_pop(); 8827 8828 /* 8829 * Back up to the NOP and ask for "interrupt-window exiting" 8830 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8831 * on the next instruction. (NOP is one byte.) 8832 */ 8833 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8834 vmcs_write(GUEST_RIP, nop_addr); 8835 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8836 enter_guest(); 8837 verify_intr_window_exit(nop_addr + 1); 8838 report_prefix_pop(); 8839 8840 /* 8841 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8842 * and expect a VM-exit on the instruction following the STI 8843 * shadow. Only the first STI (which is one byte past the NOP) 8844 * should have a shadow. The second STI (which is two bytes 8845 * past the NOP) has no shadow. Therefore, the interrupt 8846 * window opens at three bytes past the NOP. 8847 */ 8848 report_prefix_push("active, RFLAGS.IF = 0"); 8849 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8850 enter_guest(); 8851 verify_intr_window_exit(nop_addr + 3); 8852 report_prefix_pop(); 8853 8854 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8855 report_skip("CPU does not support activity state HLT."); 8856 } else { 8857 /* 8858 * Ask for "interrupt-window exiting" when entering 8859 * activity state HLT, and expect an immediate 8860 * VM-exit. RIP is still three bytes past the nop. 8861 */ 8862 report_prefix_push("halted, no blocking"); 8863 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8864 enter_guest(); 8865 verify_intr_window_exit(nop_addr + 3); 8866 report_prefix_pop(); 8867 8868 /* 8869 * Ask for "interrupt-window exiting" when entering 8870 * activity state HLT (with event injection), and 8871 * expect a VM-exit after the event is injected. That 8872 * is, RIP should should be at the address specified 8873 * in the IDT entry for #DB. 8874 */ 8875 report_prefix_push("halted, no blocking, injecting #DB"); 8876 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8877 vmcs_write(ENT_INTR_INFO, 8878 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8879 DB_VECTOR); 8880 enter_guest(); 8881 verify_intr_window_exit((u64)db_fault_addr); 8882 report_prefix_pop(); 8883 } 8884 8885 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8886 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8887 enter_guest(); 8888 report_prefix_pop(); 8889 } 8890 8891 #define GUEST_TSC_OFFSET (1u << 30) 8892 8893 static u64 guest_tsc; 8894 8895 static void vmx_store_tsc_test_guest(void) 8896 { 8897 guest_tsc = rdtsc(); 8898 } 8899 8900 /* 8901 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8902 * list, the value saved is not subject to the TSC offset that is 8903 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8904 */ 8905 static void vmx_store_tsc_test(void) 8906 { 8907 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8908 u64 low, high; 8909 8910 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8911 report_skip("'Use TSC offsetting' not supported"); 8912 return; 8913 } 8914 8915 test_set_guest(vmx_store_tsc_test_guest); 8916 8917 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8918 vmcs_write(EXI_MSR_ST_CNT, 1); 8919 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8920 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8921 8922 low = rdtsc(); 8923 enter_guest(); 8924 high = rdtsc(); 8925 8926 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8927 guest_tsc <= high + GUEST_TSC_OFFSET, 8928 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8929 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8930 report(low <= msr_entry.value && msr_entry.value <= high, 8931 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8932 msr_entry.value, low, high); 8933 } 8934 8935 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8936 { 8937 } 8938 8939 static void vmx_preemption_timer_zero_test_guest(void) 8940 { 8941 while (vmx_get_test_stage() < 3) 8942 vmcall(); 8943 } 8944 8945 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8946 { 8947 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8948 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8949 } 8950 8951 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8952 { 8953 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8954 enter_guest(); 8955 skip_exit_vmcall(); 8956 } 8957 8958 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8959 { 8960 vmx_preemption_timer_zero_activate_preemption_timer(); 8961 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8962 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8963 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8964 enter_guest(); 8965 } 8966 8967 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8968 { 8969 vmx_preemption_timer_zero_activate_preemption_timer(); 8970 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8971 vmcs_write(EXC_BITMAP, exception_bitmap); 8972 enter_guest(); 8973 } 8974 8975 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8976 { 8977 u32 reason = (u32)vmcs_read(EXI_REASON); 8978 u64 guest_rip = vmcs_read(GUEST_RIP); 8979 8980 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8981 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8982 reason, VMX_PREEMPT, guest_rip, expected_rip); 8983 } 8984 8985 /* 8986 * This test ensures that when the VMX preemption timer is zero at 8987 * VM-entry, a VM-exit occurs after any event injection and after any 8988 * pending debug exceptions are raised, but before execution of any 8989 * guest instructions. 8990 */ 8991 static void vmx_preemption_timer_zero_test(void) 8992 { 8993 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8994 handler old_db; 8995 u32 reason; 8996 8997 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 8998 report_skip("'Activate VMX-preemption timer' not supported"); 8999 return; 9000 } 9001 9002 /* 9003 * Install a custom #DB handler that doesn't abort. 9004 */ 9005 old_db = handle_exception(DB_VECTOR, 9006 vmx_preemption_timer_zero_test_db_handler); 9007 9008 test_set_guest(vmx_preemption_timer_zero_test_guest); 9009 9010 /* 9011 * VMX-preemption timer should fire after event injection. 9012 */ 9013 vmx_set_test_stage(0); 9014 vmx_preemption_timer_zero_inject_db(0); 9015 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9016 vmx_preemption_timer_zero_advance_past_vmcall(); 9017 9018 /* 9019 * VMX-preemption timer should fire after event injection. 9020 * Exception bitmap is irrelevant, since you can't intercept 9021 * an event that you injected. 9022 */ 9023 vmx_set_test_stage(1); 9024 vmx_preemption_timer_zero_inject_db(true); 9025 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9026 vmx_preemption_timer_zero_advance_past_vmcall(); 9027 9028 /* 9029 * VMX-preemption timer should fire after pending debug exceptions 9030 * have delivered a #DB trap. 9031 */ 9032 vmx_set_test_stage(2); 9033 vmx_preemption_timer_zero_set_pending_dbg(0); 9034 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9035 vmx_preemption_timer_zero_advance_past_vmcall(); 9036 9037 /* 9038 * VMX-preemption timer would fire after pending debug exceptions 9039 * have delivered a #DB trap, but in this case, the #DB trap is 9040 * intercepted. 9041 */ 9042 vmx_set_test_stage(3); 9043 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9044 reason = (u32)vmcs_read(EXI_REASON); 9045 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9046 reason, VMX_EXC_NMI); 9047 9048 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9049 enter_guest(); 9050 9051 handle_exception(DB_VECTOR, old_db); 9052 } 9053 9054 static u64 vmx_preemption_timer_tf_test_prev_rip; 9055 9056 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9057 { 9058 extern char vmx_preemption_timer_tf_test_endloop; 9059 9060 if (vmx_get_test_stage() == 2) { 9061 /* 9062 * Stage 2 means that we're done, one way or another. 9063 * Arrange for the iret to drop us out of the wbinvd 9064 * loop and stop single-stepping. 9065 */ 9066 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9067 regs->rflags &= ~X86_EFLAGS_TF; 9068 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9069 /* 9070 * The RIP should alternate between the wbinvd and the 9071 * jmp instruction in the code below. If we ever see 9072 * the same instruction twice in a row, that means a 9073 * single-step trap has been dropped. Let the 9074 * hypervisor know about the failure by executing a 9075 * VMCALL. 9076 */ 9077 vmcall(); 9078 } 9079 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9080 } 9081 9082 static void vmx_preemption_timer_tf_test_guest(void) 9083 { 9084 /* 9085 * The hypervisor doesn't intercept WBINVD, so the loop below 9086 * shouldn't be a problem--it's just two instructions 9087 * executing in VMX non-root mode. However, when the 9088 * hypervisor is running in a virtual environment, the parent 9089 * hypervisor might intercept WBINVD and emulate it. If the 9090 * parent hypervisor is broken, the single-step trap after the 9091 * WBINVD might be lost. 9092 */ 9093 asm volatile("vmcall\n\t" 9094 "0: wbinvd\n\t" 9095 "1: jmp 0b\n\t" 9096 "vmx_preemption_timer_tf_test_endloop:"); 9097 } 9098 9099 /* 9100 * Ensure that the delivery of a "VMX-preemption timer expired" 9101 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9102 * passing this test doesn't ensure correctness, because the test will 9103 * only fail if the VMX-preemtion timer fires at the right time (or 9104 * the wrong time, as it were). 9105 */ 9106 static void vmx_preemption_timer_tf_test(void) 9107 { 9108 handler old_db; 9109 u32 reason; 9110 int i; 9111 9112 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9113 report_skip("'Activate VMX-preemption timer' not supported"); 9114 return; 9115 } 9116 9117 old_db = handle_exception(DB_VECTOR, 9118 vmx_preemption_timer_tf_test_db_handler); 9119 9120 test_set_guest(vmx_preemption_timer_tf_test_guest); 9121 9122 enter_guest(); 9123 skip_exit_vmcall(); 9124 9125 vmx_set_test_stage(1); 9126 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9127 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9128 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9129 9130 /* 9131 * The only exit we should see is "VMX-preemption timer 9132 * expired." If we get a VMCALL exit, that means the #DB 9133 * handler has detected a missing single-step trap. It doesn't 9134 * matter where the guest RIP is when the VMX-preemption timer 9135 * expires (whether it's in the WBINVD loop or in the #DB 9136 * handler)--a single-step trap should never be discarded. 9137 */ 9138 for (i = 0; i < 10000; i++) { 9139 enter_guest(); 9140 reason = (u32)vmcs_read(EXI_REASON); 9141 if (reason == VMX_PREEMPT) 9142 continue; 9143 TEST_ASSERT(reason == VMX_VMCALL); 9144 skip_exit_insn(); 9145 break; 9146 } 9147 9148 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9149 9150 vmx_set_test_stage(2); 9151 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9152 enter_guest(); 9153 9154 handle_exception(DB_VECTOR, old_db); 9155 } 9156 9157 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9158 9159 static u64 vmx_preemption_timer_expiry_start; 9160 static u64 vmx_preemption_timer_expiry_finish; 9161 9162 static void vmx_preemption_timer_expiry_test_guest(void) 9163 { 9164 vmcall(); 9165 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9166 9167 while (vmx_get_test_stage() == 0) 9168 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9169 } 9170 9171 /* 9172 * Test that the VMX-preemption timer is not excessively delayed. 9173 * 9174 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9175 * with the unsigned value in the VMX-preemption timer-value field, 9176 * and the VMX-preemption timer counts down by 1 every time bit X in 9177 * the TSC changes due to a TSC increment (where X is 9178 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9179 * other than the wait-for-SIPI state, the logical processor 9180 * transitions to the C0 C-state and causes a VM-exit. 9181 * 9182 * The guest code above reads the starting TSC after VM-entry. At this 9183 * point, the VMX-preemption timer has already been activated. Next, 9184 * the guest code reads the current TSC in a loop, storing the value 9185 * read to memory. 9186 * 9187 * If the RDTSC in the loop reads a value past the VMX-preemption 9188 * timer deadline, then the VMX-preemption timer VM-exit must be 9189 * delivered before the next instruction retires. Even if a higher 9190 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9191 * must be delivered before the next instruction retires. Hence, a TSC 9192 * value past the VMX-preemption timer deadline might be read, but it 9193 * cannot be stored. If a TSC value past the deadline *is* stored, 9194 * then the architectural specification has been violated. 9195 */ 9196 static void vmx_preemption_timer_expiry_test(void) 9197 { 9198 u32 preemption_timer_value; 9199 union vmx_misc misc; 9200 u64 tsc_deadline; 9201 u32 reason; 9202 9203 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9204 report_skip("'Activate VMX-preemption timer' not supported"); 9205 return; 9206 } 9207 9208 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9209 9210 enter_guest(); 9211 skip_exit_vmcall(); 9212 9213 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9214 preemption_timer_value = 9215 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9216 9217 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9218 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9219 vmx_set_test_stage(0); 9220 9221 enter_guest(); 9222 reason = (u32)vmcs_read(EXI_REASON); 9223 TEST_ASSERT(reason == VMX_PREEMPT); 9224 9225 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9226 vmx_set_test_stage(1); 9227 enter_guest(); 9228 9229 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9230 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9231 9232 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9233 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9234 vmx_preemption_timer_expiry_finish, tsc_deadline); 9235 } 9236 9237 static void vmx_db_test_guest(void) 9238 { 9239 /* 9240 * For a hardware generated single-step #DB. 9241 */ 9242 asm volatile("vmcall;" 9243 "nop;" 9244 ".Lpost_nop:"); 9245 /* 9246 * ...in a MOVSS shadow, with pending debug exceptions. 9247 */ 9248 asm volatile("vmcall;" 9249 "nop;" 9250 ".Lpost_movss_nop:"); 9251 /* 9252 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9253 * emulates it in software.) 9254 */ 9255 asm volatile("vmcall;" 9256 "wbinvd;" 9257 ".Lpost_wbinvd:"); 9258 /* 9259 * ...in a MOVSS shadow, with pending debug exceptions. 9260 */ 9261 asm volatile("vmcall;" 9262 "wbinvd;" 9263 ".Lpost_movss_wbinvd:"); 9264 /* 9265 * For a hardware generated single-step #DB in a transactional region. 9266 */ 9267 asm volatile("vmcall;" 9268 ".Lxbegin: xbegin .Lskip_rtm;" 9269 "xend;" 9270 ".Lskip_rtm:"); 9271 } 9272 9273 /* 9274 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9275 * L2. No #DB is delivered and L2 continues to the next point of 9276 * interest. 9277 */ 9278 static void dismiss_db(void) 9279 { 9280 vmcs_write(GUEST_PENDING_DEBUG, 0); 9281 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9282 enter_guest(); 9283 } 9284 9285 /* 9286 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9287 * Then throw away the #DB exception and resume L2. 9288 */ 9289 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9290 void *expected_rip, u64 expected_exit_qual, 9291 u64 expected_dr6) 9292 { 9293 u32 reason = vmcs_read(EXI_REASON); 9294 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9295 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9296 u64 guest_rip = vmcs_read(GUEST_RIP); 9297 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9298 u64 dr6 = read_dr6(); 9299 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9300 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9301 9302 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9303 "Expected #DB VM-exit"); 9304 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9305 expected_rip, guest_rip); 9306 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9307 "Expected pending debug exceptions 0 (actual %lx)", 9308 guest_pending_dbg); 9309 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9310 "Expected exit qualification %lx (actual %lx)", 9311 expected_exit_qual, exit_qual); 9312 report_xfail(xfail_dr6, expected_dr6 == dr6, 9313 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9314 dismiss_db(); 9315 } 9316 9317 /* 9318 * Assuming the guest has just exited on a VMCALL instruction, skip 9319 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9320 * pending debug exceptions are non-zero, set the VMCS up as if the 9321 * previous instruction was a MOVSS that generated the indicated 9322 * pending debug exceptions. Then enter L2. 9323 */ 9324 static void single_step_guest(const char *test_name, u64 starting_dr6, 9325 u64 pending_debug_exceptions) 9326 { 9327 printf("\n%s\n", test_name); 9328 skip_exit_vmcall(); 9329 write_dr6(starting_dr6); 9330 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9331 if (pending_debug_exceptions) { 9332 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9333 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9334 } 9335 enter_guest(); 9336 } 9337 9338 /* 9339 * When L1 intercepts #DB, verify that a single-step trap clears 9340 * pending debug exceptions, populates the exit qualification field 9341 * properly, and that DR6 is not prematurely clobbered. In a 9342 * (simulated) MOVSS shadow, make sure that the pending debug 9343 * exception bits are properly accumulated into the exit qualification 9344 * field. 9345 */ 9346 static void vmx_db_test(void) 9347 { 9348 /* 9349 * We are going to set a few arbitrary bits in DR6 to verify that 9350 * (a) DR6 is not modified by an intercepted #DB, and 9351 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9352 * the exit qualification field for a subsequent #DB exception. 9353 */ 9354 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9355 extern char post_nop asm(".Lpost_nop"); 9356 extern char post_movss_nop asm(".Lpost_movss_nop"); 9357 extern char post_wbinvd asm(".Lpost_wbinvd"); 9358 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9359 extern char xbegin asm(".Lxbegin"); 9360 extern char skip_rtm asm(".Lskip_rtm"); 9361 9362 /* 9363 * L1 wants to intercept #DB exceptions encountered in L2. 9364 */ 9365 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9366 9367 /* 9368 * Start L2 and run it up to the first point of interest. 9369 */ 9370 test_set_guest(vmx_db_test_guest); 9371 enter_guest(); 9372 9373 /* 9374 * Hardware-delivered #DB trap for single-step sets the 9375 * standard that L0 has to follow for emulated instructions. 9376 */ 9377 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9378 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9379 9380 /* 9381 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9382 * also sets the standard that L0 has to follow for emulated 9383 * instructions. Here, we establish the VMCS pending debug 9384 * exceptions to indicate that the simulated MOVSS triggered a 9385 * data breakpoint as well as the single-step trap. 9386 */ 9387 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9388 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9389 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9390 starting_dr6); 9391 9392 /* 9393 * L0 synthesized #DB trap for single-step is buggy, because 9394 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9395 * reconstitute the exit qualification from the prematurely 9396 * modified DR6, but fails miserably. 9397 */ 9398 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9399 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9400 9401 /* 9402 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9403 * even worse, because L0 also leaves the pending debug 9404 * exceptions in the VMCS instead of accumulating them into 9405 * the exit qualification field for the #DB exception. 9406 */ 9407 single_step_guest("Software synthesized single-step in MOVSS shadow", 9408 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9409 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9410 starting_dr6); 9411 9412 /* 9413 * Optional RTM test for hardware that supports RTM, to 9414 * demonstrate that the current volume 3 of the SDM 9415 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9416 * qualification for debug exceptions is not reserved. It is 9417 * set to 1 if a debug exception (#DB) or a breakpoint 9418 * exception (#BP) occurs inside an RTM region while advanced 9419 * debugging of RTM transactional regions is enabled. 9420 */ 9421 if (this_cpu_has(X86_FEATURE_RTM)) { 9422 vmcs_write(ENT_CONTROLS, 9423 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9424 /* 9425 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9426 * in the guest to enable advanced debugging of RTM 9427 * transactional regions. 9428 */ 9429 vmcs_write(GUEST_DR7, BIT(11)); 9430 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9431 single_step_guest("Hardware delivered single-step in " 9432 "transactional region", starting_dr6, 0); 9433 check_db_exit(false, false, false, &xbegin, BIT(16), 9434 starting_dr6); 9435 } else { 9436 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9437 enter_guest(); 9438 } 9439 } 9440 9441 static void enable_vid(void) 9442 { 9443 void *virtual_apic_page; 9444 9445 assert(cpu_has_apicv()); 9446 9447 disable_intercept_for_x2apic_msrs(); 9448 9449 virtual_apic_page = alloc_page(); 9450 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9451 9452 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9453 9454 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9455 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9456 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9457 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9458 9459 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9460 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9461 } 9462 9463 static void trigger_ioapic_scan_thread(void *data) 9464 { 9465 /* Wait until other CPU entered L2 */ 9466 while (vmx_get_test_stage() != 1) 9467 ; 9468 9469 /* Trigger ioapic scan */ 9470 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9471 vmx_set_test_stage(2); 9472 } 9473 9474 static void irq_79_handler_guest(isr_regs_t *regs) 9475 { 9476 eoi(); 9477 9478 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9479 vmcall(); 9480 } 9481 9482 /* 9483 * Constant for num of busy-loop iterations after which 9484 * a timer interrupt should have happened in host 9485 */ 9486 #define TIMER_INTERRUPT_DELAY 100000000 9487 9488 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9489 { 9490 handle_irq(0x79, irq_79_handler_guest); 9491 irq_enable(); 9492 9493 /* Signal to L1 CPU to trigger ioapic scan */ 9494 vmx_set_test_stage(1); 9495 /* Wait until L1 CPU to trigger ioapic scan */ 9496 while (vmx_get_test_stage() != 2) 9497 ; 9498 9499 /* 9500 * Wait for L0 timer interrupt to be raised while we run in L2 9501 * such that L0 will process the IOAPIC scan request before 9502 * resuming L2 9503 */ 9504 delay(TIMER_INTERRUPT_DELAY); 9505 9506 asm volatile ("int $0x79"); 9507 } 9508 9509 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9510 { 9511 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9512 report_skip(__func__); 9513 return; 9514 } 9515 9516 enable_vid(); 9517 9518 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9519 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9520 9521 /* 9522 * Launch L2. 9523 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9524 * In case the reason isn't VMX_VMCALL, the asserion inside 9525 * skip_exit_vmcall() will fail. 9526 */ 9527 enter_guest(); 9528 skip_exit_vmcall(); 9529 9530 /* Let L2 finish */ 9531 enter_guest(); 9532 report_pass(__func__); 9533 } 9534 9535 #define HLT_WITH_RVI_VECTOR (0xf1) 9536 9537 bool vmx_hlt_with_rvi_guest_isr_fired; 9538 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9539 { 9540 vmx_hlt_with_rvi_guest_isr_fired = true; 9541 eoi(); 9542 } 9543 9544 static void vmx_hlt_with_rvi_guest(void) 9545 { 9546 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9547 9548 irq_enable(); 9549 asm volatile ("nop"); 9550 9551 vmcall(); 9552 } 9553 9554 static void vmx_hlt_with_rvi_test(void) 9555 { 9556 if (!cpu_has_apicv()) { 9557 report_skip(__func__); 9558 return; 9559 } 9560 9561 enable_vid(); 9562 9563 vmx_hlt_with_rvi_guest_isr_fired = false; 9564 test_set_guest(vmx_hlt_with_rvi_guest); 9565 9566 enter_guest(); 9567 skip_exit_vmcall(); 9568 9569 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9570 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9571 enter_guest(); 9572 9573 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9574 } 9575 9576 static void set_irq_line_thread(void *data) 9577 { 9578 /* Wait until other CPU entered L2 */ 9579 while (vmx_get_test_stage() != 1) 9580 ; 9581 9582 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9583 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9584 vmx_set_test_stage(2); 9585 } 9586 9587 static bool irq_78_handler_vmcall_before_eoi; 9588 static void irq_78_handler_guest(isr_regs_t *regs) 9589 { 9590 set_irq_line(0xf, 0); 9591 if (irq_78_handler_vmcall_before_eoi) 9592 vmcall(); 9593 eoi(); 9594 vmcall(); 9595 } 9596 9597 static void vmx_apic_passthrough_guest(void) 9598 { 9599 handle_irq(0x78, irq_78_handler_guest); 9600 irq_enable(); 9601 9602 /* If requested, wait for other CPU to trigger ioapic scan */ 9603 if (vmx_get_test_stage() < 1) { 9604 vmx_set_test_stage(1); 9605 while (vmx_get_test_stage() != 2) 9606 ; 9607 } 9608 9609 set_irq_line(0xf, 1); 9610 } 9611 9612 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9613 { 9614 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9615 report_skip(__func__); 9616 return; 9617 } 9618 9619 /* Test device is required for generating IRQs */ 9620 if (!test_device_enabled()) { 9621 report_skip(__func__); 9622 return; 9623 } 9624 u64 cpu_ctrl_0 = CPU_SECONDARY; 9625 u64 cpu_ctrl_1 = 0; 9626 9627 disable_intercept_for_x2apic_msrs(); 9628 9629 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9630 9631 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9632 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9633 9634 if (set_irq_line_from_thread) { 9635 irq_78_handler_vmcall_before_eoi = false; 9636 on_cpu_async(1, set_irq_line_thread, NULL); 9637 } else { 9638 irq_78_handler_vmcall_before_eoi = true; 9639 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9640 vmx_set_test_stage(2); 9641 } 9642 test_set_guest(vmx_apic_passthrough_guest); 9643 9644 if (irq_78_handler_vmcall_before_eoi) { 9645 /* Before EOI remote_irr should still be set */ 9646 enter_guest(); 9647 skip_exit_vmcall(); 9648 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9649 "IOAPIC pass-through: remote_irr=1 before EOI"); 9650 } 9651 9652 /* After EOI remote_irr should be cleared */ 9653 enter_guest(); 9654 skip_exit_vmcall(); 9655 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9656 "IOAPIC pass-through: remote_irr=0 after EOI"); 9657 9658 /* Let L2 finish */ 9659 enter_guest(); 9660 report_pass(__func__); 9661 } 9662 9663 static void vmx_apic_passthrough_test(void) 9664 { 9665 vmx_apic_passthrough(false); 9666 } 9667 9668 static void vmx_apic_passthrough_thread_test(void) 9669 { 9670 vmx_apic_passthrough(true); 9671 } 9672 9673 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9674 { 9675 cli(); 9676 apic_set_tpr(0); 9677 } 9678 9679 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9680 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9681 { 9682 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9683 eoi(); 9684 } 9685 9686 static void vmx_apic_passthrough_tpr_threshold_test(void) 9687 { 9688 int ipi_vector = 0xe1; 9689 9690 disable_intercept_for_x2apic_msrs(); 9691 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9692 9693 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9694 cli(); 9695 apic_set_tpr((ipi_vector >> 4) + 1); 9696 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9697 APIC_DM_FIXED | ipi_vector, 9698 0); 9699 9700 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9701 enter_guest(); 9702 9703 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9704 9705 /* Clean pending self-IPI */ 9706 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9707 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9708 sti(); 9709 asm volatile ("nop"); 9710 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9711 9712 report_pass(__func__); 9713 } 9714 9715 static u64 init_signal_test_exit_reason; 9716 static bool init_signal_test_thread_continued; 9717 9718 static void init_signal_test_thread(void *data) 9719 { 9720 struct vmcs *test_vmcs = data; 9721 9722 /* Enter VMX operation (i.e. exec VMXON) */ 9723 u64 *ap_vmxon_region = alloc_page(); 9724 enable_vmx(); 9725 init_vmx(ap_vmxon_region); 9726 _vmx_on(ap_vmxon_region); 9727 9728 /* Signal CPU have entered VMX operation */ 9729 vmx_set_test_stage(1); 9730 9731 /* Wait for BSP CPU to send INIT signal */ 9732 while (vmx_get_test_stage() != 2) 9733 ; 9734 9735 /* 9736 * Signal that we continue as usual as INIT signal 9737 * should be blocked while CPU is in VMX operation 9738 */ 9739 vmx_set_test_stage(3); 9740 9741 /* Wait for signal to enter VMX non-root mode */ 9742 while (vmx_get_test_stage() != 4) 9743 ; 9744 9745 /* Enter VMX non-root mode */ 9746 test_set_guest(v2_null_test_guest); 9747 make_vmcs_current(test_vmcs); 9748 enter_guest(); 9749 /* Save exit reason for BSP CPU to compare to expected result */ 9750 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9751 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9752 vmcs_clear(test_vmcs); 9753 launched = false; 9754 /* Signal that CPU exited to VMX root mode */ 9755 vmx_set_test_stage(5); 9756 9757 /* Wait for BSP CPU to signal to exit VMX operation */ 9758 while (vmx_get_test_stage() != 6) 9759 ; 9760 9761 /* Exit VMX operation (i.e. exec VMXOFF) */ 9762 vmx_off(); 9763 9764 /* 9765 * Signal to BSP CPU that we continue as usual as INIT signal 9766 * should have been consumed by VMX_INIT exit from guest 9767 */ 9768 vmx_set_test_stage(7); 9769 9770 /* Wait for BSP CPU to signal to enter VMX operation */ 9771 while (vmx_get_test_stage() != 8) 9772 ; 9773 /* Enter VMX operation (i.e. exec VMXON) */ 9774 _vmx_on(ap_vmxon_region); 9775 /* Signal to BSP we are in VMX operation */ 9776 vmx_set_test_stage(9); 9777 9778 /* Wait for BSP CPU to send INIT signal */ 9779 while (vmx_get_test_stage() != 10) 9780 ; 9781 9782 /* Exit VMX operation (i.e. exec VMXOFF) */ 9783 vmx_off(); 9784 9785 /* 9786 * Exiting VMX operation should result in latched 9787 * INIT signal being processed. Therefore, we should 9788 * never reach the below code. Thus, signal to BSP 9789 * CPU if we have reached here so it is able to 9790 * report an issue if it happens. 9791 */ 9792 init_signal_test_thread_continued = true; 9793 } 9794 9795 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9796 9797 static void vmx_init_signal_test(void) 9798 { 9799 struct vmcs *test_vmcs; 9800 9801 if (cpu_count() < 2) { 9802 report_skip(__func__); 9803 return; 9804 } 9805 9806 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9807 vmcs_save(&test_vmcs); 9808 vmcs_clear(test_vmcs); 9809 9810 vmx_set_test_stage(0); 9811 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9812 9813 /* Wait for other CPU to enter VMX operation */ 9814 while (vmx_get_test_stage() != 1) 9815 ; 9816 9817 /* Send INIT signal to other CPU */ 9818 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9819 id_map[1]); 9820 /* Signal other CPU we have sent INIT signal */ 9821 vmx_set_test_stage(2); 9822 9823 /* 9824 * Wait reasonable amount of time for INIT signal to 9825 * be received on other CPU and verify that other CPU 9826 * have proceed as usual to next test stage as INIT 9827 * signal should be blocked while other CPU in 9828 * VMX operation 9829 */ 9830 delay(INIT_SIGNAL_TEST_DELAY); 9831 report(vmx_get_test_stage() == 3, 9832 "INIT signal blocked when CPU in VMX operation"); 9833 /* No point to continue if we failed at this point */ 9834 if (vmx_get_test_stage() != 3) 9835 return; 9836 9837 /* Signal other CPU to enter VMX non-root mode */ 9838 init_signal_test_exit_reason = -1ull; 9839 vmx_set_test_stage(4); 9840 /* 9841 * Wait reasonable amont of time for other CPU 9842 * to exit to VMX root mode 9843 */ 9844 delay(INIT_SIGNAL_TEST_DELAY); 9845 if (vmx_get_test_stage() != 5) { 9846 report_fail("Pending INIT signal didn't result in VMX exit"); 9847 return; 9848 } 9849 report(init_signal_test_exit_reason == VMX_INIT, 9850 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9851 exit_reason_description(init_signal_test_exit_reason), 9852 init_signal_test_exit_reason); 9853 9854 /* Run guest to completion */ 9855 make_vmcs_current(test_vmcs); 9856 enter_guest(); 9857 9858 /* Signal other CPU to exit VMX operation */ 9859 init_signal_test_thread_continued = false; 9860 vmx_set_test_stage(6); 9861 9862 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9863 delay(INIT_SIGNAL_TEST_DELAY); 9864 report(vmx_get_test_stage() == 7, 9865 "INIT signal consumed on VMX_INIT exit"); 9866 /* No point to continue if we failed at this point */ 9867 if (vmx_get_test_stage() != 7) 9868 return; 9869 9870 /* Signal other CPU to enter VMX operation */ 9871 vmx_set_test_stage(8); 9872 /* Wait for other CPU to enter VMX operation */ 9873 while (vmx_get_test_stage() != 9) 9874 ; 9875 9876 /* Send INIT signal to other CPU */ 9877 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9878 id_map[1]); 9879 /* Signal other CPU we have sent INIT signal */ 9880 vmx_set_test_stage(10); 9881 9882 /* 9883 * Wait reasonable amount of time for other CPU 9884 * to exit VMX operation and process INIT signal 9885 */ 9886 delay(INIT_SIGNAL_TEST_DELAY); 9887 report(!init_signal_test_thread_continued, 9888 "INIT signal processed after exit VMX operation"); 9889 9890 /* 9891 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9892 * to re-init it to kvm-unit-tests standard environment. 9893 * Somehow (?) verify that SIPI was indeed received. 9894 */ 9895 } 9896 9897 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9898 9899 static void vmx_sipi_test_guest(void) 9900 { 9901 if (apic_id() == 0) { 9902 /* wait AP enter guest with activity=WAIT_SIPI */ 9903 while (vmx_get_test_stage() != 1) 9904 ; 9905 delay(SIPI_SIGNAL_TEST_DELAY); 9906 9907 /* First SIPI signal */ 9908 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9909 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9910 9911 /* wait AP enter guest */ 9912 while (vmx_get_test_stage() != 2) 9913 ; 9914 delay(SIPI_SIGNAL_TEST_DELAY); 9915 9916 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9917 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9918 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9919 9920 /* Delay a while to check whether second SIPI would cause VMExit */ 9921 delay(SIPI_SIGNAL_TEST_DELAY); 9922 9923 /* Test is done, notify AP to exit test */ 9924 vmx_set_test_stage(3); 9925 9926 /* wait AP exit non-root mode */ 9927 while (vmx_get_test_stage() != 5) 9928 ; 9929 } else { 9930 /* wait BSP notify test is done */ 9931 while (vmx_get_test_stage() != 3) 9932 ; 9933 9934 /* AP exit guest */ 9935 vmx_set_test_stage(4); 9936 } 9937 } 9938 9939 static void sipi_test_ap_thread(void *data) 9940 { 9941 struct vmcs *ap_vmcs; 9942 u64 *ap_vmxon_region; 9943 void *ap_stack, *ap_syscall_stack; 9944 u64 cpu_ctrl_0 = CPU_SECONDARY; 9945 u64 cpu_ctrl_1 = 0; 9946 9947 /* Enter VMX operation (i.e. exec VMXON) */ 9948 ap_vmxon_region = alloc_page(); 9949 enable_vmx(); 9950 init_vmx(ap_vmxon_region); 9951 _vmx_on(ap_vmxon_region); 9952 init_vmcs(&ap_vmcs); 9953 make_vmcs_current(ap_vmcs); 9954 9955 /* Set stack for AP */ 9956 ap_stack = alloc_page(); 9957 ap_syscall_stack = alloc_page(); 9958 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9959 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9960 9961 /* passthrough lapic to L2 */ 9962 disable_intercept_for_x2apic_msrs(); 9963 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9964 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9965 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9966 9967 /* Set guest activity state to wait-for-SIPI state */ 9968 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9969 9970 vmx_set_test_stage(1); 9971 9972 /* AP enter guest */ 9973 enter_guest(); 9974 9975 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9976 report_pass("AP: Handle SIPI VMExit"); 9977 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9978 vmx_set_test_stage(2); 9979 } else { 9980 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9981 vmx_off(); 9982 return; 9983 } 9984 9985 /* AP enter guest */ 9986 enter_guest(); 9987 9988 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9989 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9990 9991 /* notify BSP that AP is already exit from non-root mode */ 9992 vmx_set_test_stage(5); 9993 9994 /* Leave VMX operation */ 9995 vmx_off(); 9996 } 9997 9998 static void vmx_sipi_signal_test(void) 9999 { 10000 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 10001 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 10002 return; 10003 } 10004 10005 if (cpu_count() < 2) { 10006 report_skip(__func__); 10007 return; 10008 } 10009 10010 u64 cpu_ctrl_0 = CPU_SECONDARY; 10011 u64 cpu_ctrl_1 = 0; 10012 10013 /* passthrough lapic to L2 */ 10014 disable_intercept_for_x2apic_msrs(); 10015 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10016 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10017 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10018 10019 test_set_guest(vmx_sipi_test_guest); 10020 10021 /* update CR3 on AP */ 10022 on_cpu(1, update_cr3, (void *)read_cr3()); 10023 10024 /* start AP */ 10025 on_cpu_async(1, sipi_test_ap_thread, NULL); 10026 10027 vmx_set_test_stage(0); 10028 10029 /* BSP enter guest */ 10030 enter_guest(); 10031 } 10032 10033 10034 enum vmcs_access { 10035 ACCESS_VMREAD, 10036 ACCESS_VMWRITE, 10037 ACCESS_NONE, 10038 }; 10039 10040 struct vmcs_shadow_test_common { 10041 enum vmcs_access op; 10042 enum Reason reason; 10043 u64 field; 10044 u64 value; 10045 u64 flags; 10046 u64 time; 10047 } l1_l2_common; 10048 10049 static inline u64 vmread_flags(u64 field, u64 *val) 10050 { 10051 u64 flags; 10052 10053 asm volatile ("vmread %2, %1; pushf; pop %0" 10054 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10055 return flags & X86_EFLAGS_ALU; 10056 } 10057 10058 static inline u64 vmwrite_flags(u64 field, u64 val) 10059 { 10060 u64 flags; 10061 10062 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10063 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10064 return flags & X86_EFLAGS_ALU; 10065 } 10066 10067 static void vmx_vmcs_shadow_test_guest(void) 10068 { 10069 struct vmcs_shadow_test_common *c = &l1_l2_common; 10070 u64 start; 10071 10072 while (c->op != ACCESS_NONE) { 10073 start = rdtsc(); 10074 switch (c->op) { 10075 default: 10076 c->flags = -1ull; 10077 break; 10078 case ACCESS_VMREAD: 10079 c->flags = vmread_flags(c->field, &c->value); 10080 break; 10081 case ACCESS_VMWRITE: 10082 c->flags = vmwrite_flags(c->field, 0); 10083 break; 10084 } 10085 c->time = rdtsc() - start; 10086 vmcall(); 10087 } 10088 } 10089 10090 static u64 vmread_from_shadow(u64 field) 10091 { 10092 struct vmcs *primary; 10093 struct vmcs *shadow; 10094 u64 value; 10095 10096 TEST_ASSERT(!vmcs_save(&primary)); 10097 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10098 TEST_ASSERT(!make_vmcs_current(shadow)); 10099 value = vmcs_read(field); 10100 TEST_ASSERT(!make_vmcs_current(primary)); 10101 return value; 10102 } 10103 10104 static u64 vmwrite_to_shadow(u64 field, u64 value) 10105 { 10106 struct vmcs *primary; 10107 struct vmcs *shadow; 10108 10109 TEST_ASSERT(!vmcs_save(&primary)); 10110 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10111 TEST_ASSERT(!make_vmcs_current(shadow)); 10112 vmcs_write(field, value); 10113 value = vmcs_read(field); 10114 TEST_ASSERT(!make_vmcs_current(primary)); 10115 return value; 10116 } 10117 10118 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10119 { 10120 struct vmcs_shadow_test_common *c = &l1_l2_common; 10121 10122 c->op = access; 10123 vmcs_write(VMX_INST_ERROR, 0); 10124 enter_guest(); 10125 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10126 if (c->reason != VMX_VMCALL) { 10127 skip_exit_insn(); 10128 enter_guest(); 10129 } 10130 skip_exit_vmcall(); 10131 } 10132 10133 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10134 { 10135 struct vmcs_shadow_test_common *c = &l1_l2_common; 10136 struct vmcs *shadow; 10137 u64 value; 10138 uintptr_t flags[2]; 10139 bool good_shadow; 10140 u32 vmx_inst_error; 10141 10142 report_prefix_pushf("field %lx", field); 10143 c->field = field; 10144 10145 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10146 if (shadow != (struct vmcs *)-1ull) { 10147 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10148 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10149 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10150 } else { 10151 /* 10152 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10153 * shadowed-fields should fail with setting RFLAGS.CF. 10154 */ 10155 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10156 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10157 good_shadow = false; 10158 } 10159 10160 /* Intercept both VMREAD and VMWRITE. */ 10161 report_prefix_push("no VMREAD/VMWRITE permission"); 10162 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10163 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10164 set_bit(field, bitmap[ACCESS_VMREAD]); 10165 set_bit(field, bitmap[ACCESS_VMWRITE]); 10166 } 10167 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10168 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10169 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10170 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10171 report_prefix_pop(); 10172 10173 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10174 goto out; 10175 10176 /* Permit shadowed VMREAD. */ 10177 report_prefix_push("VMREAD permission only"); 10178 clear_bit(field, bitmap[ACCESS_VMREAD]); 10179 set_bit(field, bitmap[ACCESS_VMWRITE]); 10180 if (good_shadow) 10181 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10182 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10183 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10184 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10185 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10186 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10187 c->time); 10188 report(c->flags == flags[ACCESS_VMREAD], 10189 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10190 c->flags, flags[ACCESS_VMREAD]); 10191 if (good_shadow) 10192 report(c->value == value, 10193 "value read from shadow (%lx) is as expected (%lx)", 10194 c->value, value); 10195 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10196 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10197 "VMX_INST_ERROR (%d) is as expected (%d)", 10198 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10199 report_prefix_pop(); 10200 10201 /* Permit shadowed VMWRITE. */ 10202 report_prefix_push("VMWRITE permission only"); 10203 set_bit(field, bitmap[ACCESS_VMREAD]); 10204 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10205 if (good_shadow) 10206 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10207 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10208 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10209 report(c->reason == VMX_VMCALL, 10210 "shadowed for VMWRITE (in %ld cycles)", 10211 c->time); 10212 report(c->flags == flags[ACCESS_VMREAD], 10213 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10214 c->flags, flags[ACCESS_VMREAD]); 10215 if (good_shadow) { 10216 value = vmread_from_shadow(field); 10217 report(value == 0, 10218 "shadow VMCS value (%lx) is as expected (%lx)", value, 10219 0ul); 10220 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10221 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10222 "VMX_INST_ERROR (%d) is as expected (%d)", 10223 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10224 } 10225 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10226 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10227 report_prefix_pop(); 10228 10229 /* Permit shadowed VMREAD and VMWRITE. */ 10230 report_prefix_push("VMREAD and VMWRITE permission"); 10231 clear_bit(field, bitmap[ACCESS_VMREAD]); 10232 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10233 if (good_shadow) 10234 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10235 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10236 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10237 report(c->reason == VMX_VMCALL, 10238 "shadowed for VMWRITE (in %ld cycles)", 10239 c->time); 10240 report(c->flags == flags[ACCESS_VMREAD], 10241 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10242 c->flags, flags[ACCESS_VMREAD]); 10243 if (good_shadow) { 10244 value = vmread_from_shadow(field); 10245 report(value == 0, 10246 "shadow VMCS value (%lx) is as expected (%lx)", value, 10247 0ul); 10248 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10249 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10250 "VMX_INST_ERROR (%d) is as expected (%d)", 10251 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10252 } 10253 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10254 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10255 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10256 c->time); 10257 report(c->flags == flags[ACCESS_VMREAD], 10258 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10259 c->flags, flags[ACCESS_VMREAD]); 10260 if (good_shadow) 10261 report(c->value == 0, 10262 "value read from shadow (%lx) is as expected (%lx)", 10263 c->value, 0ul); 10264 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10265 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10266 "VMX_INST_ERROR (%d) is as expected (%d)", 10267 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10268 report_prefix_pop(); 10269 10270 out: 10271 report_prefix_pop(); 10272 } 10273 10274 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10275 { 10276 unsigned base; 10277 unsigned index; 10278 unsigned bit; 10279 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10280 10281 /* Run test on all possible valid VMCS fields */ 10282 for (base = 0; 10283 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10284 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10285 for (index = 0; index <= highest_index; index++) 10286 vmcs_shadow_test_field(bitmap, base + index); 10287 10288 /* 10289 * Run tests on some invalid VMCS fields 10290 * (Have reserved bit set). 10291 */ 10292 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10293 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10294 } 10295 10296 static void vmx_vmcs_shadow_test(void) 10297 { 10298 u8 *bitmap[2]; 10299 struct vmcs *shadow; 10300 10301 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10302 printf("\t'Activate secondary controls' not supported.\n"); 10303 return; 10304 } 10305 10306 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10307 printf("\t'VMCS shadowing' not supported.\n"); 10308 return; 10309 } 10310 10311 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10312 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10313 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10314 return; 10315 } 10316 10317 test_set_guest(vmx_vmcs_shadow_test_guest); 10318 10319 bitmap[ACCESS_VMREAD] = alloc_page(); 10320 bitmap[ACCESS_VMWRITE] = alloc_page(); 10321 10322 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10323 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10324 10325 shadow = alloc_page(); 10326 shadow->hdr.revision_id = basic.revision; 10327 shadow->hdr.shadow_vmcs = 1; 10328 TEST_ASSERT(!vmcs_clear(shadow)); 10329 10330 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10331 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10332 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10333 10334 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10335 report_prefix_push("valid link pointer"); 10336 vmx_vmcs_shadow_test_body(bitmap); 10337 report_prefix_pop(); 10338 10339 vmcs_write(VMCS_LINK_PTR, -1ull); 10340 report_prefix_push("invalid link pointer"); 10341 vmx_vmcs_shadow_test_body(bitmap); 10342 report_prefix_pop(); 10343 10344 l1_l2_common.op = ACCESS_NONE; 10345 enter_guest(); 10346 } 10347 10348 /* 10349 * This test monitors the difference between a guest RDTSC instruction 10350 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10351 * VM-exit MSR-store list when taking a VM-exit on the instruction 10352 * following RDTSC. 10353 */ 10354 #define RDTSC_DIFF_ITERS 100000 10355 #define RDTSC_DIFF_FAILS 100 10356 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10357 10358 /* 10359 * Set 'use TSC offsetting' and set the guest offset to the 10360 * inverse of the host's current TSC value, so that the guest starts running 10361 * with an effective TSC value of 0. 10362 */ 10363 static void reset_guest_tsc_to_zero(void) 10364 { 10365 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10366 vmcs_write(TSC_OFFSET, -rdtsc()); 10367 } 10368 10369 static void rdtsc_vmexit_diff_test_guest(void) 10370 { 10371 int i; 10372 10373 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10374 /* Ensure rdtsc is the last instruction before the vmcall. */ 10375 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10376 } 10377 10378 /* 10379 * This function only considers the "use TSC offsetting" VM-execution 10380 * control. It does not handle "use TSC scaling" (because the latter 10381 * isn't available to the host today.) 10382 */ 10383 static unsigned long long host_time_to_guest_time(unsigned long long t) 10384 { 10385 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10386 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10387 10388 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10389 t += vmcs_read(TSC_OFFSET); 10390 10391 return t; 10392 } 10393 10394 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10395 { 10396 unsigned long long guest_tsc, host_to_guest_tsc; 10397 10398 enter_guest(); 10399 skip_exit_vmcall(); 10400 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10401 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10402 10403 return host_to_guest_tsc - guest_tsc; 10404 } 10405 10406 static void rdtsc_vmexit_diff_test(void) 10407 { 10408 unsigned long long delta; 10409 int fail = 0; 10410 int i; 10411 10412 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10413 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10414 10415 test_set_guest(rdtsc_vmexit_diff_test_guest); 10416 10417 reset_guest_tsc_to_zero(); 10418 10419 /* 10420 * Set up the VMCS12 VM-exit MSR-store list to store just one 10421 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10422 * in the host time domain (i.e., it is not adjusted according 10423 * to the TSC multiplier and TSC offset fields in the VMCS12, 10424 * as a guest RDTSC would be.) 10425 */ 10426 exit_msr_store = alloc_page(); 10427 exit_msr_store[0].index = MSR_IA32_TSC; 10428 vmcs_write(EXI_MSR_ST_CNT, 1); 10429 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10430 10431 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10432 delta = rdtsc_vmexit_diff_test_iteration(); 10433 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10434 fail++; 10435 } 10436 10437 enter_guest(); 10438 10439 report(fail < RDTSC_DIFF_FAILS, 10440 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10441 fail, i, delta); 10442 } 10443 10444 static int invalid_msr_init(struct vmcs *vmcs) 10445 { 10446 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10447 printf("\tPreemption timer is not supported\n"); 10448 return VMX_TEST_EXIT; 10449 } 10450 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10451 preempt_val = 10000000; 10452 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10453 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10454 10455 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10456 printf("\tSave preemption value is not supported\n"); 10457 10458 vmcs_write(ENT_MSR_LD_CNT, 1); 10459 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10460 10461 return VMX_TEST_START; 10462 } 10463 10464 10465 static void invalid_msr_main(void) 10466 { 10467 report_fail("Invalid MSR load"); 10468 } 10469 10470 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10471 { 10472 report_fail("Invalid MSR load"); 10473 print_vmexit_info(exit_reason); 10474 return VMX_TEST_EXIT; 10475 } 10476 10477 static int invalid_msr_entry_failure(struct vmentry_result *result) 10478 { 10479 report(result->exit_reason.failed_vmentry && 10480 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10481 return VMX_TEST_VMEXIT; 10482 } 10483 10484 /* 10485 * The max number of MSRs in an atomic switch MSR list is: 10486 * (111B + 1) * 512 = 4096 10487 * 10488 * Each list entry consumes: 10489 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10490 * 10491 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10492 */ 10493 static const u32 msr_list_page_order = 5; 10494 10495 static void atomic_switch_msr_limit_test_guest(void) 10496 { 10497 vmcall(); 10498 } 10499 10500 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10501 size_t byte_capacity, int count) 10502 { 10503 int i; 10504 10505 for (i = 0; i < count; i++) { 10506 msr_list[i].index = MSR_IA32_TSC; 10507 msr_list[i].reserved = 0; 10508 msr_list[i].value = 0x1234567890abcdef; 10509 } 10510 10511 memset(msr_list + count, 0xff, 10512 byte_capacity - count * sizeof(*msr_list)); 10513 } 10514 10515 static int max_msr_list_size(void) 10516 { 10517 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10518 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10519 10520 return factor * 512; 10521 } 10522 10523 static void atomic_switch_msrs_test(int count) 10524 { 10525 struct vmx_msr_entry *vm_enter_load; 10526 struct vmx_msr_entry *vm_exit_load; 10527 struct vmx_msr_entry *vm_exit_store; 10528 int max_allowed = max_msr_list_size(); 10529 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10530 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10531 int exit_count = count > max_allowed ? max_allowed : count; 10532 int cleanup_count = count > max_allowed ? 2 : 1; 10533 int i; 10534 10535 /* 10536 * Check for the IA32_TSC MSR, 10537 * available with the "TSC flag" and used to populate the MSR lists. 10538 */ 10539 if (!(cpuid(1).d & (1 << 4))) { 10540 report_skip(__func__); 10541 return; 10542 } 10543 10544 /* Set L2 guest. */ 10545 test_set_guest(atomic_switch_msr_limit_test_guest); 10546 10547 /* Setup atomic MSR switch lists. */ 10548 vm_enter_load = alloc_pages(msr_list_page_order); 10549 vm_exit_load = alloc_pages(msr_list_page_order); 10550 vm_exit_store = alloc_pages(msr_list_page_order); 10551 10552 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10553 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10554 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10555 10556 /* 10557 * VM-Enter should succeed up to the max number of MSRs per list, and 10558 * should not consume junk beyond the last entry. 10559 */ 10560 populate_msr_list(vm_enter_load, byte_capacity, count); 10561 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10562 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10563 10564 vmcs_write(ENT_MSR_LD_CNT, count); 10565 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10566 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10567 10568 if (count <= max_allowed) { 10569 enter_guest(); 10570 assert_exit_reason(VMX_VMCALL); 10571 skip_exit_vmcall(); 10572 } else { 10573 u32 exit_qual; 10574 10575 test_guest_state("Invalid MSR Load Count", true, count, 10576 "ENT_MSR_LD_CNT"); 10577 10578 exit_qual = vmcs_read(EXI_QUALIFICATION); 10579 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10580 exit_qual, max_allowed + 1); 10581 } 10582 10583 /* Cleanup. */ 10584 vmcs_write(ENT_MSR_LD_CNT, 0); 10585 vmcs_write(EXI_MSR_LD_CNT, 0); 10586 vmcs_write(EXI_MSR_ST_CNT, 0); 10587 for (i = 0; i < cleanup_count; i++) { 10588 enter_guest(); 10589 skip_exit_vmcall(); 10590 } 10591 free_pages_by_order(vm_enter_load, msr_list_page_order); 10592 free_pages_by_order(vm_exit_load, msr_list_page_order); 10593 free_pages_by_order(vm_exit_store, msr_list_page_order); 10594 } 10595 10596 static void atomic_switch_max_msrs_test(void) 10597 { 10598 atomic_switch_msrs_test(max_msr_list_size()); 10599 } 10600 10601 static void atomic_switch_overflow_msrs_test(void) 10602 { 10603 if (test_device_enabled()) 10604 atomic_switch_msrs_test(max_msr_list_size() + 1); 10605 else 10606 test_skip("Test is only supported on KVM"); 10607 } 10608 10609 static void vmx_pf_exception_test_guest(void) 10610 { 10611 ac_test_run(PT_LEVEL_PML4); 10612 } 10613 10614 static void vmx_pf_exception_test(void) 10615 { 10616 u64 efer; 10617 struct cpuid cpuid; 10618 10619 test_set_guest(vmx_pf_exception_test_guest); 10620 10621 enter_guest(); 10622 10623 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10624 switch (vmcs_read(EXI_REASON)) { 10625 case VMX_RDMSR: 10626 assert(regs.rcx == MSR_EFER); 10627 efer = vmcs_read(GUEST_EFER); 10628 regs.rdx = efer >> 32; 10629 regs.rax = efer & 0xffffffff; 10630 break; 10631 case VMX_WRMSR: 10632 assert(regs.rcx == MSR_EFER); 10633 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10634 vmcs_write(GUEST_EFER, efer); 10635 break; 10636 case VMX_CPUID: 10637 cpuid = (struct cpuid) {0, 0, 0, 0}; 10638 cpuid = raw_cpuid(regs.rax, regs.rcx); 10639 regs.rax = cpuid.a; 10640 regs.rbx = cpuid.b; 10641 regs.rcx = cpuid.c; 10642 regs.rdx = cpuid.d; 10643 break; 10644 default: 10645 assert_msg(false, 10646 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10647 exit_reason_description(vmcs_read(EXI_REASON)), 10648 vmcs_read(EXI_REASON)); 10649 } 10650 skip_exit_insn(); 10651 enter_guest(); 10652 } 10653 10654 assert_exit_reason(VMX_VMCALL); 10655 } 10656 #define TEST(name) { #name, .v2 = name } 10657 10658 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10659 struct vmx_test vmx_tests[] = { 10660 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10661 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10662 { "preemption timer", preemption_timer_init, preemption_timer_main, 10663 preemption_timer_exit_handler, NULL, {0} }, 10664 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10665 test_ctrl_pat_exit_handler, NULL, {0} }, 10666 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10667 test_ctrl_efer_exit_handler, NULL, {0} }, 10668 { "CR shadowing", NULL, cr_shadowing_main, 10669 cr_shadowing_exit_handler, NULL, {0} }, 10670 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10671 NULL, {0} }, 10672 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10673 insn_intercept_exit_handler, NULL, {0} }, 10674 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10675 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10676 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10677 { "interrupt", interrupt_init, interrupt_main, 10678 interrupt_exit_handler, NULL, {0} }, 10679 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10680 nmi_hlt_exit_handler, NULL, {0} }, 10681 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10682 NULL, {0} }, 10683 { "MSR switch", msr_switch_init, msr_switch_main, 10684 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10685 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10686 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10687 disable_rdtscp_exit_handler, NULL, {0} }, 10688 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10689 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10690 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10691 exit_monitor_from_l2_handler, NULL, {0} }, 10692 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10693 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10694 /* Basic V2 tests. */ 10695 TEST(v2_null_test), 10696 TEST(v2_multiple_entries_test), 10697 TEST(fixture_test_case1), 10698 TEST(fixture_test_case2), 10699 /* Opcode tests. */ 10700 TEST(invvpid_test), 10701 /* VM-entry tests */ 10702 TEST(vmx_controls_test), 10703 TEST(vmx_host_state_area_test), 10704 TEST(vmx_guest_state_area_test), 10705 TEST(vmentry_movss_shadow_test), 10706 TEST(vmentry_unrestricted_guest_test), 10707 /* APICv tests */ 10708 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10709 TEST(vmx_hlt_with_rvi_test), 10710 TEST(apic_reg_virt_test), 10711 TEST(virt_x2apic_mode_test), 10712 /* APIC pass-through tests */ 10713 TEST(vmx_apic_passthrough_test), 10714 TEST(vmx_apic_passthrough_thread_test), 10715 TEST(vmx_apic_passthrough_tpr_threshold_test), 10716 TEST(vmx_init_signal_test), 10717 TEST(vmx_sipi_signal_test), 10718 /* VMCS Shadowing tests */ 10719 TEST(vmx_vmcs_shadow_test), 10720 /* Regression tests */ 10721 TEST(vmx_ldtr_test), 10722 TEST(vmx_cr_load_test), 10723 TEST(vmx_cr4_osxsave_test), 10724 TEST(vmx_nm_test), 10725 TEST(vmx_db_test), 10726 TEST(vmx_nmi_window_test), 10727 TEST(vmx_intr_window_test), 10728 TEST(vmx_pending_event_test), 10729 TEST(vmx_pending_event_hlt_test), 10730 TEST(vmx_store_tsc_test), 10731 TEST(vmx_preemption_timer_zero_test), 10732 TEST(vmx_preemption_timer_tf_test), 10733 TEST(vmx_preemption_timer_expiry_test), 10734 /* EPT access tests. */ 10735 TEST(ept_access_test_not_present), 10736 TEST(ept_access_test_read_only), 10737 TEST(ept_access_test_write_only), 10738 TEST(ept_access_test_read_write), 10739 TEST(ept_access_test_execute_only), 10740 TEST(ept_access_test_read_execute), 10741 TEST(ept_access_test_write_execute), 10742 TEST(ept_access_test_read_write_execute), 10743 TEST(ept_access_test_reserved_bits), 10744 TEST(ept_access_test_ignored_bits), 10745 TEST(ept_access_test_paddr_not_present_ad_disabled), 10746 TEST(ept_access_test_paddr_not_present_ad_enabled), 10747 TEST(ept_access_test_paddr_read_only_ad_disabled), 10748 TEST(ept_access_test_paddr_read_only_ad_enabled), 10749 TEST(ept_access_test_paddr_read_write), 10750 TEST(ept_access_test_paddr_read_write_execute), 10751 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10752 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10753 TEST(ept_access_test_paddr_not_present_page_fault), 10754 TEST(ept_access_test_force_2m_page), 10755 /* Atomic MSR switch tests. */ 10756 TEST(atomic_switch_max_msrs_test), 10757 TEST(atomic_switch_overflow_msrs_test), 10758 TEST(rdtsc_vmexit_diff_test), 10759 TEST(vmx_mtf_test), 10760 TEST(vmx_mtf_pdpte_test), 10761 TEST(vmx_pf_exception_test), 10762 { NULL, NULL, NULL, NULL, NULL, {0} }, 10763 }; 10764