1 /* 2 * All test cases of nested virtualization should be in this file 3 * 4 * Author : Arthur Chunqi Li <yzt356@gmail.com> 5 */ 6 7 #include <asm/debugreg.h> 8 9 #include "vmx.h" 10 #include "msr.h" 11 #include "processor.h" 12 #include "vm.h" 13 #include "pci.h" 14 #include "fwcfg.h" 15 #include "isr.h" 16 #include "desc.h" 17 #include "apic.h" 18 #include "types.h" 19 #include "vmalloc.h" 20 #include "alloc_page.h" 21 #include "smp.h" 22 #include "delay.h" 23 #include "access.h" 24 25 #define VPID_CAP_INVVPID_TYPES_SHIFT 40 26 27 u64 ia32_pat; 28 u64 ia32_efer; 29 void *io_bitmap_a, *io_bitmap_b; 30 u16 ioport; 31 32 unsigned long *pml4; 33 u64 eptp; 34 void *data_page1, *data_page2; 35 36 phys_addr_t pci_physaddr; 37 38 void *pml_log; 39 #define PML_INDEX 512 40 41 static inline unsigned ffs(unsigned x) 42 { 43 int pos = -1; 44 45 __asm__ __volatile__("bsf %1, %%eax; cmovnz %%eax, %0" 46 : "+r"(pos) : "rm"(x) : "eax"); 47 return pos + 1; 48 } 49 50 static inline void vmcall(void) 51 { 52 asm volatile("vmcall"); 53 } 54 55 static void basic_guest_main(void) 56 { 57 report_pass("Basic VMX test"); 58 } 59 60 static int basic_exit_handler(union exit_reason exit_reason) 61 { 62 report_fail("Basic VMX test"); 63 print_vmexit_info(exit_reason); 64 return VMX_TEST_EXIT; 65 } 66 67 static void vmenter_main(void) 68 { 69 u64 rax; 70 u64 rsp, resume_rsp; 71 72 report_pass("test vmlaunch"); 73 74 asm volatile( 75 "mov %%rsp, %0\n\t" 76 "mov %3, %%rax\n\t" 77 "vmcall\n\t" 78 "mov %%rax, %1\n\t" 79 "mov %%rsp, %2\n\t" 80 : "=r"(rsp), "=r"(rax), "=r"(resume_rsp) 81 : "g"(0xABCD)); 82 report((rax == 0xFFFF) && (rsp == resume_rsp), "test vmresume"); 83 } 84 85 static int vmenter_exit_handler(union exit_reason exit_reason) 86 { 87 u64 guest_rip = vmcs_read(GUEST_RIP); 88 89 switch (exit_reason.basic) { 90 case VMX_VMCALL: 91 if (regs.rax != 0xABCD) { 92 report_fail("test vmresume"); 93 return VMX_TEST_VMEXIT; 94 } 95 regs.rax = 0xFFFF; 96 vmcs_write(GUEST_RIP, guest_rip + 3); 97 return VMX_TEST_RESUME; 98 default: 99 report_fail("test vmresume"); 100 print_vmexit_info(exit_reason); 101 } 102 return VMX_TEST_VMEXIT; 103 } 104 105 u32 preempt_scale; 106 volatile unsigned long long tsc_val; 107 volatile u32 preempt_val; 108 u64 saved_rip; 109 110 static int preemption_timer_init(struct vmcs *vmcs) 111 { 112 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 113 printf("\tPreemption timer is not supported\n"); 114 return VMX_TEST_EXIT; 115 } 116 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 117 preempt_val = 10000000; 118 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 119 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 120 121 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 122 printf("\tSave preemption value is not supported\n"); 123 124 return VMX_TEST_START; 125 } 126 127 static void preemption_timer_main(void) 128 { 129 tsc_val = rdtsc(); 130 if (ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) { 131 vmx_set_test_stage(0); 132 vmcall(); 133 if (vmx_get_test_stage() == 1) 134 vmcall(); 135 } 136 vmx_set_test_stage(1); 137 while (vmx_get_test_stage() == 1) { 138 if (((rdtsc() - tsc_val) >> preempt_scale) 139 > 10 * preempt_val) { 140 vmx_set_test_stage(2); 141 vmcall(); 142 } 143 } 144 tsc_val = rdtsc(); 145 asm volatile ("hlt"); 146 vmcall(); 147 vmx_set_test_stage(5); 148 vmcall(); 149 } 150 151 static int preemption_timer_exit_handler(union exit_reason exit_reason) 152 { 153 bool guest_halted; 154 u64 guest_rip; 155 u32 insn_len; 156 u32 ctrl_exit; 157 158 guest_rip = vmcs_read(GUEST_RIP); 159 insn_len = vmcs_read(EXI_INST_LEN); 160 switch (exit_reason.basic) { 161 case VMX_PREEMPT: 162 switch (vmx_get_test_stage()) { 163 case 1: 164 case 2: 165 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val, 166 "busy-wait for preemption timer"); 167 vmx_set_test_stage(3); 168 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 169 return VMX_TEST_RESUME; 170 case 3: 171 guest_halted = 172 (vmcs_read(GUEST_ACTV_STATE) == ACTV_HLT); 173 report(((rdtsc() - tsc_val) >> preempt_scale) >= preempt_val 174 && guest_halted, 175 "preemption timer during hlt"); 176 vmx_set_test_stage(4); 177 vmcs_write(PIN_CONTROLS, 178 vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 179 vmcs_write(EXI_CONTROLS, 180 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_PREEMPT); 181 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 182 return VMX_TEST_RESUME; 183 case 4: 184 report(saved_rip == guest_rip, 185 "preemption timer with 0 value"); 186 break; 187 default: 188 report_fail("Invalid stage."); 189 print_vmexit_info(exit_reason); 190 break; 191 } 192 break; 193 case VMX_VMCALL: 194 vmcs_write(GUEST_RIP, guest_rip + insn_len); 195 switch (vmx_get_test_stage()) { 196 case 0: 197 report(vmcs_read(PREEMPT_TIMER_VALUE) == preempt_val, 198 "Keep preemption value"); 199 vmx_set_test_stage(1); 200 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 201 ctrl_exit = (vmcs_read(EXI_CONTROLS) | 202 EXI_SAVE_PREEMPT) & ctrl_exit_rev.clr; 203 vmcs_write(EXI_CONTROLS, ctrl_exit); 204 return VMX_TEST_RESUME; 205 case 1: 206 report(vmcs_read(PREEMPT_TIMER_VALUE) < preempt_val, 207 "Save preemption value"); 208 return VMX_TEST_RESUME; 209 case 2: 210 report_fail("busy-wait for preemption timer"); 211 vmx_set_test_stage(3); 212 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 213 return VMX_TEST_RESUME; 214 case 3: 215 report_fail("preemption timer during hlt"); 216 vmx_set_test_stage(4); 217 /* fall through */ 218 case 4: 219 vmcs_write(PIN_CONTROLS, 220 vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 221 vmcs_write(PREEMPT_TIMER_VALUE, 0); 222 saved_rip = guest_rip + insn_len; 223 return VMX_TEST_RESUME; 224 case 5: 225 report_fail("preemption timer with 0 value (vmcall stage 5)"); 226 break; 227 default: 228 // Should not reach here 229 report_fail("unexpected stage, %d", 230 vmx_get_test_stage()); 231 print_vmexit_info(exit_reason); 232 return VMX_TEST_VMEXIT; 233 } 234 break; 235 default: 236 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 237 print_vmexit_info(exit_reason); 238 } 239 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_PREEMPT); 240 return VMX_TEST_VMEXIT; 241 } 242 243 static void msr_bmp_init(void) 244 { 245 void *msr_bitmap; 246 u32 ctrl_cpu0; 247 248 msr_bitmap = alloc_page(); 249 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 250 ctrl_cpu0 |= CPU_MSR_BITMAP; 251 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 252 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 253 } 254 255 static void *get_msr_bitmap(void) 256 { 257 void *msr_bitmap; 258 259 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_MSR_BITMAP) { 260 msr_bitmap = (void *)vmcs_read(MSR_BITMAP); 261 } else { 262 msr_bitmap = alloc_page(); 263 memset(msr_bitmap, 0xff, PAGE_SIZE); 264 vmcs_write(MSR_BITMAP, (u64)msr_bitmap); 265 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_MSR_BITMAP); 266 } 267 268 return msr_bitmap; 269 } 270 271 static void disable_intercept_for_x2apic_msrs(void) 272 { 273 unsigned long *msr_bitmap = (unsigned long *)get_msr_bitmap(); 274 u32 msr; 275 276 for (msr = APIC_BASE_MSR; 277 msr < (APIC_BASE_MSR+0xff); 278 msr += BITS_PER_LONG) { 279 unsigned int word = msr / BITS_PER_LONG; 280 281 msr_bitmap[word] = 0; 282 msr_bitmap[word + (0x800 / sizeof(long))] = 0; 283 } 284 } 285 286 static int test_ctrl_pat_init(struct vmcs *vmcs) 287 { 288 u64 ctrl_ent; 289 u64 ctrl_exi; 290 291 msr_bmp_init(); 292 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT) && 293 !(ctrl_exit_rev.clr & EXI_LOAD_PAT) && 294 !(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 295 printf("\tSave/load PAT is not supported\n"); 296 return 1; 297 } 298 299 ctrl_ent = vmcs_read(ENT_CONTROLS); 300 ctrl_exi = vmcs_read(EXI_CONTROLS); 301 ctrl_ent |= ctrl_enter_rev.clr & ENT_LOAD_PAT; 302 ctrl_exi |= ctrl_exit_rev.clr & (EXI_SAVE_PAT | EXI_LOAD_PAT); 303 vmcs_write(ENT_CONTROLS, ctrl_ent); 304 vmcs_write(EXI_CONTROLS, ctrl_exi); 305 ia32_pat = rdmsr(MSR_IA32_CR_PAT); 306 vmcs_write(GUEST_PAT, 0x0); 307 vmcs_write(HOST_PAT, ia32_pat); 308 return VMX_TEST_START; 309 } 310 311 static void test_ctrl_pat_main(void) 312 { 313 u64 guest_ia32_pat; 314 315 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 316 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) 317 printf("\tENT_LOAD_PAT is not supported.\n"); 318 else { 319 if (guest_ia32_pat != 0) { 320 report_fail("Entry load PAT"); 321 return; 322 } 323 } 324 wrmsr(MSR_IA32_CR_PAT, 0x6); 325 vmcall(); 326 guest_ia32_pat = rdmsr(MSR_IA32_CR_PAT); 327 if (ctrl_enter_rev.clr & ENT_LOAD_PAT) 328 report(guest_ia32_pat == ia32_pat, "Entry load PAT"); 329 } 330 331 static int test_ctrl_pat_exit_handler(union exit_reason exit_reason) 332 { 333 u64 guest_rip; 334 u64 guest_pat; 335 336 guest_rip = vmcs_read(GUEST_RIP); 337 switch (exit_reason.basic) { 338 case VMX_VMCALL: 339 guest_pat = vmcs_read(GUEST_PAT); 340 if (!(ctrl_exit_rev.clr & EXI_SAVE_PAT)) { 341 printf("\tEXI_SAVE_PAT is not supported\n"); 342 vmcs_write(GUEST_PAT, 0x6); 343 } else { 344 report(guest_pat == 0x6, "Exit save PAT"); 345 } 346 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) 347 printf("\tEXI_LOAD_PAT is not supported\n"); 348 else 349 report(rdmsr(MSR_IA32_CR_PAT) == ia32_pat, 350 "Exit load PAT"); 351 vmcs_write(GUEST_PAT, ia32_pat); 352 vmcs_write(GUEST_RIP, guest_rip + 3); 353 return VMX_TEST_RESUME; 354 default: 355 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 356 break; 357 } 358 return VMX_TEST_VMEXIT; 359 } 360 361 static int test_ctrl_efer_init(struct vmcs *vmcs) 362 { 363 u64 ctrl_ent; 364 u64 ctrl_exi; 365 366 msr_bmp_init(); 367 ctrl_ent = vmcs_read(ENT_CONTROLS) | ENT_LOAD_EFER; 368 ctrl_exi = vmcs_read(EXI_CONTROLS) | EXI_SAVE_EFER | EXI_LOAD_EFER; 369 vmcs_write(ENT_CONTROLS, ctrl_ent & ctrl_enter_rev.clr); 370 vmcs_write(EXI_CONTROLS, ctrl_exi & ctrl_exit_rev.clr); 371 ia32_efer = rdmsr(MSR_EFER); 372 vmcs_write(GUEST_EFER, ia32_efer ^ EFER_NX); 373 vmcs_write(HOST_EFER, ia32_efer ^ EFER_NX); 374 return VMX_TEST_START; 375 } 376 377 static void test_ctrl_efer_main(void) 378 { 379 u64 guest_ia32_efer; 380 381 guest_ia32_efer = rdmsr(MSR_EFER); 382 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) 383 printf("\tENT_LOAD_EFER is not supported.\n"); 384 else { 385 if (guest_ia32_efer != (ia32_efer ^ EFER_NX)) { 386 report_fail("Entry load EFER"); 387 return; 388 } 389 } 390 wrmsr(MSR_EFER, ia32_efer); 391 vmcall(); 392 guest_ia32_efer = rdmsr(MSR_EFER); 393 if (ctrl_enter_rev.clr & ENT_LOAD_EFER) 394 report(guest_ia32_efer == ia32_efer, "Entry load EFER"); 395 } 396 397 static int test_ctrl_efer_exit_handler(union exit_reason exit_reason) 398 { 399 u64 guest_rip; 400 u64 guest_efer; 401 402 guest_rip = vmcs_read(GUEST_RIP); 403 switch (exit_reason.basic) { 404 case VMX_VMCALL: 405 guest_efer = vmcs_read(GUEST_EFER); 406 if (!(ctrl_exit_rev.clr & EXI_SAVE_EFER)) { 407 printf("\tEXI_SAVE_EFER is not supported\n"); 408 vmcs_write(GUEST_EFER, ia32_efer); 409 } else { 410 report(guest_efer == ia32_efer, "Exit save EFER"); 411 } 412 if (!(ctrl_exit_rev.clr & EXI_LOAD_EFER)) { 413 printf("\tEXI_LOAD_EFER is not supported\n"); 414 wrmsr(MSR_EFER, ia32_efer ^ EFER_NX); 415 } else { 416 report(rdmsr(MSR_EFER) == (ia32_efer ^ EFER_NX), 417 "Exit load EFER"); 418 } 419 vmcs_write(GUEST_PAT, ia32_efer); 420 vmcs_write(GUEST_RIP, guest_rip + 3); 421 return VMX_TEST_RESUME; 422 default: 423 printf("ERROR : Unknown exit reason, 0x%x.\n", exit_reason.full); 424 break; 425 } 426 return VMX_TEST_VMEXIT; 427 } 428 429 u32 guest_cr0, guest_cr4; 430 431 static void cr_shadowing_main(void) 432 { 433 u32 cr0, cr4, tmp; 434 435 // Test read through 436 vmx_set_test_stage(0); 437 guest_cr0 = read_cr0(); 438 if (vmx_get_test_stage() == 1) 439 report_fail("Read through CR0"); 440 else 441 vmcall(); 442 vmx_set_test_stage(1); 443 guest_cr4 = read_cr4(); 444 if (vmx_get_test_stage() == 2) 445 report_fail("Read through CR4"); 446 else 447 vmcall(); 448 // Test write through 449 guest_cr0 = guest_cr0 ^ (X86_CR0_TS | X86_CR0_MP); 450 guest_cr4 = guest_cr4 ^ (X86_CR4_TSD | X86_CR4_DE); 451 vmx_set_test_stage(2); 452 write_cr0(guest_cr0); 453 if (vmx_get_test_stage() == 3) 454 report_fail("Write throuth CR0"); 455 else 456 vmcall(); 457 vmx_set_test_stage(3); 458 write_cr4(guest_cr4); 459 if (vmx_get_test_stage() == 4) 460 report_fail("Write through CR4"); 461 else 462 vmcall(); 463 // Test read shadow 464 vmx_set_test_stage(4); 465 vmcall(); 466 cr0 = read_cr0(); 467 if (vmx_get_test_stage() != 5) 468 report(cr0 == guest_cr0, "Read shadowing CR0"); 469 vmx_set_test_stage(5); 470 cr4 = read_cr4(); 471 if (vmx_get_test_stage() != 6) 472 report(cr4 == guest_cr4, "Read shadowing CR4"); 473 // Test write shadow (same value with shadow) 474 vmx_set_test_stage(6); 475 write_cr0(guest_cr0); 476 if (vmx_get_test_stage() == 7) 477 report_fail("Write shadowing CR0 (same value with shadow)"); 478 else 479 vmcall(); 480 vmx_set_test_stage(7); 481 write_cr4(guest_cr4); 482 if (vmx_get_test_stage() == 8) 483 report_fail("Write shadowing CR4 (same value with shadow)"); 484 else 485 vmcall(); 486 // Test write shadow (different value) 487 vmx_set_test_stage(8); 488 tmp = guest_cr0 ^ X86_CR0_TS; 489 asm volatile("mov %0, %%rsi\n\t" 490 "mov %%rsi, %%cr0\n\t" 491 ::"m"(tmp) 492 :"rsi", "memory", "cc"); 493 report(vmx_get_test_stage() == 9, 494 "Write shadowing different X86_CR0_TS"); 495 vmx_set_test_stage(9); 496 tmp = guest_cr0 ^ X86_CR0_MP; 497 asm volatile("mov %0, %%rsi\n\t" 498 "mov %%rsi, %%cr0\n\t" 499 ::"m"(tmp) 500 :"rsi", "memory", "cc"); 501 report(vmx_get_test_stage() == 10, 502 "Write shadowing different X86_CR0_MP"); 503 vmx_set_test_stage(10); 504 tmp = guest_cr4 ^ X86_CR4_TSD; 505 asm volatile("mov %0, %%rsi\n\t" 506 "mov %%rsi, %%cr4\n\t" 507 ::"m"(tmp) 508 :"rsi", "memory", "cc"); 509 report(vmx_get_test_stage() == 11, 510 "Write shadowing different X86_CR4_TSD"); 511 vmx_set_test_stage(11); 512 tmp = guest_cr4 ^ X86_CR4_DE; 513 asm volatile("mov %0, %%rsi\n\t" 514 "mov %%rsi, %%cr4\n\t" 515 ::"m"(tmp) 516 :"rsi", "memory", "cc"); 517 report(vmx_get_test_stage() == 12, 518 "Write shadowing different X86_CR4_DE"); 519 } 520 521 static int cr_shadowing_exit_handler(union exit_reason exit_reason) 522 { 523 u64 guest_rip; 524 u32 insn_len; 525 u32 exit_qual; 526 527 guest_rip = vmcs_read(GUEST_RIP); 528 insn_len = vmcs_read(EXI_INST_LEN); 529 exit_qual = vmcs_read(EXI_QUALIFICATION); 530 switch (exit_reason.basic) { 531 case VMX_VMCALL: 532 switch (vmx_get_test_stage()) { 533 case 0: 534 report(guest_cr0 == vmcs_read(GUEST_CR0), 535 "Read through CR0"); 536 break; 537 case 1: 538 report(guest_cr4 == vmcs_read(GUEST_CR4), 539 "Read through CR4"); 540 break; 541 case 2: 542 report(guest_cr0 == vmcs_read(GUEST_CR0), 543 "Write through CR0"); 544 break; 545 case 3: 546 report(guest_cr4 == vmcs_read(GUEST_CR4), 547 "Write through CR4"); 548 break; 549 case 4: 550 guest_cr0 = vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP); 551 guest_cr4 = vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE); 552 vmcs_write(CR0_MASK, X86_CR0_TS | X86_CR0_MP); 553 vmcs_write(CR0_READ_SHADOW, guest_cr0 & (X86_CR0_TS | X86_CR0_MP)); 554 vmcs_write(CR4_MASK, X86_CR4_TSD | X86_CR4_DE); 555 vmcs_write(CR4_READ_SHADOW, guest_cr4 & (X86_CR4_TSD | X86_CR4_DE)); 556 break; 557 case 6: 558 report(guest_cr0 == (vmcs_read(GUEST_CR0) ^ (X86_CR0_TS | X86_CR0_MP)), 559 "Write shadowing CR0 (same value)"); 560 break; 561 case 7: 562 report(guest_cr4 == (vmcs_read(GUEST_CR4) ^ (X86_CR4_TSD | X86_CR4_DE)), 563 "Write shadowing CR4 (same value)"); 564 break; 565 default: 566 // Should not reach here 567 report_fail("unexpected stage, %d", 568 vmx_get_test_stage()); 569 print_vmexit_info(exit_reason); 570 return VMX_TEST_VMEXIT; 571 } 572 vmcs_write(GUEST_RIP, guest_rip + insn_len); 573 return VMX_TEST_RESUME; 574 case VMX_CR: 575 switch (vmx_get_test_stage()) { 576 case 4: 577 report_fail("Read shadowing CR0"); 578 vmx_inc_test_stage(); 579 break; 580 case 5: 581 report_fail("Read shadowing CR4"); 582 vmx_inc_test_stage(); 583 break; 584 case 6: 585 report_fail("Write shadowing CR0 (same value)"); 586 vmx_inc_test_stage(); 587 break; 588 case 7: 589 report_fail("Write shadowing CR4 (same value)"); 590 vmx_inc_test_stage(); 591 break; 592 case 8: 593 case 9: 594 // 0x600 encodes "mov %esi, %cr0" 595 if (exit_qual == 0x600) 596 vmx_inc_test_stage(); 597 break; 598 case 10: 599 case 11: 600 // 0x604 encodes "mov %esi, %cr4" 601 if (exit_qual == 0x604) 602 vmx_inc_test_stage(); 603 break; 604 default: 605 // Should not reach here 606 report_fail("unexpected stage, %d", 607 vmx_get_test_stage()); 608 print_vmexit_info(exit_reason); 609 return VMX_TEST_VMEXIT; 610 } 611 vmcs_write(GUEST_RIP, guest_rip + insn_len); 612 return VMX_TEST_RESUME; 613 default: 614 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 615 print_vmexit_info(exit_reason); 616 } 617 return VMX_TEST_VMEXIT; 618 } 619 620 static int iobmp_init(struct vmcs *vmcs) 621 { 622 u32 ctrl_cpu0; 623 624 io_bitmap_a = alloc_page(); 625 io_bitmap_b = alloc_page(); 626 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 627 ctrl_cpu0 |= CPU_IO_BITMAP; 628 ctrl_cpu0 &= (~CPU_IO); 629 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 630 vmcs_write(IO_BITMAP_A, (u64)io_bitmap_a); 631 vmcs_write(IO_BITMAP_B, (u64)io_bitmap_b); 632 return VMX_TEST_START; 633 } 634 635 static void iobmp_main(void) 636 { 637 // stage 0, test IO pass 638 vmx_set_test_stage(0); 639 inb(0x5000); 640 outb(0x0, 0x5000); 641 report(vmx_get_test_stage() == 0, "I/O bitmap - I/O pass"); 642 // test IO width, in/out 643 ((u8 *)io_bitmap_a)[0] = 0xFF; 644 vmx_set_test_stage(2); 645 inb(0x0); 646 report(vmx_get_test_stage() == 3, "I/O bitmap - trap in"); 647 vmx_set_test_stage(3); 648 outw(0x0, 0x0); 649 report(vmx_get_test_stage() == 4, "I/O bitmap - trap out"); 650 vmx_set_test_stage(4); 651 inl(0x0); 652 report(vmx_get_test_stage() == 5, "I/O bitmap - I/O width, long"); 653 // test low/high IO port 654 vmx_set_test_stage(5); 655 ((u8 *)io_bitmap_a)[0x5000 / 8] = (1 << (0x5000 % 8)); 656 inb(0x5000); 657 report(vmx_get_test_stage() == 6, "I/O bitmap - I/O port, low part"); 658 vmx_set_test_stage(6); 659 ((u8 *)io_bitmap_b)[0x1000 / 8] = (1 << (0x1000 % 8)); 660 inb(0x9000); 661 report(vmx_get_test_stage() == 7, "I/O bitmap - I/O port, high part"); 662 // test partial pass 663 vmx_set_test_stage(7); 664 inl(0x4FFF); 665 report(vmx_get_test_stage() == 8, "I/O bitmap - partial pass"); 666 // test overrun 667 vmx_set_test_stage(8); 668 memset(io_bitmap_a, 0x0, PAGE_SIZE); 669 memset(io_bitmap_b, 0x0, PAGE_SIZE); 670 inl(0xFFFF); 671 report(vmx_get_test_stage() == 9, "I/O bitmap - overrun"); 672 vmx_set_test_stage(9); 673 vmcall(); 674 outb(0x0, 0x0); 675 report(vmx_get_test_stage() == 9, 676 "I/O bitmap - ignore unconditional exiting"); 677 vmx_set_test_stage(10); 678 vmcall(); 679 outb(0x0, 0x0); 680 report(vmx_get_test_stage() == 11, 681 "I/O bitmap - unconditional exiting"); 682 } 683 684 static int iobmp_exit_handler(union exit_reason exit_reason) 685 { 686 u64 guest_rip; 687 ulong exit_qual; 688 u32 insn_len, ctrl_cpu0; 689 690 guest_rip = vmcs_read(GUEST_RIP); 691 exit_qual = vmcs_read(EXI_QUALIFICATION); 692 insn_len = vmcs_read(EXI_INST_LEN); 693 switch (exit_reason.basic) { 694 case VMX_IO: 695 switch (vmx_get_test_stage()) { 696 case 0: 697 case 1: 698 vmx_inc_test_stage(); 699 break; 700 case 2: 701 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_BYTE, 702 "I/O bitmap - I/O width, byte"); 703 report(exit_qual & VMX_IO_IN, 704 "I/O bitmap - I/O direction, in"); 705 vmx_inc_test_stage(); 706 break; 707 case 3: 708 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_WORD, 709 "I/O bitmap - I/O width, word"); 710 report(!(exit_qual & VMX_IO_IN), 711 "I/O bitmap - I/O direction, out"); 712 vmx_inc_test_stage(); 713 break; 714 case 4: 715 report((exit_qual & VMX_IO_SIZE_MASK) == _VMX_IO_LONG, 716 "I/O bitmap - I/O width, long"); 717 vmx_inc_test_stage(); 718 break; 719 case 5: 720 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x5000) 721 vmx_inc_test_stage(); 722 break; 723 case 6: 724 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x9000) 725 vmx_inc_test_stage(); 726 break; 727 case 7: 728 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0x4FFF) 729 vmx_inc_test_stage(); 730 break; 731 case 8: 732 if (((exit_qual & VMX_IO_PORT_MASK) >> VMX_IO_PORT_SHIFT) == 0xFFFF) 733 vmx_inc_test_stage(); 734 break; 735 case 9: 736 case 10: 737 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 738 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0 & ~CPU_IO); 739 vmx_inc_test_stage(); 740 break; 741 default: 742 // Should not reach here 743 report_fail("unexpected stage, %d", 744 vmx_get_test_stage()); 745 print_vmexit_info(exit_reason); 746 return VMX_TEST_VMEXIT; 747 } 748 vmcs_write(GUEST_RIP, guest_rip + insn_len); 749 return VMX_TEST_RESUME; 750 case VMX_VMCALL: 751 switch (vmx_get_test_stage()) { 752 case 9: 753 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 754 ctrl_cpu0 |= CPU_IO | CPU_IO_BITMAP; 755 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 756 break; 757 case 10: 758 ctrl_cpu0 = vmcs_read(CPU_EXEC_CTRL0); 759 ctrl_cpu0 = (ctrl_cpu0 & ~CPU_IO_BITMAP) | CPU_IO; 760 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu0); 761 break; 762 default: 763 // Should not reach here 764 report_fail("unexpected stage, %d", 765 vmx_get_test_stage()); 766 print_vmexit_info(exit_reason); 767 return VMX_TEST_VMEXIT; 768 } 769 vmcs_write(GUEST_RIP, guest_rip + insn_len); 770 return VMX_TEST_RESUME; 771 default: 772 printf("guest_rip = %#lx\n", guest_rip); 773 printf("\tERROR : Unknown exit reason, 0x%x\n", exit_reason.full); 774 break; 775 } 776 return VMX_TEST_VMEXIT; 777 } 778 779 #define INSN_CPU0 0 780 #define INSN_CPU1 1 781 #define INSN_ALWAYS_TRAP 2 782 783 #define FIELD_EXIT_QUAL (1 << 0) 784 #define FIELD_INSN_INFO (1 << 1) 785 786 asm( 787 "insn_hlt: hlt;ret\n\t" 788 "insn_invlpg: invlpg 0x12345678;ret\n\t" 789 "insn_mwait: xor %eax, %eax; xor %ecx, %ecx; mwait;ret\n\t" 790 "insn_rdpmc: xor %ecx, %ecx; rdpmc;ret\n\t" 791 "insn_rdtsc: rdtsc;ret\n\t" 792 "insn_cr3_load: mov cr3,%rax; mov %rax,%cr3;ret\n\t" 793 "insn_cr3_store: mov %cr3,%rax;ret\n\t" 794 "insn_cr8_load: xor %eax, %eax; mov %rax,%cr8;ret\n\t" 795 "insn_cr8_store: mov %cr8,%rax;ret\n\t" 796 "insn_monitor: xor %eax, %eax; xor %ecx, %ecx; xor %edx, %edx; monitor;ret\n\t" 797 "insn_pause: pause;ret\n\t" 798 "insn_wbinvd: wbinvd;ret\n\t" 799 "insn_cpuid: mov $10, %eax; cpuid;ret\n\t" 800 "insn_invd: invd;ret\n\t" 801 "insn_sgdt: sgdt gdt_descr;ret\n\t" 802 "insn_lgdt: lgdt gdt_descr;ret\n\t" 803 "insn_sidt: sidt idt_descr;ret\n\t" 804 "insn_lidt: lidt idt_descr;ret\n\t" 805 "insn_sldt: sldt %ax;ret\n\t" 806 "insn_lldt: xor %eax, %eax; lldt %ax;ret\n\t" 807 "insn_str: str %ax;ret\n\t" 808 "insn_rdrand: rdrand %rax;ret\n\t" 809 "insn_rdseed: rdseed %rax;ret\n\t" 810 ); 811 extern void insn_hlt(void); 812 extern void insn_invlpg(void); 813 extern void insn_mwait(void); 814 extern void insn_rdpmc(void); 815 extern void insn_rdtsc(void); 816 extern void insn_cr3_load(void); 817 extern void insn_cr3_store(void); 818 extern void insn_cr8_load(void); 819 extern void insn_cr8_store(void); 820 extern void insn_monitor(void); 821 extern void insn_pause(void); 822 extern void insn_wbinvd(void); 823 extern void insn_sgdt(void); 824 extern void insn_lgdt(void); 825 extern void insn_sidt(void); 826 extern void insn_lidt(void); 827 extern void insn_sldt(void); 828 extern void insn_lldt(void); 829 extern void insn_str(void); 830 extern void insn_cpuid(void); 831 extern void insn_invd(void); 832 extern void insn_rdrand(void); 833 extern void insn_rdseed(void); 834 835 u32 cur_insn; 836 u64 cr3; 837 838 #define X86_FEATURE_MONITOR (1 << 3) 839 840 typedef bool (*supported_fn)(void); 841 842 static bool monitor_supported(void) 843 { 844 return this_cpu_has(X86_FEATURE_MWAIT); 845 } 846 847 struct insn_table { 848 const char *name; 849 u32 flag; 850 void (*insn_func)(void); 851 u32 type; 852 u32 reason; 853 ulong exit_qual; 854 u32 insn_info; 855 // Use FIELD_EXIT_QUAL and FIELD_INSN_INFO to define 856 // which field need to be tested, reason is always tested 857 u32 test_field; 858 const supported_fn supported_fn; 859 u8 disabled; 860 }; 861 862 /* 863 * Add more test cases of instruction intercept here. Elements in this 864 * table is: 865 * name/control flag/insn function/type/exit reason/exit qulification/ 866 * instruction info/field to test 867 * The last field defines which fields (exit_qual and insn_info) need to be 868 * tested in exit handler. If set to 0, only "reason" is checked. 869 */ 870 static struct insn_table insn_table[] = { 871 // Flags for Primary Processor-Based VM-Execution Controls 872 {"HLT", CPU_HLT, insn_hlt, INSN_CPU0, 12, 0, 0, 0}, 873 {"INVLPG", CPU_INVLPG, insn_invlpg, INSN_CPU0, 14, 874 0x12345678, 0, FIELD_EXIT_QUAL}, 875 {"MWAIT", CPU_MWAIT, insn_mwait, INSN_CPU0, 36, 0, 0, 0, &monitor_supported}, 876 {"RDPMC", CPU_RDPMC, insn_rdpmc, INSN_CPU0, 15, 0, 0, 0}, 877 {"RDTSC", CPU_RDTSC, insn_rdtsc, INSN_CPU0, 16, 0, 0, 0}, 878 {"CR3 load", CPU_CR3_LOAD, insn_cr3_load, INSN_CPU0, 28, 0x3, 0, 879 FIELD_EXIT_QUAL}, 880 {"CR3 store", CPU_CR3_STORE, insn_cr3_store, INSN_CPU0, 28, 0x13, 0, 881 FIELD_EXIT_QUAL}, 882 {"CR8 load", CPU_CR8_LOAD, insn_cr8_load, INSN_CPU0, 28, 0x8, 0, 883 FIELD_EXIT_QUAL}, 884 {"CR8 store", CPU_CR8_STORE, insn_cr8_store, INSN_CPU0, 28, 0x18, 0, 885 FIELD_EXIT_QUAL}, 886 {"MONITOR", CPU_MONITOR, insn_monitor, INSN_CPU0, 39, 0, 0, 0, &monitor_supported}, 887 {"PAUSE", CPU_PAUSE, insn_pause, INSN_CPU0, 40, 0, 0, 0}, 888 // Flags for Secondary Processor-Based VM-Execution Controls 889 {"WBINVD", CPU_WBINVD, insn_wbinvd, INSN_CPU1, 54, 0, 0, 0}, 890 {"DESC_TABLE (SGDT)", CPU_DESC_TABLE, insn_sgdt, INSN_CPU1, 46, 0, 0, 0}, 891 {"DESC_TABLE (LGDT)", CPU_DESC_TABLE, insn_lgdt, INSN_CPU1, 46, 0, 0, 0}, 892 {"DESC_TABLE (SIDT)", CPU_DESC_TABLE, insn_sidt, INSN_CPU1, 46, 0, 0, 0}, 893 {"DESC_TABLE (LIDT)", CPU_DESC_TABLE, insn_lidt, INSN_CPU1, 46, 0, 0, 0}, 894 {"DESC_TABLE (SLDT)", CPU_DESC_TABLE, insn_sldt, INSN_CPU1, 47, 0, 0, 0}, 895 {"DESC_TABLE (LLDT)", CPU_DESC_TABLE, insn_lldt, INSN_CPU1, 47, 0, 0, 0}, 896 {"DESC_TABLE (STR)", CPU_DESC_TABLE, insn_str, INSN_CPU1, 47, 0, 0, 0}, 897 /* LTR causes a #GP if done with a busy selector, so it is not tested. */ 898 {"RDRAND", CPU_RDRAND, insn_rdrand, INSN_CPU1, VMX_RDRAND, 0, 0, 0}, 899 {"RDSEED", CPU_RDSEED, insn_rdseed, INSN_CPU1, VMX_RDSEED, 0, 0, 0}, 900 // Instructions always trap 901 {"CPUID", 0, insn_cpuid, INSN_ALWAYS_TRAP, 10, 0, 0, 0}, 902 {"INVD", 0, insn_invd, INSN_ALWAYS_TRAP, 13, 0, 0, 0}, 903 // Instructions never trap 904 {NULL}, 905 }; 906 907 static int insn_intercept_init(struct vmcs *vmcs) 908 { 909 u32 ctrl_cpu, cur_insn; 910 911 ctrl_cpu = ctrl_cpu_rev[0].set | CPU_SECONDARY; 912 ctrl_cpu &= ctrl_cpu_rev[0].clr; 913 vmcs_write(CPU_EXEC_CTRL0, ctrl_cpu); 914 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu_rev[1].set); 915 cr3 = read_cr3(); 916 917 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 918 if (insn_table[cur_insn].supported_fn == NULL) 919 continue; 920 insn_table[cur_insn].disabled = !insn_table[cur_insn].supported_fn(); 921 } 922 return VMX_TEST_START; 923 } 924 925 static void insn_intercept_main(void) 926 { 927 for (cur_insn = 0; insn_table[cur_insn].name != NULL; cur_insn++) { 928 vmx_set_test_stage(cur_insn * 2); 929 if ((insn_table[cur_insn].type == INSN_CPU0 && 930 !(ctrl_cpu_rev[0].clr & insn_table[cur_insn].flag)) || 931 (insn_table[cur_insn].type == INSN_CPU1 && 932 !(ctrl_cpu_rev[1].clr & insn_table[cur_insn].flag))) { 933 printf("\tCPU_CTRL%d.CPU_%s is not supported.\n", 934 insn_table[cur_insn].type - INSN_CPU0, 935 insn_table[cur_insn].name); 936 continue; 937 } 938 939 if (insn_table[cur_insn].disabled) { 940 printf("\tFeature required for %s is not supported.\n", 941 insn_table[cur_insn].name); 942 continue; 943 } 944 945 if ((insn_table[cur_insn].type == INSN_CPU0 && 946 !(ctrl_cpu_rev[0].set & insn_table[cur_insn].flag)) || 947 (insn_table[cur_insn].type == INSN_CPU1 && 948 !(ctrl_cpu_rev[1].set & insn_table[cur_insn].flag))) { 949 /* skip hlt, it stalls the guest and is tested below */ 950 if (insn_table[cur_insn].insn_func != insn_hlt) 951 insn_table[cur_insn].insn_func(); 952 report(vmx_get_test_stage() == cur_insn * 2, 953 "execute %s", 954 insn_table[cur_insn].name); 955 } else if (insn_table[cur_insn].type != INSN_ALWAYS_TRAP) 956 printf("\tCPU_CTRL%d.CPU_%s always traps.\n", 957 insn_table[cur_insn].type - INSN_CPU0, 958 insn_table[cur_insn].name); 959 960 vmcall(); 961 962 insn_table[cur_insn].insn_func(); 963 report(vmx_get_test_stage() == cur_insn * 2 + 1, 964 "intercept %s", 965 insn_table[cur_insn].name); 966 967 vmx_set_test_stage(cur_insn * 2 + 1); 968 vmcall(); 969 } 970 } 971 972 static int insn_intercept_exit_handler(union exit_reason exit_reason) 973 { 974 u64 guest_rip; 975 ulong exit_qual; 976 u32 insn_len; 977 u32 insn_info; 978 bool pass; 979 980 guest_rip = vmcs_read(GUEST_RIP); 981 exit_qual = vmcs_read(EXI_QUALIFICATION); 982 insn_len = vmcs_read(EXI_INST_LEN); 983 insn_info = vmcs_read(EXI_INST_INFO); 984 985 if (exit_reason.basic == VMX_VMCALL) { 986 u32 val = 0; 987 988 if (insn_table[cur_insn].type == INSN_CPU0) 989 val = vmcs_read(CPU_EXEC_CTRL0); 990 else if (insn_table[cur_insn].type == INSN_CPU1) 991 val = vmcs_read(CPU_EXEC_CTRL1); 992 993 if (vmx_get_test_stage() & 1) 994 val &= ~insn_table[cur_insn].flag; 995 else 996 val |= insn_table[cur_insn].flag; 997 998 if (insn_table[cur_insn].type == INSN_CPU0) 999 vmcs_write(CPU_EXEC_CTRL0, val | ctrl_cpu_rev[0].set); 1000 else if (insn_table[cur_insn].type == INSN_CPU1) 1001 vmcs_write(CPU_EXEC_CTRL1, val | ctrl_cpu_rev[1].set); 1002 } else { 1003 pass = (cur_insn * 2 == vmx_get_test_stage()) && 1004 insn_table[cur_insn].reason == exit_reason.full; 1005 if (insn_table[cur_insn].test_field & FIELD_EXIT_QUAL && 1006 insn_table[cur_insn].exit_qual != exit_qual) 1007 pass = false; 1008 if (insn_table[cur_insn].test_field & FIELD_INSN_INFO && 1009 insn_table[cur_insn].insn_info != insn_info) 1010 pass = false; 1011 if (pass) 1012 vmx_inc_test_stage(); 1013 } 1014 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1015 return VMX_TEST_RESUME; 1016 } 1017 1018 /** 1019 * __setup_ept - Setup the VMCS fields to enable Extended Page Tables (EPT) 1020 * @hpa: Host physical address of the top-level, a.k.a. root, EPT table 1021 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1022 * 1023 * Returns 0 on success, 1 on failure. 1024 * 1025 * Note that @hpa doesn't need to point at actual memory if VM-Launch is 1026 * expected to fail, e.g. setup_dummy_ept() arbitrarily passes '0' to satisfy 1027 * the various EPTP consistency checks, but doesn't ensure backing for HPA '0'. 1028 */ 1029 static int __setup_ept(u64 hpa, bool enable_ad) 1030 { 1031 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1032 !(ctrl_cpu_rev[1].clr & CPU_EPT)) { 1033 printf("\tEPT is not supported\n"); 1034 return 1; 1035 } 1036 if (!(ept_vpid.val & EPT_CAP_WB)) { 1037 printf("\tWB memtype for EPT walks not supported\n"); 1038 return 1; 1039 } 1040 if (!(ept_vpid.val & EPT_CAP_PWL4)) { 1041 printf("\tPWL4 is not supported\n"); 1042 return 1; 1043 } 1044 1045 eptp = EPT_MEM_TYPE_WB; 1046 eptp |= (3 << EPTP_PG_WALK_LEN_SHIFT); 1047 eptp |= hpa; 1048 if (enable_ad) 1049 eptp |= EPTP_AD_FLAG; 1050 1051 vmcs_write(EPTP, eptp); 1052 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0)| CPU_SECONDARY); 1053 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1)| CPU_EPT); 1054 1055 return 0; 1056 } 1057 1058 /** 1059 * setup_ept - Enable Extended Page Tables (EPT) and setup an identity map 1060 * @enable_ad: Whether or not to enable Access/Dirty bits for EPT entries 1061 * 1062 * Returns 0 on success, 1 on failure. 1063 * 1064 * This is the "real" function for setting up EPT tables, i.e. use this for 1065 * tests that need to run code in the guest with EPT enabled. 1066 */ 1067 static int setup_ept(bool enable_ad) 1068 { 1069 unsigned long end_of_memory; 1070 1071 pml4 = alloc_page(); 1072 1073 if (__setup_ept(virt_to_phys(pml4), enable_ad)) 1074 return 1; 1075 1076 end_of_memory = fwcfg_get_u64(FW_CFG_RAM_SIZE); 1077 if (end_of_memory < (1ul << 32)) 1078 end_of_memory = (1ul << 32); 1079 /* Cannot use large EPT pages if we need to track EPT 1080 * accessed/dirty bits at 4K granularity. 1081 */ 1082 setup_ept_range(pml4, 0, end_of_memory, 0, 1083 !enable_ad && ept_2m_supported(), 1084 EPT_WA | EPT_RA | EPT_EA); 1085 return 0; 1086 } 1087 1088 /** 1089 * setup_dummy_ept - Enable Extended Page Tables (EPT) with a dummy root HPA 1090 * 1091 * Setup EPT using a semi-arbitrary dummy root HPA. This function is intended 1092 * for use by tests that need EPT enabled to verify dependent VMCS controls 1093 * but never expect to fully enter the guest, i.e. don't need setup the actual 1094 * EPT tables. 1095 */ 1096 static void setup_dummy_ept(void) 1097 { 1098 if (__setup_ept(0, false)) 1099 report_abort("EPT setup unexpectedly failed"); 1100 } 1101 1102 static int enable_unrestricted_guest(bool need_valid_ept) 1103 { 1104 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1105 !(ctrl_cpu_rev[1].clr & CPU_URG) || 1106 !(ctrl_cpu_rev[1].clr & CPU_EPT)) 1107 return 1; 1108 1109 if (need_valid_ept) 1110 setup_ept(false); 1111 else 1112 setup_dummy_ept(); 1113 1114 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 1115 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 1116 1117 return 0; 1118 } 1119 1120 static void ept_enable_ad_bits(void) 1121 { 1122 eptp |= EPTP_AD_FLAG; 1123 vmcs_write(EPTP, eptp); 1124 } 1125 1126 static void ept_disable_ad_bits(void) 1127 { 1128 eptp &= ~EPTP_AD_FLAG; 1129 vmcs_write(EPTP, eptp); 1130 } 1131 1132 static int ept_ad_enabled(void) 1133 { 1134 return eptp & EPTP_AD_FLAG; 1135 } 1136 1137 static void ept_enable_ad_bits_or_skip_test(void) 1138 { 1139 if (!ept_ad_bits_supported()) 1140 test_skip("EPT AD bits not supported."); 1141 ept_enable_ad_bits(); 1142 } 1143 1144 static int apic_version; 1145 1146 static int ept_init_common(bool have_ad) 1147 { 1148 int ret; 1149 struct pci_dev pcidev; 1150 1151 /* INVEPT is required by the EPT violation handler. */ 1152 if (!is_invept_type_supported(INVEPT_SINGLE)) 1153 return VMX_TEST_EXIT; 1154 1155 if (setup_ept(have_ad)) 1156 return VMX_TEST_EXIT; 1157 1158 data_page1 = alloc_page(); 1159 data_page2 = alloc_page(); 1160 *((u32 *)data_page1) = MAGIC_VAL_1; 1161 *((u32 *)data_page2) = MAGIC_VAL_2; 1162 install_ept(pml4, (unsigned long)data_page1, (unsigned long)data_page2, 1163 EPT_RA | EPT_WA | EPT_EA); 1164 1165 apic_version = apic_read(APIC_LVR); 1166 1167 ret = pci_find_dev(PCI_VENDOR_ID_REDHAT, PCI_DEVICE_ID_REDHAT_TEST); 1168 if (ret != PCIDEVADDR_INVALID) { 1169 pci_dev_init(&pcidev, ret); 1170 pci_physaddr = pcidev.resource[PCI_TESTDEV_BAR_MEM]; 1171 } 1172 1173 return VMX_TEST_START; 1174 } 1175 1176 static int ept_init(struct vmcs *vmcs) 1177 { 1178 return ept_init_common(false); 1179 } 1180 1181 static void ept_common(void) 1182 { 1183 vmx_set_test_stage(0); 1184 if (*((u32 *)data_page2) != MAGIC_VAL_1 || 1185 *((u32 *)data_page1) != MAGIC_VAL_1) 1186 report_fail("EPT basic framework - read"); 1187 else { 1188 *((u32 *)data_page2) = MAGIC_VAL_3; 1189 vmcall(); 1190 if (vmx_get_test_stage() == 1) { 1191 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1192 *((u32 *)data_page2) == MAGIC_VAL_2) 1193 report_pass("EPT basic framework"); 1194 else 1195 report_pass("EPT basic framework - remap"); 1196 } 1197 } 1198 // Test EPT Misconfigurations 1199 vmx_set_test_stage(1); 1200 vmcall(); 1201 *((u32 *)data_page1) = MAGIC_VAL_1; 1202 if (vmx_get_test_stage() != 2) { 1203 report_fail("EPT misconfigurations"); 1204 goto t1; 1205 } 1206 vmx_set_test_stage(2); 1207 vmcall(); 1208 *((u32 *)data_page1) = MAGIC_VAL_1; 1209 report(vmx_get_test_stage() == 3, "EPT misconfigurations"); 1210 t1: 1211 // Test EPT violation 1212 vmx_set_test_stage(3); 1213 vmcall(); 1214 *((u32 *)data_page1) = MAGIC_VAL_1; 1215 report(vmx_get_test_stage() == 4, "EPT violation - page permission"); 1216 // Violation caused by EPT paging structure 1217 vmx_set_test_stage(4); 1218 vmcall(); 1219 *((u32 *)data_page1) = MAGIC_VAL_2; 1220 report(vmx_get_test_stage() == 5, "EPT violation - paging structure"); 1221 1222 // MMIO Read/Write 1223 vmx_set_test_stage(5); 1224 vmcall(); 1225 1226 *(u32 volatile *)pci_physaddr; 1227 report(vmx_get_test_stage() == 6, "MMIO EPT violation - read"); 1228 1229 *(u32 volatile *)pci_physaddr = MAGIC_VAL_1; 1230 report(vmx_get_test_stage() == 7, "MMIO EPT violation - write"); 1231 } 1232 1233 static void ept_main(void) 1234 { 1235 ept_common(); 1236 1237 // Test EPT access to L1 MMIO 1238 vmx_set_test_stage(7); 1239 report(*((u32 *)0xfee00030UL) == apic_version, "EPT - MMIO access"); 1240 1241 // Test invalid operand for INVEPT 1242 vmcall(); 1243 report(vmx_get_test_stage() == 8, "EPT - unsupported INVEPT"); 1244 } 1245 1246 static bool invept_test(int type, u64 eptp) 1247 { 1248 bool ret, supported; 1249 1250 supported = ept_vpid.val & (EPT_CAP_INVEPT_SINGLE >> INVEPT_SINGLE << type); 1251 ret = __invept(type, eptp); 1252 1253 if (ret == !supported) 1254 return false; 1255 1256 if (!supported) 1257 printf("WARNING: unsupported invept passed!\n"); 1258 else 1259 printf("WARNING: invept failed!\n"); 1260 1261 return true; 1262 } 1263 1264 static int pml_exit_handler(union exit_reason exit_reason) 1265 { 1266 u16 index, count; 1267 u64 *pmlbuf = pml_log; 1268 u64 guest_rip = vmcs_read(GUEST_RIP);; 1269 u64 guest_cr3 = vmcs_read(GUEST_CR3); 1270 u32 insn_len = vmcs_read(EXI_INST_LEN); 1271 1272 switch (exit_reason.basic) { 1273 case VMX_VMCALL: 1274 switch (vmx_get_test_stage()) { 1275 case 0: 1276 index = vmcs_read(GUEST_PML_INDEX); 1277 for (count = index + 1; count < PML_INDEX; count++) { 1278 if (pmlbuf[count] == (u64)data_page2) { 1279 vmx_inc_test_stage(); 1280 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1281 break; 1282 } 1283 } 1284 break; 1285 case 1: 1286 index = vmcs_read(GUEST_PML_INDEX); 1287 /* Keep clearing the dirty bit till a overflow */ 1288 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1289 break; 1290 default: 1291 report_fail("unexpected stage, %d.", 1292 vmx_get_test_stage()); 1293 print_vmexit_info(exit_reason); 1294 return VMX_TEST_VMEXIT; 1295 } 1296 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1297 return VMX_TEST_RESUME; 1298 case VMX_PML_FULL: 1299 vmx_inc_test_stage(); 1300 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1301 return VMX_TEST_RESUME; 1302 default: 1303 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1304 print_vmexit_info(exit_reason); 1305 } 1306 return VMX_TEST_VMEXIT; 1307 } 1308 1309 static int ept_exit_handler_common(union exit_reason exit_reason, bool have_ad) 1310 { 1311 u64 guest_rip; 1312 u64 guest_cr3; 1313 u32 insn_len; 1314 u32 exit_qual; 1315 static unsigned long data_page1_pte, data_page1_pte_pte, memaddr_pte, 1316 guest_pte_addr; 1317 1318 guest_rip = vmcs_read(GUEST_RIP); 1319 guest_cr3 = vmcs_read(GUEST_CR3); 1320 insn_len = vmcs_read(EXI_INST_LEN); 1321 exit_qual = vmcs_read(EXI_QUALIFICATION); 1322 pteval_t *ptep; 1323 switch (exit_reason.basic) { 1324 case VMX_VMCALL: 1325 switch (vmx_get_test_stage()) { 1326 case 0: 1327 check_ept_ad(pml4, guest_cr3, 1328 (unsigned long)data_page1, 1329 have_ad ? EPT_ACCESS_FLAG : 0, 1330 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1331 check_ept_ad(pml4, guest_cr3, 1332 (unsigned long)data_page2, 1333 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0, 1334 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1335 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1336 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page2); 1337 if (have_ad) 1338 invept(INVEPT_SINGLE, eptp); 1339 if (*((u32 *)data_page1) == MAGIC_VAL_3 && 1340 *((u32 *)data_page2) == MAGIC_VAL_2) { 1341 vmx_inc_test_stage(); 1342 install_ept(pml4, (unsigned long)data_page2, 1343 (unsigned long)data_page2, 1344 EPT_RA | EPT_WA | EPT_EA); 1345 } else 1346 report_fail("EPT basic framework - write"); 1347 break; 1348 case 1: 1349 install_ept(pml4, (unsigned long)data_page1, 1350 (unsigned long)data_page1, EPT_WA); 1351 invept(INVEPT_SINGLE, eptp); 1352 break; 1353 case 2: 1354 install_ept(pml4, (unsigned long)data_page1, 1355 (unsigned long)data_page1, 1356 EPT_RA | EPT_WA | EPT_EA | 1357 (2 << EPT_MEM_TYPE_SHIFT)); 1358 invept(INVEPT_SINGLE, eptp); 1359 break; 1360 case 3: 1361 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1362 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)data_page1, 1363 1, &data_page1_pte)); 1364 set_ept_pte(pml4, (unsigned long)data_page1, 1365 1, data_page1_pte & ~EPT_PRESENT); 1366 invept(INVEPT_SINGLE, eptp); 1367 break; 1368 case 4: 1369 ptep = get_pte_level((pgd_t *)guest_cr3, data_page1, /*level=*/2); 1370 guest_pte_addr = virt_to_phys(ptep) & PAGE_MASK; 1371 1372 TEST_ASSERT(get_ept_pte(pml4, guest_pte_addr, 2, &data_page1_pte_pte)); 1373 set_ept_pte(pml4, guest_pte_addr, 2, 1374 data_page1_pte_pte & ~EPT_PRESENT); 1375 invept(INVEPT_SINGLE, eptp); 1376 break; 1377 case 5: 1378 install_ept(pml4, (unsigned long)pci_physaddr, 1379 (unsigned long)pci_physaddr, 0); 1380 invept(INVEPT_SINGLE, eptp); 1381 break; 1382 case 7: 1383 if (!invept_test(0, eptp)) 1384 vmx_inc_test_stage(); 1385 break; 1386 // Should not reach here 1387 default: 1388 report_fail("ERROR - unexpected stage, %d.", 1389 vmx_get_test_stage()); 1390 print_vmexit_info(exit_reason); 1391 return VMX_TEST_VMEXIT; 1392 } 1393 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1394 return VMX_TEST_RESUME; 1395 case VMX_EPT_MISCONFIG: 1396 switch (vmx_get_test_stage()) { 1397 case 1: 1398 case 2: 1399 vmx_inc_test_stage(); 1400 install_ept(pml4, (unsigned long)data_page1, 1401 (unsigned long)data_page1, 1402 EPT_RA | EPT_WA | EPT_EA); 1403 invept(INVEPT_SINGLE, eptp); 1404 break; 1405 // Should not reach here 1406 default: 1407 report_fail("ERROR - unexpected stage, %d.", 1408 vmx_get_test_stage()); 1409 print_vmexit_info(exit_reason); 1410 return VMX_TEST_VMEXIT; 1411 } 1412 return VMX_TEST_RESUME; 1413 case VMX_EPT_VIOLATION: 1414 /* 1415 * Exit-qualifications are masked not to account for advanced 1416 * VM-exit information. Once KVM supports this feature, this 1417 * masking should be removed. 1418 */ 1419 exit_qual &= ~EPT_VLT_GUEST_MASK; 1420 1421 switch(vmx_get_test_stage()) { 1422 case 3: 1423 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1424 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1425 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1426 if (exit_qual == (EPT_VLT_WR | EPT_VLT_LADDR_VLD | 1427 EPT_VLT_PADDR)) 1428 vmx_inc_test_stage(); 1429 set_ept_pte(pml4, (unsigned long)data_page1, 1430 1, data_page1_pte | (EPT_PRESENT)); 1431 invept(INVEPT_SINGLE, eptp); 1432 break; 1433 case 4: 1434 check_ept_ad(pml4, guest_cr3, (unsigned long)data_page1, 0, 1435 have_ad ? EPT_ACCESS_FLAG | EPT_DIRTY_FLAG : 0); 1436 clear_ept_ad(pml4, guest_cr3, (unsigned long)data_page1); 1437 if (exit_qual == (EPT_VLT_RD | 1438 (have_ad ? EPT_VLT_WR : 0) | 1439 EPT_VLT_LADDR_VLD)) 1440 vmx_inc_test_stage(); 1441 set_ept_pte(pml4, guest_pte_addr, 2, 1442 data_page1_pte_pte | (EPT_PRESENT)); 1443 invept(INVEPT_SINGLE, eptp); 1444 break; 1445 case 5: 1446 if (exit_qual & EPT_VLT_RD) 1447 vmx_inc_test_stage(); 1448 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1449 1, &memaddr_pte)); 1450 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA); 1451 invept(INVEPT_SINGLE, eptp); 1452 break; 1453 case 6: 1454 if (exit_qual & EPT_VLT_WR) 1455 vmx_inc_test_stage(); 1456 TEST_ASSERT(get_ept_pte(pml4, (unsigned long)pci_physaddr, 1457 1, &memaddr_pte)); 1458 set_ept_pte(pml4, memaddr_pte, 1, memaddr_pte | EPT_RA | EPT_WA); 1459 invept(INVEPT_SINGLE, eptp); 1460 break; 1461 default: 1462 // Should not reach here 1463 report_fail("ERROR : unexpected stage, %d", 1464 vmx_get_test_stage()); 1465 print_vmexit_info(exit_reason); 1466 return VMX_TEST_VMEXIT; 1467 } 1468 return VMX_TEST_RESUME; 1469 default: 1470 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1471 print_vmexit_info(exit_reason); 1472 } 1473 return VMX_TEST_VMEXIT; 1474 } 1475 1476 static int ept_exit_handler(union exit_reason exit_reason) 1477 { 1478 return ept_exit_handler_common(exit_reason, false); 1479 } 1480 1481 static int eptad_init(struct vmcs *vmcs) 1482 { 1483 int r = ept_init_common(true); 1484 1485 if (r == VMX_TEST_EXIT) 1486 return r; 1487 1488 if ((rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & EPT_CAP_AD_FLAG) == 0) { 1489 printf("\tEPT A/D bits are not supported"); 1490 return VMX_TEST_EXIT; 1491 } 1492 1493 return r; 1494 } 1495 1496 static int pml_init(struct vmcs *vmcs) 1497 { 1498 u32 ctrl_cpu; 1499 int r = eptad_init(vmcs); 1500 1501 if (r == VMX_TEST_EXIT) 1502 return r; 1503 1504 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 1505 !(ctrl_cpu_rev[1].clr & CPU_PML)) { 1506 printf("\tPML is not supported"); 1507 return VMX_TEST_EXIT; 1508 } 1509 1510 pml_log = alloc_page(); 1511 vmcs_write(PMLADDR, (u64)pml_log); 1512 vmcs_write(GUEST_PML_INDEX, PML_INDEX - 1); 1513 1514 ctrl_cpu = vmcs_read(CPU_EXEC_CTRL1) | CPU_PML; 1515 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu); 1516 1517 return VMX_TEST_START; 1518 } 1519 1520 static void pml_main(void) 1521 { 1522 int count = 0; 1523 1524 vmx_set_test_stage(0); 1525 *((u32 *)data_page2) = 0x1; 1526 vmcall(); 1527 report(vmx_get_test_stage() == 1, "PML - Dirty GPA Logging"); 1528 1529 while (vmx_get_test_stage() == 1) { 1530 vmcall(); 1531 *((u32 *)data_page2) = 0x1; 1532 if (count++ > PML_INDEX) 1533 break; 1534 } 1535 report(vmx_get_test_stage() == 2, "PML Full Event"); 1536 } 1537 1538 static void eptad_main(void) 1539 { 1540 ept_common(); 1541 } 1542 1543 static int eptad_exit_handler(union exit_reason exit_reason) 1544 { 1545 return ept_exit_handler_common(exit_reason, true); 1546 } 1547 1548 #define TIMER_VECTOR 222 1549 1550 static volatile bool timer_fired; 1551 1552 static void timer_isr(isr_regs_t *regs) 1553 { 1554 timer_fired = true; 1555 apic_write(APIC_EOI, 0); 1556 } 1557 1558 static int interrupt_init(struct vmcs *vmcs) 1559 { 1560 msr_bmp_init(); 1561 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1562 handle_irq(TIMER_VECTOR, timer_isr); 1563 return VMX_TEST_START; 1564 } 1565 1566 static void interrupt_main(void) 1567 { 1568 long long start, loops; 1569 1570 vmx_set_test_stage(0); 1571 1572 apic_write(APIC_LVTT, TIMER_VECTOR); 1573 irq_enable(); 1574 1575 apic_write(APIC_TMICT, 1); 1576 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1577 asm volatile ("nop"); 1578 report(timer_fired, "direct interrupt while running guest"); 1579 1580 apic_write(APIC_TMICT, 0); 1581 irq_disable(); 1582 vmcall(); 1583 timer_fired = false; 1584 apic_write(APIC_TMICT, 1); 1585 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1586 asm volatile ("nop"); 1587 report(timer_fired, "intercepted interrupt while running guest"); 1588 1589 irq_enable(); 1590 apic_write(APIC_TMICT, 0); 1591 irq_disable(); 1592 vmcall(); 1593 timer_fired = false; 1594 start = rdtsc(); 1595 apic_write(APIC_TMICT, 1000000); 1596 1597 safe_halt(); 1598 1599 report(rdtsc() - start > 1000000 && timer_fired, 1600 "direct interrupt + hlt"); 1601 1602 apic_write(APIC_TMICT, 0); 1603 irq_disable(); 1604 vmcall(); 1605 timer_fired = false; 1606 start = rdtsc(); 1607 apic_write(APIC_TMICT, 1000000); 1608 1609 safe_halt(); 1610 1611 report(rdtsc() - start > 10000 && timer_fired, 1612 "intercepted interrupt + hlt"); 1613 1614 apic_write(APIC_TMICT, 0); 1615 irq_disable(); 1616 vmcall(); 1617 timer_fired = false; 1618 start = rdtsc(); 1619 apic_write(APIC_TMICT, 1000000); 1620 1621 irq_enable(); 1622 asm volatile ("nop"); 1623 vmcall(); 1624 1625 report(rdtsc() - start > 10000 && timer_fired, 1626 "direct interrupt + activity state hlt"); 1627 1628 apic_write(APIC_TMICT, 0); 1629 irq_disable(); 1630 vmcall(); 1631 timer_fired = false; 1632 start = rdtsc(); 1633 apic_write(APIC_TMICT, 1000000); 1634 1635 irq_enable(); 1636 asm volatile ("nop"); 1637 vmcall(); 1638 1639 report(rdtsc() - start > 10000 && timer_fired, 1640 "intercepted interrupt + activity state hlt"); 1641 1642 apic_write(APIC_TMICT, 0); 1643 irq_disable(); 1644 vmx_set_test_stage(7); 1645 vmcall(); 1646 timer_fired = false; 1647 apic_write(APIC_TMICT, 1); 1648 for (loops = 0; loops < 10000000 && !timer_fired; loops++) 1649 asm volatile ("nop"); 1650 report(timer_fired, 1651 "running a guest with interrupt acknowledgement set"); 1652 1653 apic_write(APIC_TMICT, 0); 1654 irq_enable(); 1655 timer_fired = false; 1656 vmcall(); 1657 report(timer_fired, "Inject an event to a halted guest"); 1658 } 1659 1660 static int interrupt_exit_handler(union exit_reason exit_reason) 1661 { 1662 u64 guest_rip = vmcs_read(GUEST_RIP); 1663 u32 insn_len = vmcs_read(EXI_INST_LEN); 1664 1665 switch (exit_reason.basic) { 1666 case VMX_VMCALL: 1667 switch (vmx_get_test_stage()) { 1668 case 0: 1669 case 2: 1670 case 5: 1671 vmcs_write(PIN_CONTROLS, 1672 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1673 break; 1674 case 7: 1675 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_INTA); 1676 vmcs_write(PIN_CONTROLS, 1677 vmcs_read(PIN_CONTROLS) | PIN_EXTINT); 1678 break; 1679 case 1: 1680 case 3: 1681 vmcs_write(PIN_CONTROLS, 1682 vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 1683 break; 1684 case 4: 1685 case 6: 1686 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1687 break; 1688 1689 case 8: 1690 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 1691 vmcs_write(ENT_INTR_INFO, 1692 TIMER_VECTOR | 1693 (VMX_INTR_TYPE_EXT_INTR << INTR_INFO_INTR_TYPE_SHIFT) | 1694 INTR_INFO_VALID_MASK); 1695 break; 1696 } 1697 vmx_inc_test_stage(); 1698 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1699 return VMX_TEST_RESUME; 1700 case VMX_EXTINT: 1701 if (vmcs_read(EXI_CONTROLS) & EXI_INTA) { 1702 int vector = vmcs_read(EXI_INTR_INFO) & 0xff; 1703 handle_external_interrupt(vector); 1704 } else { 1705 irq_enable(); 1706 asm volatile ("nop"); 1707 irq_disable(); 1708 } 1709 if (vmx_get_test_stage() >= 2) 1710 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1711 return VMX_TEST_RESUME; 1712 default: 1713 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 1714 print_vmexit_info(exit_reason); 1715 } 1716 1717 return VMX_TEST_VMEXIT; 1718 } 1719 1720 1721 static volatile int nmi_fired; 1722 1723 #define NMI_DELAY 100000000ULL 1724 1725 static void nmi_isr(isr_regs_t *regs) 1726 { 1727 nmi_fired = true; 1728 } 1729 1730 static int nmi_hlt_init(struct vmcs *vmcs) 1731 { 1732 msr_bmp_init(); 1733 handle_irq(NMI_VECTOR, nmi_isr); 1734 vmcs_write(PIN_CONTROLS, 1735 vmcs_read(PIN_CONTROLS) & ~PIN_NMI); 1736 vmcs_write(PIN_CONTROLS, 1737 vmcs_read(PIN_CONTROLS) & ~PIN_VIRT_NMI); 1738 return VMX_TEST_START; 1739 } 1740 1741 static void nmi_message_thread(void *data) 1742 { 1743 while (vmx_get_test_stage() != 1) 1744 pause(); 1745 1746 delay(NMI_DELAY); 1747 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1748 1749 while (vmx_get_test_stage() != 2) 1750 pause(); 1751 1752 delay(NMI_DELAY); 1753 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_NMI | APIC_INT_ASSERT, id_map[0]); 1754 } 1755 1756 static void nmi_hlt_main(void) 1757 { 1758 long long start; 1759 1760 if (cpu_count() < 2) { 1761 report_skip(__func__); 1762 vmx_set_test_stage(-1); 1763 return; 1764 } 1765 1766 vmx_set_test_stage(0); 1767 on_cpu_async(1, nmi_message_thread, NULL); 1768 start = rdtsc(); 1769 vmx_set_test_stage(1); 1770 asm volatile ("hlt"); 1771 report((rdtsc() - start > NMI_DELAY) && nmi_fired, 1772 "direct NMI + hlt"); 1773 if (!nmi_fired) 1774 vmx_set_test_stage(-1); 1775 nmi_fired = false; 1776 1777 vmcall(); 1778 1779 start = rdtsc(); 1780 vmx_set_test_stage(2); 1781 asm volatile ("hlt"); 1782 report((rdtsc() - start > NMI_DELAY) && !nmi_fired, 1783 "intercepted NMI + hlt"); 1784 if (nmi_fired) { 1785 report(!nmi_fired, "intercepted NMI was dispatched"); 1786 vmx_set_test_stage(-1); 1787 return; 1788 } 1789 vmx_set_test_stage(3); 1790 } 1791 1792 static int nmi_hlt_exit_handler(union exit_reason exit_reason) 1793 { 1794 u64 guest_rip = vmcs_read(GUEST_RIP); 1795 u32 insn_len = vmcs_read(EXI_INST_LEN); 1796 1797 switch (vmx_get_test_stage()) { 1798 case 1: 1799 if (exit_reason.basic != VMX_VMCALL) { 1800 report_fail("VMEXIT not due to vmcall. Exit reason 0x%x", 1801 exit_reason.full); 1802 print_vmexit_info(exit_reason); 1803 return VMX_TEST_VMEXIT; 1804 } 1805 1806 vmcs_write(PIN_CONTROLS, 1807 vmcs_read(PIN_CONTROLS) | PIN_NMI); 1808 vmcs_write(PIN_CONTROLS, 1809 vmcs_read(PIN_CONTROLS) | PIN_VIRT_NMI); 1810 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1811 break; 1812 1813 case 2: 1814 if (exit_reason.basic != VMX_EXC_NMI) { 1815 report_fail("VMEXIT not due to NMI intercept. Exit reason 0x%x", 1816 exit_reason.full); 1817 print_vmexit_info(exit_reason); 1818 return VMX_TEST_VMEXIT; 1819 } 1820 report_pass("NMI intercept while running guest"); 1821 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 1822 break; 1823 1824 case 3: 1825 break; 1826 1827 default: 1828 return VMX_TEST_VMEXIT; 1829 } 1830 1831 if (vmx_get_test_stage() == 3) 1832 return VMX_TEST_VMEXIT; 1833 1834 return VMX_TEST_RESUME; 1835 } 1836 1837 1838 static int dbgctls_init(struct vmcs *vmcs) 1839 { 1840 u64 dr7 = 0x402; 1841 u64 zero = 0; 1842 1843 msr_bmp_init(); 1844 asm volatile( 1845 "mov %0,%%dr0\n\t" 1846 "mov %0,%%dr1\n\t" 1847 "mov %0,%%dr2\n\t" 1848 "mov %1,%%dr7\n\t" 1849 : : "r" (zero), "r" (dr7)); 1850 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1851 vmcs_write(GUEST_DR7, 0x404); 1852 vmcs_write(GUEST_DEBUGCTL, 0x2); 1853 1854 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 1855 vmcs_write(EXI_CONTROLS, vmcs_read(EXI_CONTROLS) | EXI_SAVE_DBGCTLS); 1856 1857 return VMX_TEST_START; 1858 } 1859 1860 static void dbgctls_main(void) 1861 { 1862 u64 dr7, debugctl; 1863 1864 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1865 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1866 /* Commented out: KVM does not support DEBUGCTL so far */ 1867 (void)debugctl; 1868 report(dr7 == 0x404, "Load debug controls" /* && debugctl == 0x2 */); 1869 1870 dr7 = 0x408; 1871 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1872 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1873 1874 vmx_set_test_stage(0); 1875 vmcall(); 1876 report(vmx_get_test_stage() == 1, "Save debug controls"); 1877 1878 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS || 1879 ctrl_exit_rev.set & EXI_SAVE_DBGCTLS) { 1880 printf("\tDebug controls are always loaded/saved\n"); 1881 return; 1882 } 1883 vmx_set_test_stage(2); 1884 vmcall(); 1885 1886 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1887 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1888 /* Commented out: KVM does not support DEBUGCTL so far */ 1889 (void)debugctl; 1890 report(dr7 == 0x402, 1891 "Guest=host debug controls" /* && debugctl == 0x1 */); 1892 1893 dr7 = 0x408; 1894 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1895 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x3); 1896 1897 vmx_set_test_stage(3); 1898 vmcall(); 1899 report(vmx_get_test_stage() == 4, "Don't save debug controls"); 1900 } 1901 1902 static int dbgctls_exit_handler(union exit_reason exit_reason) 1903 { 1904 u32 insn_len = vmcs_read(EXI_INST_LEN); 1905 u64 guest_rip = vmcs_read(GUEST_RIP); 1906 u64 dr7, debugctl; 1907 1908 asm volatile("mov %%dr7,%0" : "=r" (dr7)); 1909 debugctl = rdmsr(MSR_IA32_DEBUGCTLMSR); 1910 1911 switch (exit_reason.basic) { 1912 case VMX_VMCALL: 1913 switch (vmx_get_test_stage()) { 1914 case 0: 1915 if (dr7 == 0x400 && debugctl == 0 && 1916 vmcs_read(GUEST_DR7) == 0x408 /* && 1917 Commented out: KVM does not support DEBUGCTL so far 1918 vmcs_read(GUEST_DEBUGCTL) == 0x3 */) 1919 vmx_inc_test_stage(); 1920 break; 1921 case 2: 1922 dr7 = 0x402; 1923 asm volatile("mov %0,%%dr7" : : "r" (dr7)); 1924 wrmsr(MSR_IA32_DEBUGCTLMSR, 0x1); 1925 vmcs_write(GUEST_DR7, 0x404); 1926 vmcs_write(GUEST_DEBUGCTL, 0x2); 1927 1928 vmcs_write(ENT_CONTROLS, 1929 vmcs_read(ENT_CONTROLS) & ~ENT_LOAD_DBGCTLS); 1930 vmcs_write(EXI_CONTROLS, 1931 vmcs_read(EXI_CONTROLS) & ~EXI_SAVE_DBGCTLS); 1932 break; 1933 case 3: 1934 if (dr7 == 0x400 && debugctl == 0 && 1935 vmcs_read(GUEST_DR7) == 0x404 /* && 1936 Commented out: KVM does not support DEBUGCTL so far 1937 vmcs_read(GUEST_DEBUGCTL) == 0x2 */) 1938 vmx_inc_test_stage(); 1939 break; 1940 } 1941 vmcs_write(GUEST_RIP, guest_rip + insn_len); 1942 return VMX_TEST_RESUME; 1943 default: 1944 report_fail("Unknown exit reason, %d", exit_reason.full); 1945 print_vmexit_info(exit_reason); 1946 } 1947 return VMX_TEST_VMEXIT; 1948 } 1949 1950 struct vmx_msr_entry { 1951 u32 index; 1952 u32 reserved; 1953 u64 value; 1954 } __attribute__((packed)); 1955 1956 #define MSR_MAGIC 0x31415926 1957 struct vmx_msr_entry *exit_msr_store, *entry_msr_load, *exit_msr_load; 1958 1959 static int msr_switch_init(struct vmcs *vmcs) 1960 { 1961 msr_bmp_init(); 1962 exit_msr_store = alloc_page(); 1963 exit_msr_load = alloc_page(); 1964 entry_msr_load = alloc_page(); 1965 entry_msr_load[0].index = MSR_KERNEL_GS_BASE; 1966 entry_msr_load[0].value = MSR_MAGIC; 1967 1968 vmx_set_test_stage(1); 1969 vmcs_write(ENT_MSR_LD_CNT, 1); 1970 vmcs_write(ENTER_MSR_LD_ADDR, (u64)entry_msr_load); 1971 vmcs_write(EXI_MSR_ST_CNT, 1); 1972 vmcs_write(EXIT_MSR_ST_ADDR, (u64)exit_msr_store); 1973 vmcs_write(EXI_MSR_LD_CNT, 1); 1974 vmcs_write(EXIT_MSR_LD_ADDR, (u64)exit_msr_load); 1975 return VMX_TEST_START; 1976 } 1977 1978 static void msr_switch_main(void) 1979 { 1980 if (vmx_get_test_stage() == 1) { 1981 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC, 1982 "VM entry MSR load"); 1983 vmx_set_test_stage(2); 1984 wrmsr(MSR_KERNEL_GS_BASE, MSR_MAGIC + 1); 1985 exit_msr_store[0].index = MSR_KERNEL_GS_BASE; 1986 exit_msr_load[0].index = MSR_KERNEL_GS_BASE; 1987 exit_msr_load[0].value = MSR_MAGIC + 2; 1988 } 1989 vmcall(); 1990 } 1991 1992 static int msr_switch_exit_handler(union exit_reason exit_reason) 1993 { 1994 if (exit_reason.basic == VMX_VMCALL && vmx_get_test_stage() == 2) { 1995 report(exit_msr_store[0].value == MSR_MAGIC + 1, 1996 "VM exit MSR store"); 1997 report(rdmsr(MSR_KERNEL_GS_BASE) == MSR_MAGIC + 2, 1998 "VM exit MSR load"); 1999 vmx_set_test_stage(3); 2000 entry_msr_load[0].index = MSR_FS_BASE; 2001 return VMX_TEST_RESUME; 2002 } 2003 printf("ERROR %s: unexpected stage=%u or reason=0x%x\n", 2004 __func__, vmx_get_test_stage(), exit_reason.full); 2005 return VMX_TEST_EXIT; 2006 } 2007 2008 static int msr_switch_entry_failure(struct vmentry_result *result) 2009 { 2010 if (result->vm_fail) { 2011 printf("ERROR %s: VM-Fail on %s\n", __func__, result->instr); 2012 return VMX_TEST_EXIT; 2013 } 2014 2015 if (result->exit_reason.failed_vmentry && 2016 result->exit_reason.basic == VMX_FAIL_MSR && 2017 vmx_get_test_stage() == 3) { 2018 report(vmcs_read(EXI_QUALIFICATION) == 1, 2019 "VM entry MSR load: try to load FS_BASE"); 2020 return VMX_TEST_VMEXIT; 2021 } 2022 printf("ERROR %s: unexpected stage=%u or reason=%x\n", 2023 __func__, vmx_get_test_stage(), result->exit_reason.full); 2024 return VMX_TEST_EXIT; 2025 } 2026 2027 static int vmmcall_init(struct vmcs *vmcs) 2028 { 2029 vmcs_write(EXC_BITMAP, 1 << UD_VECTOR); 2030 return VMX_TEST_START; 2031 } 2032 2033 static void vmmcall_main(void) 2034 { 2035 asm volatile( 2036 "mov $0xABCD, %%rax\n\t" 2037 "vmmcall\n\t" 2038 ::: "rax"); 2039 2040 report_fail("VMMCALL"); 2041 } 2042 2043 static int vmmcall_exit_handler(union exit_reason exit_reason) 2044 { 2045 switch (exit_reason.basic) { 2046 case VMX_VMCALL: 2047 printf("here\n"); 2048 report_fail("VMMCALL triggers #UD"); 2049 break; 2050 case VMX_EXC_NMI: 2051 report((vmcs_read(EXI_INTR_INFO) & 0xff) == UD_VECTOR, 2052 "VMMCALL triggers #UD"); 2053 break; 2054 default: 2055 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2056 print_vmexit_info(exit_reason); 2057 } 2058 2059 return VMX_TEST_VMEXIT; 2060 } 2061 2062 static int disable_rdtscp_init(struct vmcs *vmcs) 2063 { 2064 u32 ctrl_cpu1; 2065 2066 if (ctrl_cpu_rev[0].clr & CPU_SECONDARY) { 2067 ctrl_cpu1 = vmcs_read(CPU_EXEC_CTRL1); 2068 ctrl_cpu1 &= ~CPU_RDTSCP; 2069 vmcs_write(CPU_EXEC_CTRL1, ctrl_cpu1); 2070 } 2071 2072 return VMX_TEST_START; 2073 } 2074 2075 static void disable_rdtscp_ud_handler(struct ex_regs *regs) 2076 { 2077 switch (vmx_get_test_stage()) { 2078 case 0: 2079 report_pass("RDTSCP triggers #UD"); 2080 vmx_inc_test_stage(); 2081 regs->rip += 3; 2082 break; 2083 case 2: 2084 report_pass("RDPID triggers #UD"); 2085 vmx_inc_test_stage(); 2086 regs->rip += 4; 2087 break; 2088 } 2089 return; 2090 2091 } 2092 2093 static void disable_rdtscp_main(void) 2094 { 2095 /* Test that #UD is properly injected in L2. */ 2096 handle_exception(UD_VECTOR, disable_rdtscp_ud_handler); 2097 2098 vmx_set_test_stage(0); 2099 asm volatile("rdtscp" : : : "eax", "ecx", "edx"); 2100 vmcall(); 2101 asm volatile(".byte 0xf3, 0x0f, 0xc7, 0xf8" : : : "eax"); 2102 2103 handle_exception(UD_VECTOR, 0); 2104 vmcall(); 2105 } 2106 2107 static int disable_rdtscp_exit_handler(union exit_reason exit_reason) 2108 { 2109 switch (exit_reason.basic) { 2110 case VMX_VMCALL: 2111 switch (vmx_get_test_stage()) { 2112 case 0: 2113 report_fail("RDTSCP triggers #UD"); 2114 vmx_inc_test_stage(); 2115 /* fallthrough */ 2116 case 1: 2117 vmx_inc_test_stage(); 2118 vmcs_write(GUEST_RIP, vmcs_read(GUEST_RIP) + 3); 2119 return VMX_TEST_RESUME; 2120 case 2: 2121 report_fail("RDPID triggers #UD"); 2122 break; 2123 } 2124 break; 2125 2126 default: 2127 report_fail("Unknown exit reason, 0x%x", exit_reason.full); 2128 print_vmexit_info(exit_reason); 2129 } 2130 return VMX_TEST_VMEXIT; 2131 } 2132 2133 static int int3_init(struct vmcs *vmcs) 2134 { 2135 vmcs_write(EXC_BITMAP, ~0u); 2136 return VMX_TEST_START; 2137 } 2138 2139 static void int3_guest_main(void) 2140 { 2141 asm volatile ("int3"); 2142 } 2143 2144 static int int3_exit_handler(union exit_reason exit_reason) 2145 { 2146 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2147 2148 report(exit_reason.basic == VMX_EXC_NMI && 2149 (intr_info & INTR_INFO_VALID_MASK) && 2150 (intr_info & INTR_INFO_VECTOR_MASK) == BP_VECTOR && 2151 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2152 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2153 "L1 intercepts #BP"); 2154 2155 return VMX_TEST_VMEXIT; 2156 } 2157 2158 static int into_init(struct vmcs *vmcs) 2159 { 2160 vmcs_write(EXC_BITMAP, ~0u); 2161 return VMX_TEST_START; 2162 } 2163 2164 static void into_guest_main(void) 2165 { 2166 struct far_pointer32 fp = { 2167 .offset = (uintptr_t)&&into, 2168 .selector = KERNEL_CS32, 2169 }; 2170 uintptr_t rsp; 2171 2172 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 2173 2174 if (fp.offset != (uintptr_t)&&into) { 2175 printf("Code address too high.\n"); 2176 return; 2177 } 2178 if ((u32)rsp != rsp) { 2179 printf("Stack address too high.\n"); 2180 return; 2181 } 2182 2183 asm goto ("lcall *%0" : : "m" (fp) : "rax" : into); 2184 return; 2185 into: 2186 asm volatile (".code32;" 2187 "movl $0x7fffffff, %eax;" 2188 "addl %eax, %eax;" 2189 "into;" 2190 "lret;" 2191 ".code64"); 2192 __builtin_unreachable(); 2193 } 2194 2195 static int into_exit_handler(union exit_reason exit_reason) 2196 { 2197 u32 intr_info = vmcs_read(EXI_INTR_INFO); 2198 2199 report(exit_reason.basic == VMX_EXC_NMI && 2200 (intr_info & INTR_INFO_VALID_MASK) && 2201 (intr_info & INTR_INFO_VECTOR_MASK) == OF_VECTOR && 2202 ((intr_info & INTR_INFO_INTR_TYPE_MASK) >> 2203 INTR_INFO_INTR_TYPE_SHIFT) == VMX_INTR_TYPE_SOFT_EXCEPTION, 2204 "L1 intercepts #OF"); 2205 2206 return VMX_TEST_VMEXIT; 2207 } 2208 2209 static void exit_monitor_from_l2_main(void) 2210 { 2211 printf("Calling exit(0) from l2...\n"); 2212 exit(0); 2213 } 2214 2215 static int exit_monitor_from_l2_handler(union exit_reason exit_reason) 2216 { 2217 report_fail("The guest should have killed the VMM"); 2218 return VMX_TEST_EXIT; 2219 } 2220 2221 static void assert_exit_reason(u64 expected) 2222 { 2223 u64 actual = vmcs_read(EXI_REASON); 2224 2225 TEST_ASSERT_EQ_MSG(expected, actual, "Expected %s, got %s.", 2226 exit_reason_description(expected), 2227 exit_reason_description(actual)); 2228 } 2229 2230 static void skip_exit_insn(void) 2231 { 2232 u64 guest_rip = vmcs_read(GUEST_RIP); 2233 u32 insn_len = vmcs_read(EXI_INST_LEN); 2234 vmcs_write(GUEST_RIP, guest_rip + insn_len); 2235 } 2236 2237 static void skip_exit_vmcall(void) 2238 { 2239 assert_exit_reason(VMX_VMCALL); 2240 skip_exit_insn(); 2241 } 2242 2243 static void v2_null_test_guest(void) 2244 { 2245 } 2246 2247 static void v2_null_test(void) 2248 { 2249 test_set_guest(v2_null_test_guest); 2250 enter_guest(); 2251 report_pass(__func__); 2252 } 2253 2254 static void v2_multiple_entries_test_guest(void) 2255 { 2256 vmx_set_test_stage(1); 2257 vmcall(); 2258 vmx_set_test_stage(2); 2259 } 2260 2261 static void v2_multiple_entries_test(void) 2262 { 2263 test_set_guest(v2_multiple_entries_test_guest); 2264 enter_guest(); 2265 TEST_ASSERT_EQ(vmx_get_test_stage(), 1); 2266 skip_exit_vmcall(); 2267 enter_guest(); 2268 TEST_ASSERT_EQ(vmx_get_test_stage(), 2); 2269 report_pass(__func__); 2270 } 2271 2272 static int fixture_test_data = 1; 2273 2274 static void fixture_test_teardown(void *data) 2275 { 2276 *((int *) data) = 1; 2277 } 2278 2279 static void fixture_test_guest(void) 2280 { 2281 fixture_test_data++; 2282 } 2283 2284 2285 static void fixture_test_setup(void) 2286 { 2287 TEST_ASSERT_EQ_MSG(1, fixture_test_data, 2288 "fixture_test_teardown didn't run?!"); 2289 fixture_test_data = 2; 2290 test_add_teardown(fixture_test_teardown, &fixture_test_data); 2291 test_set_guest(fixture_test_guest); 2292 } 2293 2294 static void fixture_test_case1(void) 2295 { 2296 fixture_test_setup(); 2297 TEST_ASSERT_EQ(2, fixture_test_data); 2298 enter_guest(); 2299 TEST_ASSERT_EQ(3, fixture_test_data); 2300 report_pass(__func__); 2301 } 2302 2303 static void fixture_test_case2(void) 2304 { 2305 fixture_test_setup(); 2306 TEST_ASSERT_EQ(2, fixture_test_data); 2307 enter_guest(); 2308 TEST_ASSERT_EQ(3, fixture_test_data); 2309 report_pass(__func__); 2310 } 2311 2312 enum ept_access_op { 2313 OP_READ, 2314 OP_WRITE, 2315 OP_EXEC, 2316 OP_FLUSH_TLB, 2317 OP_EXIT, 2318 }; 2319 2320 static struct ept_access_test_data { 2321 unsigned long gpa; 2322 unsigned long *gva; 2323 unsigned long hpa; 2324 unsigned long *hva; 2325 enum ept_access_op op; 2326 } ept_access_test_data; 2327 2328 extern unsigned char ret42_start; 2329 extern unsigned char ret42_end; 2330 2331 /* Returns 42. */ 2332 asm( 2333 ".align 64\n" 2334 "ret42_start:\n" 2335 "mov $42, %eax\n" 2336 "ret\n" 2337 "ret42_end:\n" 2338 ); 2339 2340 static void 2341 diagnose_ept_violation_qual(u64 expected, u64 actual) 2342 { 2343 2344 #define DIAGNOSE(flag) \ 2345 do { \ 2346 if ((expected & flag) != (actual & flag)) \ 2347 printf(#flag " %sexpected\n", \ 2348 (expected & flag) ? "" : "un"); \ 2349 } while (0) 2350 2351 DIAGNOSE(EPT_VLT_RD); 2352 DIAGNOSE(EPT_VLT_WR); 2353 DIAGNOSE(EPT_VLT_FETCH); 2354 DIAGNOSE(EPT_VLT_PERM_RD); 2355 DIAGNOSE(EPT_VLT_PERM_WR); 2356 DIAGNOSE(EPT_VLT_PERM_EX); 2357 DIAGNOSE(EPT_VLT_LADDR_VLD); 2358 DIAGNOSE(EPT_VLT_PADDR); 2359 2360 #undef DIAGNOSE 2361 } 2362 2363 static void do_ept_access_op(enum ept_access_op op) 2364 { 2365 ept_access_test_data.op = op; 2366 enter_guest(); 2367 } 2368 2369 /* 2370 * Force the guest to flush its TLB (i.e., flush gva -> gpa mappings). Only 2371 * needed by tests that modify guest PTEs. 2372 */ 2373 static void ept_access_test_guest_flush_tlb(void) 2374 { 2375 do_ept_access_op(OP_FLUSH_TLB); 2376 skip_exit_vmcall(); 2377 } 2378 2379 /* 2380 * Modifies the EPT entry at @level in the mapping of @gpa. First clears the 2381 * bits in @clear then sets the bits in @set. @mkhuge transforms the entry into 2382 * a huge page. 2383 */ 2384 static unsigned long ept_twiddle(unsigned long gpa, bool mkhuge, int level, 2385 unsigned long clear, unsigned long set) 2386 { 2387 struct ept_access_test_data *data = &ept_access_test_data; 2388 unsigned long orig_pte; 2389 unsigned long pte; 2390 2391 /* Screw with the mapping at the requested level. */ 2392 TEST_ASSERT(get_ept_pte(pml4, gpa, level, &orig_pte)); 2393 pte = orig_pte; 2394 if (mkhuge) 2395 pte = (orig_pte & ~EPT_ADDR_MASK) | data->hpa | EPT_LARGE_PAGE; 2396 else 2397 pte = orig_pte; 2398 pte = (pte & ~clear) | set; 2399 set_ept_pte(pml4, gpa, level, pte); 2400 invept(INVEPT_SINGLE, eptp); 2401 2402 return orig_pte; 2403 } 2404 2405 static void ept_untwiddle(unsigned long gpa, int level, unsigned long orig_pte) 2406 { 2407 set_ept_pte(pml4, gpa, level, orig_pte); 2408 invept(INVEPT_SINGLE, eptp); 2409 } 2410 2411 static void do_ept_violation(bool leaf, enum ept_access_op op, 2412 u64 expected_qual, u64 expected_paddr) 2413 { 2414 u64 qual; 2415 2416 /* Try the access and observe the violation. */ 2417 do_ept_access_op(op); 2418 2419 assert_exit_reason(VMX_EPT_VIOLATION); 2420 2421 qual = vmcs_read(EXI_QUALIFICATION); 2422 2423 /* Mask undefined bits (which may later be defined in certain cases). */ 2424 qual &= ~(EPT_VLT_GUEST_USER | EPT_VLT_GUEST_RW | EPT_VLT_GUEST_EX | 2425 EPT_VLT_PERM_USER_EX); 2426 2427 diagnose_ept_violation_qual(expected_qual, qual); 2428 TEST_EXPECT_EQ(expected_qual, qual); 2429 2430 #if 0 2431 /* Disable for now otherwise every test will fail */ 2432 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2433 (unsigned long) ( 2434 op == OP_EXEC ? data->gva + 1 : data->gva)); 2435 #endif 2436 /* 2437 * TODO: tests that probe expected_paddr in pages other than the one at 2438 * the beginning of the 1g region. 2439 */ 2440 TEST_EXPECT_EQ(vmcs_read(INFO_PHYS_ADDR), expected_paddr); 2441 } 2442 2443 static void 2444 ept_violation_at_level_mkhuge(bool mkhuge, int level, unsigned long clear, 2445 unsigned long set, enum ept_access_op op, 2446 u64 expected_qual) 2447 { 2448 struct ept_access_test_data *data = &ept_access_test_data; 2449 unsigned long orig_pte; 2450 2451 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2452 2453 do_ept_violation(level == 1 || mkhuge, op, expected_qual, 2454 op == OP_EXEC ? data->gpa + sizeof(unsigned long) : 2455 data->gpa); 2456 2457 /* Fix the violation and resume the op loop. */ 2458 ept_untwiddle(data->gpa, level, orig_pte); 2459 enter_guest(); 2460 skip_exit_vmcall(); 2461 } 2462 2463 static void 2464 ept_violation_at_level(int level, unsigned long clear, unsigned long set, 2465 enum ept_access_op op, u64 expected_qual) 2466 { 2467 ept_violation_at_level_mkhuge(false, level, clear, set, op, 2468 expected_qual); 2469 if (ept_huge_pages_supported(level)) 2470 ept_violation_at_level_mkhuge(true, level, clear, set, op, 2471 expected_qual); 2472 } 2473 2474 static void ept_violation(unsigned long clear, unsigned long set, 2475 enum ept_access_op op, u64 expected_qual) 2476 { 2477 ept_violation_at_level(1, clear, set, op, expected_qual); 2478 ept_violation_at_level(2, clear, set, op, expected_qual); 2479 ept_violation_at_level(3, clear, set, op, expected_qual); 2480 ept_violation_at_level(4, clear, set, op, expected_qual); 2481 } 2482 2483 static void ept_access_violation(unsigned long access, enum ept_access_op op, 2484 u64 expected_qual) 2485 { 2486 ept_violation(EPT_PRESENT, access, op, 2487 expected_qual | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2488 } 2489 2490 /* 2491 * For translations that don't involve a GVA, that is physical address (paddr) 2492 * accesses, EPT violations don't set the flag EPT_VLT_PADDR. For a typical 2493 * guest memory access, the hardware does GVA -> GPA -> HPA. However, certain 2494 * translations don't involve GVAs, such as when the hardware does the guest 2495 * page table walk. For example, in translating GVA_1 -> GPA_1, the guest MMU 2496 * might try to set an A bit on a guest PTE. If the GPA_2 that the PTE resides 2497 * on isn't present in the EPT, then the EPT violation will be for GPA_2 and 2498 * the EPT_VLT_PADDR bit will be clear in the exit qualification. 2499 * 2500 * Note that paddr violations can also be triggered by loading PAE page tables 2501 * with wonky addresses. We don't test that yet. 2502 * 2503 * This function modifies the EPT entry that maps the GPA that the guest page 2504 * table entry mapping ept_access_test_data.gva resides on. 2505 * 2506 * @ept_access EPT permissions to set. Other permissions are cleared. 2507 * 2508 * @pte_ad Set the A/D bits on the guest PTE accordingly. 2509 * 2510 * @op Guest operation to perform with 2511 * ept_access_test_data.gva. 2512 * 2513 * @expect_violation 2514 * Is a violation expected during the paddr access? 2515 * 2516 * @expected_qual Expected qualification for the EPT violation. 2517 * EPT_VLT_PADDR should be clear. 2518 */ 2519 static void ept_access_paddr(unsigned long ept_access, unsigned long pte_ad, 2520 enum ept_access_op op, bool expect_violation, 2521 u64 expected_qual) 2522 { 2523 struct ept_access_test_data *data = &ept_access_test_data; 2524 unsigned long *ptep; 2525 unsigned long gpa; 2526 unsigned long orig_epte; 2527 unsigned long epte; 2528 int i; 2529 2530 /* Modify the guest PTE mapping data->gva according to @pte_ad. */ 2531 ptep = get_pte_level(current_page_table(), data->gva, /*level=*/1); 2532 TEST_ASSERT(ptep); 2533 TEST_ASSERT_EQ(*ptep & PT_ADDR_MASK, data->gpa); 2534 *ptep = (*ptep & ~PT_AD_MASK) | pte_ad; 2535 ept_access_test_guest_flush_tlb(); 2536 2537 /* 2538 * Now modify the access bits on the EPT entry for the GPA that the 2539 * guest PTE resides on. Note that by modifying a single EPT entry, 2540 * we're potentially affecting 512 guest PTEs. However, we've carefully 2541 * constructed our test such that those other 511 PTEs aren't used by 2542 * the guest: data->gva is at the beginning of a 1G huge page, thus the 2543 * PTE we're modifying is at the beginning of a 4K page and the 2544 * following 511 entires are also under our control (and not touched by 2545 * the guest). 2546 */ 2547 gpa = virt_to_phys(ptep); 2548 TEST_ASSERT_EQ(gpa & ~PAGE_MASK, 0); 2549 /* 2550 * Make sure the guest page table page is mapped with a 4K EPT entry, 2551 * otherwise our level=1 twiddling below will fail. We use the 2552 * identity map (gpa = gpa) since page tables are shared with the host. 2553 */ 2554 install_ept(pml4, gpa, gpa, EPT_PRESENT); 2555 orig_epte = ept_twiddle(gpa, /*mkhuge=*/0, /*level=*/1, 2556 /*clear=*/EPT_PRESENT, /*set=*/ept_access); 2557 2558 if (expect_violation) { 2559 do_ept_violation(/*leaf=*/true, op, 2560 expected_qual | EPT_VLT_LADDR_VLD, gpa); 2561 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2562 do_ept_access_op(op); 2563 } else { 2564 do_ept_access_op(op); 2565 if (ept_ad_enabled()) { 2566 for (i = EPT_PAGE_LEVEL; i > 0; i--) { 2567 TEST_ASSERT(get_ept_pte(pml4, gpa, i, &epte)); 2568 TEST_ASSERT(epte & EPT_ACCESS_FLAG); 2569 if (i == 1) 2570 TEST_ASSERT(epte & EPT_DIRTY_FLAG); 2571 else 2572 TEST_ASSERT_EQ(epte & EPT_DIRTY_FLAG, 0); 2573 } 2574 } 2575 2576 ept_untwiddle(gpa, /*level=*/1, orig_epte); 2577 } 2578 2579 TEST_ASSERT(*ptep & PT_ACCESSED_MASK); 2580 if ((pte_ad & PT_DIRTY_MASK) || op == OP_WRITE) 2581 TEST_ASSERT(*ptep & PT_DIRTY_MASK); 2582 2583 skip_exit_vmcall(); 2584 } 2585 2586 static void ept_access_allowed_paddr(unsigned long ept_access, 2587 unsigned long pte_ad, 2588 enum ept_access_op op) 2589 { 2590 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/false, 2591 /*expected_qual=*/-1); 2592 } 2593 2594 static void ept_access_violation_paddr(unsigned long ept_access, 2595 unsigned long pte_ad, 2596 enum ept_access_op op, 2597 u64 expected_qual) 2598 { 2599 ept_access_paddr(ept_access, pte_ad, op, /*expect_violation=*/true, 2600 expected_qual); 2601 } 2602 2603 2604 static void ept_allowed_at_level_mkhuge(bool mkhuge, int level, 2605 unsigned long clear, 2606 unsigned long set, 2607 enum ept_access_op op) 2608 { 2609 struct ept_access_test_data *data = &ept_access_test_data; 2610 unsigned long orig_pte; 2611 2612 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2613 2614 /* No violation. Should proceed to vmcall. */ 2615 do_ept_access_op(op); 2616 skip_exit_vmcall(); 2617 2618 ept_untwiddle(data->gpa, level, orig_pte); 2619 } 2620 2621 static void ept_allowed_at_level(int level, unsigned long clear, 2622 unsigned long set, enum ept_access_op op) 2623 { 2624 ept_allowed_at_level_mkhuge(false, level, clear, set, op); 2625 if (ept_huge_pages_supported(level)) 2626 ept_allowed_at_level_mkhuge(true, level, clear, set, op); 2627 } 2628 2629 static void ept_allowed(unsigned long clear, unsigned long set, 2630 enum ept_access_op op) 2631 { 2632 ept_allowed_at_level(1, clear, set, op); 2633 ept_allowed_at_level(2, clear, set, op); 2634 ept_allowed_at_level(3, clear, set, op); 2635 ept_allowed_at_level(4, clear, set, op); 2636 } 2637 2638 static void ept_ignored_bit(int bit) 2639 { 2640 /* Set the bit. */ 2641 ept_allowed(0, 1ul << bit, OP_READ); 2642 ept_allowed(0, 1ul << bit, OP_WRITE); 2643 ept_allowed(0, 1ul << bit, OP_EXEC); 2644 2645 /* Clear the bit. */ 2646 ept_allowed(1ul << bit, 0, OP_READ); 2647 ept_allowed(1ul << bit, 0, OP_WRITE); 2648 ept_allowed(1ul << bit, 0, OP_EXEC); 2649 } 2650 2651 static void ept_access_allowed(unsigned long access, enum ept_access_op op) 2652 { 2653 ept_allowed(EPT_PRESENT, access, op); 2654 } 2655 2656 2657 static void ept_misconfig_at_level_mkhuge_op(bool mkhuge, int level, 2658 unsigned long clear, 2659 unsigned long set, 2660 enum ept_access_op op) 2661 { 2662 struct ept_access_test_data *data = &ept_access_test_data; 2663 unsigned long orig_pte; 2664 2665 orig_pte = ept_twiddle(data->gpa, mkhuge, level, clear, set); 2666 2667 do_ept_access_op(op); 2668 assert_exit_reason(VMX_EPT_MISCONFIG); 2669 2670 /* Intel 27.2.1, "For all other VM exits, this field is cleared." */ 2671 #if 0 2672 /* broken: */ 2673 TEST_EXPECT_EQ_MSG(vmcs_read(EXI_QUALIFICATION), 0); 2674 #endif 2675 #if 0 2676 /* 2677 * broken: 2678 * According to description of exit qual for EPT violation, 2679 * EPT_VLT_LADDR_VLD indicates if GUEST_LINEAR_ADDRESS is valid. 2680 * However, I can't find anything that says GUEST_LINEAR_ADDRESS ought 2681 * to be set for msiconfig. 2682 */ 2683 TEST_EXPECT_EQ(vmcs_read(GUEST_LINEAR_ADDRESS), 2684 (unsigned long) ( 2685 op == OP_EXEC ? data->gva + 1 : data->gva)); 2686 #endif 2687 2688 /* Fix the violation and resume the op loop. */ 2689 ept_untwiddle(data->gpa, level, orig_pte); 2690 enter_guest(); 2691 skip_exit_vmcall(); 2692 } 2693 2694 static void ept_misconfig_at_level_mkhuge(bool mkhuge, int level, 2695 unsigned long clear, 2696 unsigned long set) 2697 { 2698 /* The op shouldn't matter (read, write, exec), so try them all! */ 2699 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_READ); 2700 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_WRITE); 2701 ept_misconfig_at_level_mkhuge_op(mkhuge, level, clear, set, OP_EXEC); 2702 } 2703 2704 static void ept_misconfig_at_level(int level, unsigned long clear, 2705 unsigned long set) 2706 { 2707 ept_misconfig_at_level_mkhuge(false, level, clear, set); 2708 if (ept_huge_pages_supported(level)) 2709 ept_misconfig_at_level_mkhuge(true, level, clear, set); 2710 } 2711 2712 static void ept_misconfig(unsigned long clear, unsigned long set) 2713 { 2714 ept_misconfig_at_level(1, clear, set); 2715 ept_misconfig_at_level(2, clear, set); 2716 ept_misconfig_at_level(3, clear, set); 2717 ept_misconfig_at_level(4, clear, set); 2718 } 2719 2720 static void ept_access_misconfig(unsigned long access) 2721 { 2722 ept_misconfig(EPT_PRESENT, access); 2723 } 2724 2725 static void ept_reserved_bit_at_level_nohuge(int level, int bit) 2726 { 2727 /* Setting the bit causes a misconfig. */ 2728 ept_misconfig_at_level_mkhuge(false, level, 0, 1ul << bit); 2729 2730 /* Making the entry non-present turns reserved bits into ignored. */ 2731 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2732 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2733 } 2734 2735 static void ept_reserved_bit_at_level_huge(int level, int bit) 2736 { 2737 /* Setting the bit causes a misconfig. */ 2738 ept_misconfig_at_level_mkhuge(true, level, 0, 1ul << bit); 2739 2740 /* Making the entry non-present turns reserved bits into ignored. */ 2741 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2742 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2743 } 2744 2745 static void ept_reserved_bit_at_level(int level, int bit) 2746 { 2747 /* Setting the bit causes a misconfig. */ 2748 ept_misconfig_at_level(level, 0, 1ul << bit); 2749 2750 /* Making the entry non-present turns reserved bits into ignored. */ 2751 ept_violation_at_level(level, EPT_PRESENT, 1ul << bit, OP_READ, 2752 EPT_VLT_RD | EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 2753 } 2754 2755 static void ept_reserved_bit(int bit) 2756 { 2757 ept_reserved_bit_at_level(1, bit); 2758 ept_reserved_bit_at_level(2, bit); 2759 ept_reserved_bit_at_level(3, bit); 2760 ept_reserved_bit_at_level(4, bit); 2761 } 2762 2763 #define PAGE_2M_ORDER 9 2764 #define PAGE_1G_ORDER 18 2765 2766 static void *get_1g_page(void) 2767 { 2768 static void *alloc; 2769 2770 if (!alloc) 2771 alloc = alloc_pages(PAGE_1G_ORDER); 2772 return alloc; 2773 } 2774 2775 static void ept_access_test_teardown(void *unused) 2776 { 2777 /* Exit the guest cleanly. */ 2778 do_ept_access_op(OP_EXIT); 2779 } 2780 2781 static void ept_access_test_guest(void) 2782 { 2783 struct ept_access_test_data *data = &ept_access_test_data; 2784 int (*code)(void) = (int (*)(void)) &data->gva[1]; 2785 2786 while (true) { 2787 switch (data->op) { 2788 case OP_READ: 2789 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_1); 2790 break; 2791 case OP_WRITE: 2792 *data->gva = MAGIC_VAL_2; 2793 TEST_ASSERT_EQ(*data->gva, MAGIC_VAL_2); 2794 *data->gva = MAGIC_VAL_1; 2795 break; 2796 case OP_EXEC: 2797 TEST_ASSERT_EQ(42, code()); 2798 break; 2799 case OP_FLUSH_TLB: 2800 write_cr3(read_cr3()); 2801 break; 2802 case OP_EXIT: 2803 return; 2804 default: 2805 TEST_ASSERT_MSG(false, "Unknown op %d", data->op); 2806 } 2807 vmcall(); 2808 } 2809 } 2810 2811 static void ept_access_test_setup(void) 2812 { 2813 struct ept_access_test_data *data = &ept_access_test_data; 2814 unsigned long npages = 1ul << PAGE_1G_ORDER; 2815 unsigned long size = npages * PAGE_SIZE; 2816 unsigned long *page_table = current_page_table(); 2817 unsigned long pte; 2818 2819 if (setup_ept(false)) 2820 test_skip("EPT not supported"); 2821 2822 /* We use data->gpa = 1 << 39 so that test data has a separate pml4 entry */ 2823 if (cpuid_maxphyaddr() < 40) 2824 test_skip("Test needs MAXPHYADDR >= 40"); 2825 2826 test_set_guest(ept_access_test_guest); 2827 test_add_teardown(ept_access_test_teardown, NULL); 2828 2829 data->hva = get_1g_page(); 2830 TEST_ASSERT(data->hva); 2831 data->hpa = virt_to_phys(data->hva); 2832 2833 data->gpa = 1ul << 39; 2834 data->gva = (void *) ALIGN((unsigned long) alloc_vpages(npages * 2), 2835 size); 2836 TEST_ASSERT(!any_present_pages(page_table, data->gva, size)); 2837 install_pages(page_table, data->gpa, size, data->gva); 2838 2839 /* 2840 * Make sure nothing's mapped here so the tests that screw with the 2841 * pml4 entry don't inadvertently break something. 2842 */ 2843 TEST_ASSERT(get_ept_pte(pml4, data->gpa, 4, &pte) && pte == 0); 2844 TEST_ASSERT(get_ept_pte(pml4, data->gpa + size - 1, 4, &pte) && pte == 0); 2845 install_ept(pml4, data->hpa, data->gpa, EPT_PRESENT); 2846 2847 data->hva[0] = MAGIC_VAL_1; 2848 memcpy(&data->hva[1], &ret42_start, &ret42_end - &ret42_start); 2849 } 2850 2851 static void ept_access_test_not_present(void) 2852 { 2853 ept_access_test_setup(); 2854 /* --- */ 2855 ept_access_violation(0, OP_READ, EPT_VLT_RD); 2856 ept_access_violation(0, OP_WRITE, EPT_VLT_WR); 2857 ept_access_violation(0, OP_EXEC, EPT_VLT_FETCH); 2858 } 2859 2860 static void ept_access_test_read_only(void) 2861 { 2862 ept_access_test_setup(); 2863 2864 /* r-- */ 2865 ept_access_allowed(EPT_RA, OP_READ); 2866 ept_access_violation(EPT_RA, OP_WRITE, EPT_VLT_WR | EPT_VLT_PERM_RD); 2867 ept_access_violation(EPT_RA, OP_EXEC, EPT_VLT_FETCH | EPT_VLT_PERM_RD); 2868 } 2869 2870 static void ept_access_test_write_only(void) 2871 { 2872 ept_access_test_setup(); 2873 /* -w- */ 2874 ept_access_misconfig(EPT_WA); 2875 } 2876 2877 static void ept_access_test_read_write(void) 2878 { 2879 ept_access_test_setup(); 2880 /* rw- */ 2881 ept_access_allowed(EPT_RA | EPT_WA, OP_READ); 2882 ept_access_allowed(EPT_RA | EPT_WA, OP_WRITE); 2883 ept_access_violation(EPT_RA | EPT_WA, OP_EXEC, 2884 EPT_VLT_FETCH | EPT_VLT_PERM_RD | EPT_VLT_PERM_WR); 2885 } 2886 2887 2888 static void ept_access_test_execute_only(void) 2889 { 2890 ept_access_test_setup(); 2891 /* --x */ 2892 if (ept_execute_only_supported()) { 2893 ept_access_violation(EPT_EA, OP_READ, 2894 EPT_VLT_RD | EPT_VLT_PERM_EX); 2895 ept_access_violation(EPT_EA, OP_WRITE, 2896 EPT_VLT_WR | EPT_VLT_PERM_EX); 2897 ept_access_allowed(EPT_EA, OP_EXEC); 2898 } else { 2899 ept_access_misconfig(EPT_EA); 2900 } 2901 } 2902 2903 static void ept_access_test_read_execute(void) 2904 { 2905 ept_access_test_setup(); 2906 /* r-x */ 2907 ept_access_allowed(EPT_RA | EPT_EA, OP_READ); 2908 ept_access_violation(EPT_RA | EPT_EA, OP_WRITE, 2909 EPT_VLT_WR | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX); 2910 ept_access_allowed(EPT_RA | EPT_EA, OP_EXEC); 2911 } 2912 2913 static void ept_access_test_write_execute(void) 2914 { 2915 ept_access_test_setup(); 2916 /* -wx */ 2917 ept_access_misconfig(EPT_WA | EPT_EA); 2918 } 2919 2920 static void ept_access_test_read_write_execute(void) 2921 { 2922 ept_access_test_setup(); 2923 /* rwx */ 2924 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_READ); 2925 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_WRITE); 2926 ept_access_allowed(EPT_RA | EPT_WA | EPT_EA, OP_EXEC); 2927 } 2928 2929 static void ept_access_test_reserved_bits(void) 2930 { 2931 int i; 2932 int maxphyaddr; 2933 2934 ept_access_test_setup(); 2935 2936 /* Reserved bits above maxphyaddr. */ 2937 maxphyaddr = cpuid_maxphyaddr(); 2938 for (i = maxphyaddr; i <= 51; i++) { 2939 report_prefix_pushf("reserved_bit=%d", i); 2940 ept_reserved_bit(i); 2941 report_prefix_pop(); 2942 } 2943 2944 /* Level-specific reserved bits. */ 2945 ept_reserved_bit_at_level_nohuge(2, 3); 2946 ept_reserved_bit_at_level_nohuge(2, 4); 2947 ept_reserved_bit_at_level_nohuge(2, 5); 2948 ept_reserved_bit_at_level_nohuge(2, 6); 2949 /* 2M alignment. */ 2950 for (i = 12; i < 20; i++) { 2951 report_prefix_pushf("reserved_bit=%d", i); 2952 ept_reserved_bit_at_level_huge(2, i); 2953 report_prefix_pop(); 2954 } 2955 ept_reserved_bit_at_level_nohuge(3, 3); 2956 ept_reserved_bit_at_level_nohuge(3, 4); 2957 ept_reserved_bit_at_level_nohuge(3, 5); 2958 ept_reserved_bit_at_level_nohuge(3, 6); 2959 /* 1G alignment. */ 2960 for (i = 12; i < 29; i++) { 2961 report_prefix_pushf("reserved_bit=%d", i); 2962 ept_reserved_bit_at_level_huge(3, i); 2963 report_prefix_pop(); 2964 } 2965 ept_reserved_bit_at_level(4, 3); 2966 ept_reserved_bit_at_level(4, 4); 2967 ept_reserved_bit_at_level(4, 5); 2968 ept_reserved_bit_at_level(4, 6); 2969 ept_reserved_bit_at_level(4, 7); 2970 } 2971 2972 static void ept_access_test_ignored_bits(void) 2973 { 2974 ept_access_test_setup(); 2975 /* 2976 * Bits ignored at every level. Bits 8 and 9 (A and D) are ignored as 2977 * far as translation is concerned even if AD bits are enabled in the 2978 * EPTP. Bit 63 is ignored because "EPT-violation #VE" VM-execution 2979 * control is 0. 2980 */ 2981 ept_ignored_bit(8); 2982 ept_ignored_bit(9); 2983 ept_ignored_bit(10); 2984 ept_ignored_bit(11); 2985 ept_ignored_bit(52); 2986 ept_ignored_bit(53); 2987 ept_ignored_bit(54); 2988 ept_ignored_bit(55); 2989 ept_ignored_bit(56); 2990 ept_ignored_bit(57); 2991 ept_ignored_bit(58); 2992 ept_ignored_bit(59); 2993 ept_ignored_bit(60); 2994 ept_ignored_bit(61); 2995 ept_ignored_bit(62); 2996 ept_ignored_bit(63); 2997 } 2998 2999 static void ept_access_test_paddr_not_present_ad_disabled(void) 3000 { 3001 ept_access_test_setup(); 3002 ept_disable_ad_bits(); 3003 3004 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, EPT_VLT_RD); 3005 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, EPT_VLT_RD); 3006 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, EPT_VLT_RD); 3007 } 3008 3009 static void ept_access_test_paddr_not_present_ad_enabled(void) 3010 { 3011 u64 qual = EPT_VLT_RD | EPT_VLT_WR; 3012 3013 ept_access_test_setup(); 3014 ept_enable_ad_bits_or_skip_test(); 3015 3016 ept_access_violation_paddr(0, PT_AD_MASK, OP_READ, qual); 3017 ept_access_violation_paddr(0, PT_AD_MASK, OP_WRITE, qual); 3018 ept_access_violation_paddr(0, PT_AD_MASK, OP_EXEC, qual); 3019 } 3020 3021 static void ept_access_test_paddr_read_only_ad_disabled(void) 3022 { 3023 /* 3024 * When EPT AD bits are disabled, all accesses to guest paging 3025 * structures are reported separately as a read and (after 3026 * translation of the GPA to host physical address) a read+write 3027 * if the A/D bits have to be set. 3028 */ 3029 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3030 3031 ept_access_test_setup(); 3032 ept_disable_ad_bits(); 3033 3034 /* Can't update A bit, so all accesses fail. */ 3035 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3036 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3037 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3038 /* AD bits disabled, so only writes try to update the D bit. */ 3039 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ); 3040 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3041 ept_access_allowed_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC); 3042 /* Both A and D already set, so read-only is OK. */ 3043 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_READ); 3044 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_WRITE); 3045 ept_access_allowed_paddr(EPT_RA, PT_AD_MASK, OP_EXEC); 3046 } 3047 3048 static void ept_access_test_paddr_read_only_ad_enabled(void) 3049 { 3050 /* 3051 * When EPT AD bits are enabled, all accesses to guest paging 3052 * structures are considered writes as far as EPT translation 3053 * is concerned. 3054 */ 3055 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD; 3056 3057 ept_access_test_setup(); 3058 ept_enable_ad_bits_or_skip_test(); 3059 3060 ept_access_violation_paddr(EPT_RA, 0, OP_READ, qual); 3061 ept_access_violation_paddr(EPT_RA, 0, OP_WRITE, qual); 3062 ept_access_violation_paddr(EPT_RA, 0, OP_EXEC, qual); 3063 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_READ, qual); 3064 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_WRITE, qual); 3065 ept_access_violation_paddr(EPT_RA, PT_ACCESSED_MASK, OP_EXEC, qual); 3066 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_READ, qual); 3067 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_WRITE, qual); 3068 ept_access_violation_paddr(EPT_RA, PT_AD_MASK, OP_EXEC, qual); 3069 } 3070 3071 static void ept_access_test_paddr_read_write(void) 3072 { 3073 ept_access_test_setup(); 3074 /* Read-write access to paging structure. */ 3075 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_READ); 3076 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_WRITE); 3077 ept_access_allowed_paddr(EPT_RA | EPT_WA, 0, OP_EXEC); 3078 } 3079 3080 static void ept_access_test_paddr_read_write_execute(void) 3081 { 3082 ept_access_test_setup(); 3083 /* RWX access to paging structure. */ 3084 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_READ); 3085 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_WRITE); 3086 ept_access_allowed_paddr(EPT_PRESENT, 0, OP_EXEC); 3087 } 3088 3089 static void ept_access_test_paddr_read_execute_ad_disabled(void) 3090 { 3091 /* 3092 * When EPT AD bits are disabled, all accesses to guest paging 3093 * structures are reported separately as a read and (after 3094 * translation of the GPA to host physical address) a read+write 3095 * if the A/D bits have to be set. 3096 */ 3097 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3098 3099 ept_access_test_setup(); 3100 ept_disable_ad_bits(); 3101 3102 /* Can't update A bit, so all accesses fail. */ 3103 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3104 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3105 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3106 /* AD bits disabled, so only writes try to update the D bit. */ 3107 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ); 3108 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3109 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC); 3110 /* Both A and D already set, so read-only is OK. */ 3111 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ); 3112 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE); 3113 ept_access_allowed_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC); 3114 } 3115 3116 static void ept_access_test_paddr_read_execute_ad_enabled(void) 3117 { 3118 /* 3119 * When EPT AD bits are enabled, all accesses to guest paging 3120 * structures are considered writes as far as EPT translation 3121 * is concerned. 3122 */ 3123 u64 qual = EPT_VLT_WR | EPT_VLT_RD | EPT_VLT_PERM_RD | EPT_VLT_PERM_EX; 3124 3125 ept_access_test_setup(); 3126 ept_enable_ad_bits_or_skip_test(); 3127 3128 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_READ, qual); 3129 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_WRITE, qual); 3130 ept_access_violation_paddr(EPT_RA | EPT_EA, 0, OP_EXEC, qual); 3131 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_READ, qual); 3132 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_WRITE, qual); 3133 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_ACCESSED_MASK, OP_EXEC, qual); 3134 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_READ, qual); 3135 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_WRITE, qual); 3136 ept_access_violation_paddr(EPT_RA | EPT_EA, PT_AD_MASK, OP_EXEC, qual); 3137 } 3138 3139 static void ept_access_test_paddr_not_present_page_fault(void) 3140 { 3141 ept_access_test_setup(); 3142 /* 3143 * TODO: test no EPT violation as long as guest PF occurs. e.g., GPA is 3144 * page is read-only in EPT but GVA is also mapped read only in PT. 3145 * Thus guest page fault before host takes EPT violation for trying to 3146 * update A bit. 3147 */ 3148 } 3149 3150 static void ept_access_test_force_2m_page(void) 3151 { 3152 ept_access_test_setup(); 3153 3154 TEST_ASSERT_EQ(ept_2m_supported(), true); 3155 ept_allowed_at_level_mkhuge(true, 2, 0, 0, OP_READ); 3156 ept_violation_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_RA, OP_WRITE, 3157 EPT_VLT_WR | EPT_VLT_PERM_RD | 3158 EPT_VLT_LADDR_VLD | EPT_VLT_PADDR); 3159 ept_misconfig_at_level_mkhuge(true, 2, EPT_PRESENT, EPT_WA); 3160 } 3161 3162 static bool invvpid_valid(u64 type, u64 vpid, u64 gla) 3163 { 3164 if (!is_invvpid_type_supported(type)) 3165 return false; 3166 3167 if (vpid >> 16) 3168 return false; 3169 3170 if (type != INVVPID_ALL && !vpid) 3171 return false; 3172 3173 if (type == INVVPID_ADDR && !is_canonical(gla)) 3174 return false; 3175 3176 return true; 3177 } 3178 3179 static void try_invvpid(u64 type, u64 vpid, u64 gla) 3180 { 3181 int rc; 3182 bool valid = invvpid_valid(type, vpid, gla); 3183 u64 expected = valid ? VMXERR_UNSUPPORTED_VMCS_COMPONENT 3184 : VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID; 3185 /* 3186 * Set VMX_INST_ERROR to VMXERR_UNVALID_VMCS_COMPONENT, so 3187 * that we can tell if it is updated by INVVPID. 3188 */ 3189 vmcs_read(~0); 3190 rc = __invvpid(type, vpid, gla); 3191 report(!rc == valid, "INVVPID type %ld VPID %lx GLA %lx %s", type, 3192 vpid, gla, 3193 valid ? "passes" : "fails"); 3194 report(vmcs_read(VMX_INST_ERROR) == expected, 3195 "After %s INVVPID, VMX_INST_ERR is %ld (actual %ld)", 3196 rc ? "failed" : "successful", 3197 expected, vmcs_read(VMX_INST_ERROR)); 3198 } 3199 3200 static void ds_invvpid(void *data) 3201 { 3202 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3203 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3204 3205 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3206 asm volatile("invvpid %0, %1" 3207 : 3208 : "m"(*(struct invvpid_operand *)data), 3209 "r"(type)); 3210 } 3211 3212 /* 3213 * The SS override is ignored in 64-bit mode, so we use an addressing 3214 * mode with %rsp as the base register to generate an implicit SS 3215 * reference. 3216 */ 3217 static void ss_invvpid(void *data) 3218 { 3219 u64 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3220 u64 type = ffs(msr >> VPID_CAP_INVVPID_TYPES_SHIFT) - 1; 3221 3222 TEST_ASSERT(type >= INVVPID_ADDR && type <= INVVPID_CONTEXT_LOCAL); 3223 asm volatile("sub %%rsp,%0; invvpid (%%rsp,%0,1), %1" 3224 : "+r"(data) 3225 : "r"(type)); 3226 } 3227 3228 static void invvpid_test_gp(void) 3229 { 3230 bool fault; 3231 3232 fault = test_for_exception(GP_VECTOR, &ds_invvpid, 3233 (void *)NONCANONICAL); 3234 report(fault, "INVVPID with non-canonical DS operand raises #GP"); 3235 } 3236 3237 static void invvpid_test_ss(void) 3238 { 3239 bool fault; 3240 3241 fault = test_for_exception(SS_VECTOR, &ss_invvpid, 3242 (void *)NONCANONICAL); 3243 report(fault, "INVVPID with non-canonical SS operand raises #SS"); 3244 } 3245 3246 static void invvpid_test_pf(void) 3247 { 3248 void *vpage = alloc_vpage(); 3249 bool fault; 3250 3251 fault = test_for_exception(PF_VECTOR, &ds_invvpid, vpage); 3252 report(fault, "INVVPID with unmapped operand raises #PF"); 3253 } 3254 3255 static void try_compat_invvpid(void *unused) 3256 { 3257 struct far_pointer32 fp = { 3258 .offset = (uintptr_t)&&invvpid, 3259 .selector = KERNEL_CS32, 3260 }; 3261 uintptr_t rsp; 3262 3263 asm volatile ("mov %%rsp, %0" : "=r"(rsp)); 3264 3265 TEST_ASSERT_MSG(fp.offset == (uintptr_t)&&invvpid, 3266 "Code address too high."); 3267 TEST_ASSERT_MSG(rsp == (u32)rsp, "Stack address too high."); 3268 3269 asm goto ("lcall *%0" : : "m" (fp) : "rax" : invvpid); 3270 return; 3271 invvpid: 3272 asm volatile (".code32;" 3273 "invvpid (%eax), %eax;" 3274 "lret;" 3275 ".code64"); 3276 __builtin_unreachable(); 3277 } 3278 3279 static void invvpid_test_compatibility_mode(void) 3280 { 3281 bool fault; 3282 3283 fault = test_for_exception(UD_VECTOR, &try_compat_invvpid, NULL); 3284 report(fault, "Compatibility mode INVVPID raises #UD"); 3285 } 3286 3287 static void invvpid_test_not_in_vmx_operation(void) 3288 { 3289 bool fault; 3290 3291 TEST_ASSERT(!vmx_off()); 3292 fault = test_for_exception(UD_VECTOR, &ds_invvpid, NULL); 3293 report(fault, "INVVPID outside of VMX operation raises #UD"); 3294 TEST_ASSERT(!vmx_on()); 3295 } 3296 3297 /* 3298 * This does not test real-address mode, virtual-8086 mode, protected mode, 3299 * or CPL > 0. 3300 */ 3301 static void invvpid_test(void) 3302 { 3303 u64 msr; 3304 int i; 3305 unsigned types = 0; 3306 unsigned type; 3307 3308 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 3309 !(ctrl_cpu_rev[1].clr & CPU_VPID)) 3310 test_skip("VPID not supported"); 3311 3312 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 3313 3314 if (!(msr & VPID_CAP_INVVPID)) 3315 test_skip("INVVPID not supported.\n"); 3316 3317 if (is_invvpid_type_supported(INVVPID_ADDR)) 3318 types |= 1u << INVVPID_ADDR; 3319 if (is_invvpid_type_supported(INVVPID_CONTEXT_GLOBAL)) 3320 types |= 1u << INVVPID_CONTEXT_GLOBAL; 3321 if (is_invvpid_type_supported(INVVPID_ALL)) 3322 types |= 1u << INVVPID_ALL; 3323 if (is_invvpid_type_supported(INVVPID_CONTEXT_LOCAL)) 3324 types |= 1u << INVVPID_CONTEXT_LOCAL; 3325 3326 if (!types) 3327 test_skip("No INVVPID types supported.\n"); 3328 3329 for (i = -127; i < 128; i++) 3330 try_invvpid(i, 0xffff, 0); 3331 3332 /* 3333 * VPID must not be more than 16 bits. 3334 */ 3335 for (i = 0; i < 64; i++) 3336 for (type = 0; type < 4; type++) 3337 if (types & (1u << type)) 3338 try_invvpid(type, 1ul << i, 0); 3339 3340 /* 3341 * VPID must not be zero, except for "all contexts." 3342 */ 3343 for (type = 0; type < 4; type++) 3344 if (types & (1u << type)) 3345 try_invvpid(type, 0, 0); 3346 3347 /* 3348 * The gla operand is only validated for single-address INVVPID. 3349 */ 3350 if (types & (1u << INVVPID_ADDR)) 3351 try_invvpid(INVVPID_ADDR, 0xffff, NONCANONICAL); 3352 3353 invvpid_test_gp(); 3354 invvpid_test_ss(); 3355 invvpid_test_pf(); 3356 invvpid_test_compatibility_mode(); 3357 invvpid_test_not_in_vmx_operation(); 3358 } 3359 3360 /* 3361 * Test for early VMLAUNCH failure. Returns true if VMLAUNCH makes it 3362 * at least as far as the guest-state checks. Returns false if the 3363 * VMLAUNCH fails early and execution falls through to the next 3364 * instruction. 3365 */ 3366 static bool vmlaunch_succeeds(void) 3367 { 3368 u32 exit_reason; 3369 3370 /* 3371 * Indirectly set VMX_INST_ERR to 12 ("VMREAD/VMWRITE from/to 3372 * unsupported VMCS component"). The caller can then check 3373 * to see if a failed VM-entry sets VMX_INST_ERR as expected. 3374 */ 3375 vmcs_write(~0u, 0); 3376 3377 vmcs_write(HOST_RIP, (uintptr_t)&&success); 3378 __asm__ __volatile__ goto ("vmwrite %%rsp, %0; vmlaunch" 3379 : 3380 : "r" ((u64)HOST_RSP) 3381 : "cc", "memory" 3382 : success); 3383 return false; 3384 success: 3385 exit_reason = vmcs_read(EXI_REASON); 3386 TEST_ASSERT(exit_reason == (VMX_FAIL_STATE | VMX_ENTRY_FAILURE) || 3387 exit_reason == (VMX_FAIL_MSR | VMX_ENTRY_FAILURE)); 3388 return true; 3389 } 3390 3391 /* 3392 * Try to launch the current VMCS. 3393 */ 3394 static void test_vmx_vmlaunch(u32 xerror) 3395 { 3396 bool success = vmlaunch_succeeds(); 3397 u32 vmx_inst_err; 3398 3399 report(success == !xerror, "vmlaunch %s", 3400 !xerror ? "succeeds" : "fails"); 3401 if (!success && xerror) { 3402 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3403 report(vmx_inst_err == xerror, 3404 "VMX inst error is %d (actual %d)", xerror, 3405 vmx_inst_err); 3406 } 3407 } 3408 3409 /* 3410 * Try to launch the current VMCS, and expect one of two possible 3411 * errors (or success) codes. 3412 */ 3413 static void test_vmx_vmlaunch2(u32 xerror1, u32 xerror2) 3414 { 3415 bool success = vmlaunch_succeeds(); 3416 u32 vmx_inst_err; 3417 3418 if (!xerror1 == !xerror2) 3419 report(success == !xerror1, "vmlaunch %s", 3420 !xerror1 ? "succeeds" : "fails"); 3421 3422 if (!success && (xerror1 || xerror2)) { 3423 vmx_inst_err = vmcs_read(VMX_INST_ERROR); 3424 report(vmx_inst_err == xerror1 || vmx_inst_err == xerror2, 3425 "VMX inst error is %d or %d (actual %d)", xerror1, 3426 xerror2, vmx_inst_err); 3427 } 3428 } 3429 3430 static void test_vmx_invalid_controls(void) 3431 { 3432 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_CONTROL_FIELD); 3433 } 3434 3435 static void test_vmx_valid_controls(void) 3436 { 3437 test_vmx_vmlaunch(0); 3438 } 3439 3440 /* 3441 * Test a particular value of a VM-execution control bit, if the value 3442 * is required or if the value is zero. 3443 */ 3444 static void test_rsvd_ctl_bit_value(const char *name, union vmx_ctrl_msr msr, 3445 enum Encoding encoding, unsigned bit, 3446 unsigned val) 3447 { 3448 u32 mask = 1u << bit; 3449 bool expected; 3450 u32 controls; 3451 3452 if (msr.set & mask) 3453 TEST_ASSERT(msr.clr & mask); 3454 3455 /* 3456 * We can't arbitrarily turn on a control bit, because it may 3457 * introduce dependencies on other VMCS fields. So, we only 3458 * test turning on bits that have a required setting. 3459 */ 3460 if (val && (msr.clr & mask) && !(msr.set & mask)) 3461 return; 3462 3463 report_prefix_pushf("%s %s bit %d", 3464 val ? "Set" : "Clear", name, bit); 3465 3466 controls = vmcs_read(encoding); 3467 if (val) { 3468 vmcs_write(encoding, msr.set | mask); 3469 expected = (msr.clr & mask); 3470 } else { 3471 vmcs_write(encoding, msr.set & ~mask); 3472 expected = !(msr.set & mask); 3473 } 3474 if (expected) 3475 test_vmx_valid_controls(); 3476 else 3477 test_vmx_invalid_controls(); 3478 vmcs_write(encoding, controls); 3479 report_prefix_pop(); 3480 } 3481 3482 /* 3483 * Test reserved values of a VM-execution control bit, based on the 3484 * allowed bit settings from the corresponding VMX capability MSR. 3485 */ 3486 static void test_rsvd_ctl_bit(const char *name, union vmx_ctrl_msr msr, 3487 enum Encoding encoding, unsigned bit) 3488 { 3489 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 0); 3490 test_rsvd_ctl_bit_value(name, msr, encoding, bit, 1); 3491 } 3492 3493 /* 3494 * Reserved bits in the pin-based VM-execution controls must be set 3495 * properly. Software may consult the VMX capability MSRs to determine 3496 * the proper settings. 3497 * [Intel SDM] 3498 */ 3499 static void test_pin_based_ctls(void) 3500 { 3501 unsigned bit; 3502 3503 printf("%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PIN" : 3504 "MSR_IA32_VMX_PINBASED_CTLS", ctrl_pin_rev.val); 3505 for (bit = 0; bit < 32; bit++) 3506 test_rsvd_ctl_bit("pin-based controls", 3507 ctrl_pin_rev, PIN_CONTROLS, bit); 3508 } 3509 3510 /* 3511 * Reserved bits in the primary processor-based VM-execution controls 3512 * must be set properly. Software may consult the VMX capability MSRs 3513 * to determine the proper settings. 3514 * [Intel SDM] 3515 */ 3516 static void test_primary_processor_based_ctls(void) 3517 { 3518 unsigned bit; 3519 3520 printf("\n%s: %lx\n", basic.ctrl ? "MSR_IA32_VMX_TRUE_PROC" : 3521 "MSR_IA32_VMX_PROCBASED_CTLS", ctrl_cpu_rev[0].val); 3522 for (bit = 0; bit < 32; bit++) 3523 test_rsvd_ctl_bit("primary processor-based controls", 3524 ctrl_cpu_rev[0], CPU_EXEC_CTRL0, bit); 3525 } 3526 3527 /* 3528 * If the "activate secondary controls" primary processor-based 3529 * VM-execution control is 1, reserved bits in the secondary 3530 * processor-based VM-execution controls must be cleared. Software may 3531 * consult the VMX capability MSRs to determine which bits are 3532 * reserved. 3533 * If the "activate secondary controls" primary processor-based 3534 * VM-execution control is 0 (or if the processor does not support the 3535 * 1-setting of that control), no checks are performed on the 3536 * secondary processor-based VM-execution controls. 3537 * [Intel SDM] 3538 */ 3539 static void test_secondary_processor_based_ctls(void) 3540 { 3541 u32 primary; 3542 u32 secondary; 3543 unsigned bit; 3544 3545 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) 3546 return; 3547 3548 primary = vmcs_read(CPU_EXEC_CTRL0); 3549 secondary = vmcs_read(CPU_EXEC_CTRL1); 3550 3551 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3552 printf("\nMSR_IA32_VMX_PROCBASED_CTLS2: %lx\n", ctrl_cpu_rev[1].val); 3553 for (bit = 0; bit < 32; bit++) 3554 test_rsvd_ctl_bit("secondary processor-based controls", 3555 ctrl_cpu_rev[1], CPU_EXEC_CTRL1, bit); 3556 3557 /* 3558 * When the "activate secondary controls" VM-execution control 3559 * is clear, there are no checks on the secondary controls. 3560 */ 3561 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3562 vmcs_write(CPU_EXEC_CTRL1, ~0); 3563 report(vmlaunch_succeeds(), 3564 "Secondary processor-based controls ignored"); 3565 vmcs_write(CPU_EXEC_CTRL1, secondary); 3566 vmcs_write(CPU_EXEC_CTRL0, primary); 3567 } 3568 3569 static void try_cr3_target_count(unsigned i, unsigned max) 3570 { 3571 report_prefix_pushf("CR3 target count 0x%x", i); 3572 vmcs_write(CR3_TARGET_COUNT, i); 3573 if (i <= max) 3574 test_vmx_valid_controls(); 3575 else 3576 test_vmx_invalid_controls(); 3577 report_prefix_pop(); 3578 } 3579 3580 /* 3581 * The CR3-target count must not be greater than 4. Future processors 3582 * may support a different number of CR3-target values. Software 3583 * should read the VMX capability MSR IA32_VMX_MISC to determine the 3584 * number of values supported. 3585 * [Intel SDM] 3586 */ 3587 static void test_cr3_targets(void) 3588 { 3589 unsigned supported_targets = (rdmsr(MSR_IA32_VMX_MISC) >> 16) & 0x1ff; 3590 u32 cr3_targets = vmcs_read(CR3_TARGET_COUNT); 3591 unsigned i; 3592 3593 printf("\nSupported CR3 targets: %d\n", supported_targets); 3594 TEST_ASSERT(supported_targets <= 256); 3595 3596 try_cr3_target_count(-1u, supported_targets); 3597 try_cr3_target_count(0x80000000, supported_targets); 3598 try_cr3_target_count(0x7fffffff, supported_targets); 3599 for (i = 0; i <= supported_targets + 1; i++) 3600 try_cr3_target_count(i, supported_targets); 3601 vmcs_write(CR3_TARGET_COUNT, cr3_targets); 3602 3603 /* VMWRITE to nonexistent target fields should fail. */ 3604 for (i = supported_targets; i < 256; i++) 3605 TEST_ASSERT(vmcs_write(CR3_TARGET_0 + i*2, 0)); 3606 } 3607 3608 /* 3609 * Test a particular address setting in the VMCS 3610 */ 3611 static void test_vmcs_addr(const char *name, 3612 enum Encoding encoding, 3613 u64 align, 3614 bool ignored, 3615 bool skip_beyond_mapped_ram, 3616 u64 addr) 3617 { 3618 report_prefix_pushf("%s = %lx", name, addr); 3619 vmcs_write(encoding, addr); 3620 if (skip_beyond_mapped_ram && 3621 addr > fwcfg_get_u64(FW_CFG_RAM_SIZE) - align && 3622 addr < (1ul << cpuid_maxphyaddr())) 3623 printf("Skipping physical address beyond mapped RAM\n"); 3624 else if (ignored || (IS_ALIGNED(addr, align) && 3625 addr < (1ul << cpuid_maxphyaddr()))) 3626 test_vmx_valid_controls(); 3627 else 3628 test_vmx_invalid_controls(); 3629 report_prefix_pop(); 3630 } 3631 3632 /* 3633 * Test interesting values for a VMCS address 3634 */ 3635 static void test_vmcs_addr_values(const char *name, 3636 enum Encoding encoding, 3637 u64 align, 3638 bool ignored, 3639 bool skip_beyond_mapped_ram, 3640 u32 bit_start, u32 bit_end) 3641 { 3642 unsigned i; 3643 u64 orig_val = vmcs_read(encoding); 3644 3645 for (i = bit_start; i <= bit_end; i++) 3646 test_vmcs_addr(name, encoding, align, ignored, 3647 skip_beyond_mapped_ram, 1ul << i); 3648 3649 test_vmcs_addr(name, encoding, align, ignored, 3650 skip_beyond_mapped_ram, PAGE_SIZE - 1); 3651 test_vmcs_addr(name, encoding, align, ignored, 3652 skip_beyond_mapped_ram, PAGE_SIZE); 3653 test_vmcs_addr(name, encoding, align, ignored, 3654 skip_beyond_mapped_ram, 3655 (1ul << cpuid_maxphyaddr()) - PAGE_SIZE); 3656 test_vmcs_addr(name, encoding, align, ignored, 3657 skip_beyond_mapped_ram, -1ul); 3658 3659 vmcs_write(encoding, orig_val); 3660 } 3661 3662 /* 3663 * Test a physical address reference in the VMCS, when the corresponding 3664 * feature is enabled and when the corresponding feature is disabled. 3665 */ 3666 static void test_vmcs_addr_reference(u32 control_bit, enum Encoding field, 3667 const char *field_name, 3668 const char *control_name, u64 align, 3669 bool skip_beyond_mapped_ram, 3670 bool control_primary) 3671 { 3672 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 3673 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 3674 u64 page_addr; 3675 3676 if (control_primary) { 3677 if (!(ctrl_cpu_rev[0].clr & control_bit)) 3678 return; 3679 } else { 3680 if (!(ctrl_cpu_rev[1].clr & control_bit)) 3681 return; 3682 } 3683 3684 page_addr = vmcs_read(field); 3685 3686 report_prefix_pushf("%s enabled", control_name); 3687 if (control_primary) { 3688 vmcs_write(CPU_EXEC_CTRL0, primary | control_bit); 3689 } else { 3690 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3691 vmcs_write(CPU_EXEC_CTRL1, secondary | control_bit); 3692 } 3693 3694 test_vmcs_addr_values(field_name, field, align, false, 3695 skip_beyond_mapped_ram, 0, 63); 3696 report_prefix_pop(); 3697 3698 report_prefix_pushf("%s disabled", control_name); 3699 if (control_primary) { 3700 vmcs_write(CPU_EXEC_CTRL0, primary & ~control_bit); 3701 } else { 3702 vmcs_write(CPU_EXEC_CTRL0, primary & ~CPU_SECONDARY); 3703 vmcs_write(CPU_EXEC_CTRL1, secondary & ~control_bit); 3704 } 3705 3706 test_vmcs_addr_values(field_name, field, align, true, false, 0, 63); 3707 report_prefix_pop(); 3708 3709 vmcs_write(field, page_addr); 3710 vmcs_write(CPU_EXEC_CTRL0, primary); 3711 vmcs_write(CPU_EXEC_CTRL1, secondary); 3712 } 3713 3714 /* 3715 * If the "use I/O bitmaps" VM-execution control is 1, bits 11:0 of 3716 * each I/O-bitmap address must be 0. Neither address should set any 3717 * bits beyond the processor's physical-address width. 3718 * [Intel SDM] 3719 */ 3720 static void test_io_bitmaps(void) 3721 { 3722 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_A, 3723 "I/O bitmap A", "Use I/O bitmaps", 3724 PAGE_SIZE, false, true); 3725 test_vmcs_addr_reference(CPU_IO_BITMAP, IO_BITMAP_B, 3726 "I/O bitmap B", "Use I/O bitmaps", 3727 PAGE_SIZE, false, true); 3728 } 3729 3730 /* 3731 * If the "use MSR bitmaps" VM-execution control is 1, bits 11:0 of 3732 * the MSR-bitmap address must be 0. The address should not set any 3733 * bits beyond the processor's physical-address width. 3734 * [Intel SDM] 3735 */ 3736 static void test_msr_bitmap(void) 3737 { 3738 test_vmcs_addr_reference(CPU_MSR_BITMAP, MSR_BITMAP, 3739 "MSR bitmap", "Use MSR bitmaps", 3740 PAGE_SIZE, false, true); 3741 } 3742 3743 /* 3744 * If the "use TPR shadow" VM-execution control is 1, the virtual-APIC 3745 * address must satisfy the following checks: 3746 * - Bits 11:0 of the address must be 0. 3747 * - The address should not set any bits beyond the processor's 3748 * physical-address width. 3749 * [Intel SDM] 3750 */ 3751 static void test_apic_virt_addr(void) 3752 { 3753 /* 3754 * Ensure the processor will never use the virtual-APIC page, since 3755 * we will point it to invalid RAM. Otherwise KVM is puzzled about 3756 * what we're trying to achieve and fails vmentry. 3757 */ 3758 u32 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 3759 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0 | CPU_CR8_LOAD | CPU_CR8_STORE); 3760 test_vmcs_addr_reference(CPU_TPR_SHADOW, APIC_VIRT_ADDR, 3761 "virtual-APIC address", "Use TPR shadow", 3762 PAGE_SIZE, false, true); 3763 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 3764 } 3765 3766 /* 3767 * If the "virtualize APIC-accesses" VM-execution control is 1, the 3768 * APIC-access address must satisfy the following checks: 3769 * - Bits 11:0 of the address must be 0. 3770 * - The address should not set any bits beyond the processor's 3771 * physical-address width. 3772 * [Intel SDM] 3773 */ 3774 static void test_apic_access_addr(void) 3775 { 3776 void *apic_access_page = alloc_page(); 3777 3778 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_page)); 3779 3780 test_vmcs_addr_reference(CPU_VIRT_APIC_ACCESSES, APIC_ACCS_ADDR, 3781 "APIC-access address", 3782 "virtualize APIC-accesses", PAGE_SIZE, 3783 true, false); 3784 } 3785 3786 static bool set_bit_pattern(u8 mask, u32 *secondary) 3787 { 3788 u8 i; 3789 bool flag = false; 3790 u32 test_bits[3] = { 3791 CPU_VIRT_X2APIC, 3792 CPU_APIC_REG_VIRT, 3793 CPU_VINTD 3794 }; 3795 3796 for (i = 0; i < ARRAY_SIZE(test_bits); i++) { 3797 if ((mask & (1u << i)) && 3798 (ctrl_cpu_rev[1].clr & test_bits[i])) { 3799 *secondary |= test_bits[i]; 3800 flag = true; 3801 } 3802 } 3803 3804 return (flag); 3805 } 3806 3807 /* 3808 * If the "use TPR shadow" VM-execution control is 0, the following 3809 * VM-execution controls must also be 0: 3810 * - virtualize x2APIC mode 3811 * - APIC-register virtualization 3812 * - virtual-interrupt delivery 3813 * [Intel SDM] 3814 * 3815 * 2. If the "virtualize x2APIC mode" VM-execution control is 1, the 3816 * "virtualize APIC accesses" VM-execution control must be 0. 3817 * [Intel SDM] 3818 */ 3819 static void test_apic_virtual_ctls(void) 3820 { 3821 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3822 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3823 u32 primary = saved_primary; 3824 u32 secondary = saved_secondary; 3825 bool ctrl = false; 3826 char str[10] = "disabled"; 3827 u8 i = 0, j; 3828 3829 /* 3830 * First test 3831 */ 3832 if (!((ctrl_cpu_rev[0].clr & (CPU_SECONDARY | CPU_TPR_SHADOW)) == 3833 (CPU_SECONDARY | CPU_TPR_SHADOW))) 3834 return; 3835 3836 primary |= CPU_SECONDARY; 3837 primary &= ~CPU_TPR_SHADOW; 3838 vmcs_write(CPU_EXEC_CTRL0, primary); 3839 3840 while (1) { 3841 for (j = 1; j < 8; j++) { 3842 secondary &= ~(CPU_VIRT_X2APIC | CPU_APIC_REG_VIRT | CPU_VINTD); 3843 if (primary & CPU_TPR_SHADOW) { 3844 ctrl = true; 3845 } else { 3846 if (! set_bit_pattern(j, &secondary)) 3847 ctrl = true; 3848 else 3849 ctrl = false; 3850 } 3851 3852 vmcs_write(CPU_EXEC_CTRL1, secondary); 3853 report_prefix_pushf("Use TPR shadow %s, virtualize x2APIC mode %s, APIC-register virtualization %s, virtual-interrupt delivery %s", 3854 str, (secondary & CPU_VIRT_X2APIC) ? "enabled" : "disabled", (secondary & CPU_APIC_REG_VIRT) ? "enabled" : "disabled", (secondary & CPU_VINTD) ? "enabled" : "disabled"); 3855 if (ctrl) 3856 test_vmx_valid_controls(); 3857 else 3858 test_vmx_invalid_controls(); 3859 report_prefix_pop(); 3860 } 3861 3862 if (i == 1) 3863 break; 3864 i++; 3865 3866 primary |= CPU_TPR_SHADOW; 3867 vmcs_write(CPU_EXEC_CTRL0, primary); 3868 strcpy(str, "enabled"); 3869 } 3870 3871 /* 3872 * Second test 3873 */ 3874 u32 apic_virt_ctls = (CPU_VIRT_X2APIC | CPU_VIRT_APIC_ACCESSES); 3875 3876 primary = saved_primary; 3877 secondary = saved_secondary; 3878 if (!((ctrl_cpu_rev[1].clr & apic_virt_ctls) == apic_virt_ctls)) 3879 return; 3880 3881 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY); 3882 secondary &= ~CPU_VIRT_APIC_ACCESSES; 3883 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_X2APIC); 3884 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access disabled"); 3885 test_vmx_valid_controls(); 3886 report_prefix_pop(); 3887 3888 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_APIC_ACCESSES); 3889 report_prefix_pushf("Virtualize x2APIC mode disabled; virtualize APIC access enabled"); 3890 test_vmx_valid_controls(); 3891 report_prefix_pop(); 3892 3893 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VIRT_X2APIC); 3894 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access enabled"); 3895 test_vmx_invalid_controls(); 3896 report_prefix_pop(); 3897 3898 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VIRT_APIC_ACCESSES); 3899 report_prefix_pushf("Virtualize x2APIC mode enabled; virtualize APIC access disabled"); 3900 test_vmx_valid_controls(); 3901 report_prefix_pop(); 3902 3903 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3904 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3905 } 3906 3907 /* 3908 * If the "virtual-interrupt delivery" VM-execution control is 1, the 3909 * "external-interrupt exiting" VM-execution control must be 1. 3910 * [Intel SDM] 3911 */ 3912 static void test_virtual_intr_ctls(void) 3913 { 3914 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3915 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3916 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3917 u32 primary = saved_primary; 3918 u32 secondary = saved_secondary; 3919 u32 pin = saved_pin; 3920 3921 if (!((ctrl_cpu_rev[1].clr & CPU_VINTD) && 3922 (ctrl_pin_rev.clr & PIN_EXTINT))) 3923 return; 3924 3925 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3926 vmcs_write(CPU_EXEC_CTRL1, secondary & ~CPU_VINTD); 3927 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3928 report_prefix_pushf("Virtualize interrupt-delivery disabled; external-interrupt exiting disabled"); 3929 test_vmx_valid_controls(); 3930 report_prefix_pop(); 3931 3932 vmcs_write(CPU_EXEC_CTRL1, secondary | CPU_VINTD); 3933 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3934 test_vmx_invalid_controls(); 3935 report_prefix_pop(); 3936 3937 vmcs_write(PIN_CONTROLS, pin | PIN_EXTINT); 3938 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting enabled"); 3939 test_vmx_valid_controls(); 3940 report_prefix_pop(); 3941 3942 vmcs_write(PIN_CONTROLS, pin & ~PIN_EXTINT); 3943 report_prefix_pushf("Virtualize interrupt-delivery enabled; external-interrupt exiting disabled"); 3944 test_vmx_invalid_controls(); 3945 report_prefix_pop(); 3946 3947 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 3948 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 3949 vmcs_write(PIN_CONTROLS, saved_pin); 3950 } 3951 3952 static void test_pi_desc_addr(u64 addr, bool ctrl) 3953 { 3954 vmcs_write(POSTED_INTR_DESC_ADDR, addr); 3955 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-descriptor-address 0x%lx", addr); 3956 if (ctrl) 3957 test_vmx_valid_controls(); 3958 else 3959 test_vmx_invalid_controls(); 3960 report_prefix_pop(); 3961 } 3962 3963 /* 3964 * If the "process posted interrupts" VM-execution control is 1, the 3965 * following must be true: 3966 * 3967 * - The "virtual-interrupt delivery" VM-execution control is 1. 3968 * - The "acknowledge interrupt on exit" VM-exit control is 1. 3969 * - The posted-interrupt notification vector has a value in the 3970 * - range 0 - 255 (bits 15:8 are all 0). 3971 * - Bits 5:0 of the posted-interrupt descriptor address are all 0. 3972 * - The posted-interrupt descriptor address does not set any bits 3973 * beyond the processor's physical-address width. 3974 * [Intel SDM] 3975 */ 3976 static void test_posted_intr(void) 3977 { 3978 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 3979 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 3980 u32 saved_pin = vmcs_read(PIN_CONTROLS); 3981 u32 exit_ctl_saved = vmcs_read(EXI_CONTROLS); 3982 u32 primary = saved_primary; 3983 u32 secondary = saved_secondary; 3984 u32 pin = saved_pin; 3985 u32 exit_ctl = exit_ctl_saved; 3986 u16 vec; 3987 int i; 3988 3989 if (!((ctrl_pin_rev.clr & PIN_POST_INTR) && 3990 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 3991 (ctrl_exit_rev.clr & EXI_INTA))) 3992 return; 3993 3994 vmcs_write(CPU_EXEC_CTRL0, primary | CPU_SECONDARY | CPU_TPR_SHADOW); 3995 3996 /* 3997 * Test virtual-interrupt-delivery and acknowledge-interrupt-on-exit 3998 */ 3999 pin |= PIN_POST_INTR; 4000 vmcs_write(PIN_CONTROLS, pin); 4001 secondary &= ~CPU_VINTD; 4002 vmcs_write(CPU_EXEC_CTRL1, secondary); 4003 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled"); 4004 test_vmx_invalid_controls(); 4005 report_prefix_pop(); 4006 4007 secondary |= CPU_VINTD; 4008 vmcs_write(CPU_EXEC_CTRL1, secondary); 4009 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled"); 4010 test_vmx_invalid_controls(); 4011 report_prefix_pop(); 4012 4013 exit_ctl &= ~EXI_INTA; 4014 vmcs_write(EXI_CONTROLS, exit_ctl); 4015 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit disabled"); 4016 test_vmx_invalid_controls(); 4017 report_prefix_pop(); 4018 4019 exit_ctl |= EXI_INTA; 4020 vmcs_write(EXI_CONTROLS, exit_ctl); 4021 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4022 test_vmx_valid_controls(); 4023 report_prefix_pop(); 4024 4025 secondary &= ~CPU_VINTD; 4026 vmcs_write(CPU_EXEC_CTRL1, secondary); 4027 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery disabled; acknowledge-interrupt-on-exit enabled"); 4028 test_vmx_invalid_controls(); 4029 report_prefix_pop(); 4030 4031 secondary |= CPU_VINTD; 4032 vmcs_write(CPU_EXEC_CTRL1, secondary); 4033 report_prefix_pushf("Process-posted-interrupts enabled; virtual-interrupt-delivery enabled; acknowledge-interrupt-on-exit enabled"); 4034 test_vmx_valid_controls(); 4035 report_prefix_pop(); 4036 4037 /* 4038 * Test posted-interrupt notification vector 4039 */ 4040 for (i = 0; i < 8; i++) { 4041 vec = (1ul << i); 4042 vmcs_write(PINV, vec); 4043 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4044 test_vmx_valid_controls(); 4045 report_prefix_pop(); 4046 } 4047 for (i = 8; i < 16; i++) { 4048 vec = (1ul << i); 4049 vmcs_write(PINV, vec); 4050 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4051 test_vmx_invalid_controls(); 4052 report_prefix_pop(); 4053 } 4054 4055 vec &= ~(0xff << 8); 4056 vmcs_write(PINV, vec); 4057 report_prefix_pushf("Process-posted-interrupts enabled; posted-interrupt-notification-vector %u", vec); 4058 test_vmx_valid_controls(); 4059 report_prefix_pop(); 4060 4061 /* 4062 * Test posted-interrupt descriptor addresss 4063 */ 4064 for (i = 0; i < 6; i++) { 4065 test_pi_desc_addr(1ul << i, false); 4066 } 4067 4068 test_pi_desc_addr(0xf0, false); 4069 test_pi_desc_addr(0xff, false); 4070 test_pi_desc_addr(0x0f, false); 4071 test_pi_desc_addr(0x8000, true); 4072 test_pi_desc_addr(0x00, true); 4073 test_pi_desc_addr(0xc000, true); 4074 4075 test_vmcs_addr_values("process-posted interrupts", 4076 POSTED_INTR_DESC_ADDR, 64, 4077 false, false, 0, 63); 4078 4079 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4080 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4081 vmcs_write(PIN_CONTROLS, saved_pin); 4082 } 4083 4084 static void test_apic_ctls(void) 4085 { 4086 test_apic_virt_addr(); 4087 test_apic_access_addr(); 4088 test_apic_virtual_ctls(); 4089 test_virtual_intr_ctls(); 4090 test_posted_intr(); 4091 } 4092 4093 /* 4094 * If the "enable VPID" VM-execution control is 1, the value of the 4095 * of the VPID VM-execution control field must not be 0000H. 4096 * [Intel SDM] 4097 */ 4098 static void test_vpid(void) 4099 { 4100 u32 saved_primary = vmcs_read(CPU_EXEC_CTRL0); 4101 u32 saved_secondary = vmcs_read(CPU_EXEC_CTRL1); 4102 u16 vpid = 0x0000; 4103 int i; 4104 4105 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4106 (ctrl_cpu_rev[1].clr & CPU_VPID))) { 4107 printf("Secondary controls and/or VPID not supported\n"); 4108 return; 4109 } 4110 4111 vmcs_write(CPU_EXEC_CTRL0, saved_primary | CPU_SECONDARY); 4112 vmcs_write(CPU_EXEC_CTRL1, saved_secondary & ~CPU_VPID); 4113 vmcs_write(VPID, vpid); 4114 report_prefix_pushf("VPID disabled; VPID value %x", vpid); 4115 test_vmx_valid_controls(); 4116 report_prefix_pop(); 4117 4118 vmcs_write(CPU_EXEC_CTRL1, saved_secondary | CPU_VPID); 4119 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4120 test_vmx_invalid_controls(); 4121 report_prefix_pop(); 4122 4123 for (i = 0; i < 16; i++) { 4124 vpid = (short)1 << i;; 4125 vmcs_write(VPID, vpid); 4126 report_prefix_pushf("VPID enabled; VPID value %x", vpid); 4127 test_vmx_valid_controls(); 4128 report_prefix_pop(); 4129 } 4130 4131 vmcs_write(CPU_EXEC_CTRL0, saved_primary); 4132 vmcs_write(CPU_EXEC_CTRL1, saved_secondary); 4133 } 4134 4135 static void set_vtpr(unsigned vtpr) 4136 { 4137 *(u32 *)phys_to_virt(vmcs_read(APIC_VIRT_ADDR) + APIC_TASKPRI) = vtpr; 4138 } 4139 4140 static void try_tpr_threshold_and_vtpr(unsigned threshold, unsigned vtpr) 4141 { 4142 bool valid = true; 4143 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4144 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4145 4146 if ((primary & CPU_TPR_SHADOW) && 4147 (!(primary & CPU_SECONDARY) || 4148 !(secondary & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4149 valid = (threshold & 0xf) <= ((vtpr >> 4) & 0xf); 4150 4151 set_vtpr(vtpr); 4152 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0x%x", 4153 threshold, (vtpr >> 4) & 0xf); 4154 if (valid) 4155 test_vmx_valid_controls(); 4156 else 4157 test_vmx_invalid_controls(); 4158 report_prefix_pop(); 4159 } 4160 4161 static void test_invalid_event_injection(void) 4162 { 4163 u32 ent_intr_info_save = vmcs_read(ENT_INTR_INFO); 4164 u32 ent_intr_error_save = vmcs_read(ENT_INTR_ERROR); 4165 u32 ent_inst_len_save = vmcs_read(ENT_INST_LEN); 4166 u32 primary_save = vmcs_read(CPU_EXEC_CTRL0); 4167 u32 secondary_save = vmcs_read(CPU_EXEC_CTRL1); 4168 u64 guest_cr0_save = vmcs_read(GUEST_CR0); 4169 u32 ent_intr_info_base = INTR_INFO_VALID_MASK; 4170 u32 ent_intr_info, ent_intr_err, ent_intr_len; 4171 u32 cnt; 4172 4173 /* Setup */ 4174 report_prefix_push("invalid event injection"); 4175 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4176 vmcs_write(ENT_INST_LEN, 0x00000001); 4177 4178 /* The field's interruption type is not set to a reserved value. */ 4179 ent_intr_info = ent_intr_info_base | INTR_TYPE_RESERVED | DE_VECTOR; 4180 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4181 "RESERVED interruption type invalid [-]", 4182 ent_intr_info); 4183 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4184 test_vmx_invalid_controls(); 4185 report_prefix_pop(); 4186 4187 ent_intr_info = ent_intr_info_base | INTR_TYPE_EXT_INTR | 4188 DE_VECTOR; 4189 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4190 "RESERVED interruption type invalid [+]", 4191 ent_intr_info); 4192 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4193 test_vmx_valid_controls(); 4194 report_prefix_pop(); 4195 4196 /* If the interruption type is other event, the vector is 0. */ 4197 ent_intr_info = ent_intr_info_base | INTR_TYPE_OTHER_EVENT | DB_VECTOR; 4198 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4199 "(OTHER EVENT && vector != 0) invalid [-]", 4200 ent_intr_info); 4201 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4202 test_vmx_invalid_controls(); 4203 report_prefix_pop(); 4204 4205 /* If the interruption type is NMI, the vector is 2 (negative case). */ 4206 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | DE_VECTOR; 4207 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4208 "(NMI && vector != 2) invalid [-]", ent_intr_info); 4209 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4210 test_vmx_invalid_controls(); 4211 report_prefix_pop(); 4212 4213 /* If the interruption type is NMI, the vector is 2 (positive case). */ 4214 ent_intr_info = ent_intr_info_base | INTR_TYPE_NMI_INTR | NMI_VECTOR; 4215 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4216 "(NMI && vector == 2) valid [+]", ent_intr_info); 4217 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4218 test_vmx_valid_controls(); 4219 report_prefix_pop(); 4220 4221 /* 4222 * If the interruption type 4223 * is HW exception, the vector is at most 31. 4224 */ 4225 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 0x20; 4226 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4227 "(HW exception && vector > 31) invalid [-]", 4228 ent_intr_info); 4229 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4230 test_vmx_invalid_controls(); 4231 report_prefix_pop(); 4232 4233 /* 4234 * deliver-error-code is 1 iff either 4235 * (a) the "unrestricted guest" VM-execution control is 0 4236 * (b) CR0.PE is set. 4237 */ 4238 4239 /* Assert that unrestricted guest is disabled or unsupported */ 4240 assert(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 4241 !(secondary_save & CPU_URG)); 4242 4243 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4244 GP_VECTOR; 4245 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4246 "error code <-> (!URG || prot_mode) [-]", 4247 ent_intr_info); 4248 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4249 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4250 test_vmx_invalid_controls(); 4251 report_prefix_pop(); 4252 4253 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4254 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4255 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4256 "error code <-> (!URG || prot_mode) [+]", 4257 ent_intr_info); 4258 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4259 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4260 test_vmx_valid_controls(); 4261 report_prefix_pop(); 4262 4263 if (enable_unrestricted_guest(false)) 4264 goto skip_unrestricted_guest; 4265 4266 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4267 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4268 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4269 "error code <-> (!URG || prot_mode) [-]", 4270 ent_intr_info); 4271 vmcs_write(GUEST_CR0, guest_cr0_save & ~X86_CR0_PE & ~X86_CR0_PG); 4272 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4273 test_vmx_invalid_controls(); 4274 report_prefix_pop(); 4275 4276 ent_intr_info = ent_intr_info_base | INTR_TYPE_HARD_EXCEPTION | 4277 GP_VECTOR; 4278 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4279 "error code <-> (!URG || prot_mode) [-]", 4280 ent_intr_info); 4281 vmcs_write(GUEST_CR0, guest_cr0_save | X86_CR0_PE); 4282 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4283 test_vmx_invalid_controls(); 4284 report_prefix_pop(); 4285 4286 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4287 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4288 4289 skip_unrestricted_guest: 4290 vmcs_write(GUEST_CR0, guest_cr0_save); 4291 4292 /* deliver-error-code is 1 iff the interruption type is HW exception */ 4293 report_prefix_push("error code <-> HW exception"); 4294 for (cnt = 0; cnt < 8; cnt++) { 4295 u32 exception_type_mask = cnt << 8; 4296 u32 deliver_error_code_mask = 4297 exception_type_mask != INTR_TYPE_HARD_EXCEPTION ? 4298 INTR_INFO_DELIVER_CODE_MASK : 0; 4299 4300 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4301 exception_type_mask | GP_VECTOR; 4302 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4303 ent_intr_info); 4304 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4305 test_vmx_invalid_controls(); 4306 report_prefix_pop(); 4307 } 4308 report_prefix_pop(); 4309 4310 /* 4311 * deliver-error-code is 1 iff the the vector 4312 * indicates an exception that would normally deliver an error code 4313 */ 4314 report_prefix_push("error code <-> vector delivers error code"); 4315 for (cnt = 0; cnt < 32; cnt++) { 4316 bool has_error_code = false; 4317 u32 deliver_error_code_mask; 4318 4319 switch (cnt) { 4320 case DF_VECTOR: 4321 case TS_VECTOR: 4322 case NP_VECTOR: 4323 case SS_VECTOR: 4324 case GP_VECTOR: 4325 case PF_VECTOR: 4326 case AC_VECTOR: 4327 has_error_code = true; 4328 case CP_VECTOR: 4329 /* Some CPUs have error code and some do not, skip */ 4330 continue; 4331 } 4332 4333 /* Negative case */ 4334 deliver_error_code_mask = has_error_code ? 4335 0 : 4336 INTR_INFO_DELIVER_CODE_MASK; 4337 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4338 INTR_TYPE_HARD_EXCEPTION | cnt; 4339 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4340 ent_intr_info); 4341 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4342 test_vmx_invalid_controls(); 4343 report_prefix_pop(); 4344 4345 /* Positive case */ 4346 deliver_error_code_mask = has_error_code ? 4347 INTR_INFO_DELIVER_CODE_MASK : 4348 0; 4349 ent_intr_info = ent_intr_info_base | deliver_error_code_mask | 4350 INTR_TYPE_HARD_EXCEPTION | cnt; 4351 report_prefix_pushf("VM-entry intr info=0x%x [+]", 4352 ent_intr_info); 4353 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4354 test_vmx_valid_controls(); 4355 report_prefix_pop(); 4356 } 4357 report_prefix_pop(); 4358 4359 /* Reserved bits in the field (30:12) are 0. */ 4360 report_prefix_push("reserved bits clear"); 4361 for (cnt = 12; cnt <= 30; cnt++) { 4362 ent_intr_info = ent_intr_info_base | 4363 INTR_INFO_DELIVER_CODE_MASK | 4364 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR | 4365 (1U << cnt); 4366 report_prefix_pushf("VM-entry intr info=0x%x [-]", 4367 ent_intr_info); 4368 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4369 test_vmx_invalid_controls(); 4370 report_prefix_pop(); 4371 } 4372 report_prefix_pop(); 4373 4374 /* 4375 * If deliver-error-code is 1 4376 * bits 31:16 of the VM-entry exception error-code field are 0. 4377 */ 4378 ent_intr_info = ent_intr_info_base | INTR_INFO_DELIVER_CODE_MASK | 4379 INTR_TYPE_HARD_EXCEPTION | GP_VECTOR; 4380 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4381 "VM-entry exception error code[31:16] clear", 4382 ent_intr_info); 4383 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4384 for (cnt = 16; cnt <= 31; cnt++) { 4385 ent_intr_err = 1U << cnt; 4386 report_prefix_pushf("VM-entry intr error=0x%x [-]", 4387 ent_intr_err); 4388 vmcs_write(ENT_INTR_ERROR, ent_intr_err); 4389 test_vmx_invalid_controls(); 4390 report_prefix_pop(); 4391 } 4392 vmcs_write(ENT_INTR_ERROR, 0x00000000); 4393 report_prefix_pop(); 4394 4395 /* 4396 * If the interruption type is software interrupt, software exception, 4397 * or privileged software exception, the VM-entry instruction-length 4398 * field is in the range 0 - 15. 4399 */ 4400 4401 for (cnt = 0; cnt < 3; cnt++) { 4402 switch (cnt) { 4403 case 0: 4404 ent_intr_info = ent_intr_info_base | 4405 INTR_TYPE_SOFT_INTR; 4406 break; 4407 case 1: 4408 ent_intr_info = ent_intr_info_base | 4409 INTR_TYPE_SOFT_EXCEPTION; 4410 break; 4411 case 2: 4412 ent_intr_info = ent_intr_info_base | 4413 INTR_TYPE_PRIV_SW_EXCEPTION; 4414 break; 4415 } 4416 report_prefix_pushf("%s, VM-entry intr info=0x%x", 4417 "VM-entry instruction-length check", 4418 ent_intr_info); 4419 vmcs_write(ENT_INTR_INFO, ent_intr_info); 4420 4421 /* Instruction length set to -1 (0xFFFFFFFF) should fail */ 4422 ent_intr_len = -1; 4423 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4424 ent_intr_len); 4425 vmcs_write(ENT_INST_LEN, ent_intr_len); 4426 test_vmx_invalid_controls(); 4427 report_prefix_pop(); 4428 4429 /* Instruction length set to 16 should fail */ 4430 ent_intr_len = 0x00000010; 4431 report_prefix_pushf("VM-entry intr length = 0x%x [-]", 4432 ent_intr_len); 4433 vmcs_write(ENT_INST_LEN, 0x00000010); 4434 test_vmx_invalid_controls(); 4435 report_prefix_pop(); 4436 4437 report_prefix_pop(); 4438 } 4439 4440 /* Cleanup */ 4441 vmcs_write(ENT_INTR_INFO, ent_intr_info_save); 4442 vmcs_write(ENT_INTR_ERROR, ent_intr_error_save); 4443 vmcs_write(ENT_INST_LEN, ent_inst_len_save); 4444 vmcs_write(CPU_EXEC_CTRL0, primary_save); 4445 vmcs_write(CPU_EXEC_CTRL1, secondary_save); 4446 vmcs_write(GUEST_CR0, guest_cr0_save); 4447 report_prefix_pop(); 4448 } 4449 4450 /* 4451 * Test interesting vTPR values for a given TPR threshold. 4452 */ 4453 static void test_vtpr_values(unsigned threshold) 4454 { 4455 try_tpr_threshold_and_vtpr(threshold, (threshold - 1) << 4); 4456 try_tpr_threshold_and_vtpr(threshold, threshold << 4); 4457 try_tpr_threshold_and_vtpr(threshold, (threshold + 1) << 4); 4458 } 4459 4460 static void try_tpr_threshold(unsigned threshold) 4461 { 4462 bool valid = true; 4463 4464 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4465 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4466 4467 if ((primary & CPU_TPR_SHADOW) && !((primary & CPU_SECONDARY) && 4468 (secondary & CPU_VINTD))) 4469 valid = !(threshold >> 4); 4470 4471 set_vtpr(-1); 4472 vmcs_write(TPR_THRESHOLD, threshold); 4473 report_prefix_pushf("TPR threshold 0x%x, VTPR.class 0xf", threshold); 4474 if (valid) 4475 test_vmx_valid_controls(); 4476 else 4477 test_vmx_invalid_controls(); 4478 report_prefix_pop(); 4479 4480 if (valid) 4481 test_vtpr_values(threshold); 4482 } 4483 4484 /* 4485 * Test interesting TPR threshold values. 4486 */ 4487 static void test_tpr_threshold_values(void) 4488 { 4489 unsigned i; 4490 4491 for (i = 0; i < 0x10; i++) 4492 try_tpr_threshold(i); 4493 for (i = 4; i < 32; i++) 4494 try_tpr_threshold(1u << i); 4495 try_tpr_threshold(-1u); 4496 try_tpr_threshold(0x7fffffff); 4497 } 4498 4499 /* 4500 * This test covers the following two VM entry checks: 4501 * 4502 * i) If the "use TPR shadow" VM-execution control is 1 and the 4503 * "virtual-interrupt delivery" VM-execution control is 0, bits 4504 * 31:4 of the TPR threshold VM-execution control field must 4505 be 0. 4506 * [Intel SDM] 4507 * 4508 * ii) If the "use TPR shadow" VM-execution control is 1, the 4509 * "virtual-interrupt delivery" VM-execution control is 0 4510 * and the "virtualize APIC accesses" VM-execution control 4511 * is 0, the value of bits 3:0 of the TPR threshold VM-execution 4512 * control field must not be greater than the value of bits 4513 * 7:4 of VTPR. 4514 * [Intel SDM] 4515 */ 4516 static void test_tpr_threshold(void) 4517 { 4518 u32 primary = vmcs_read(CPU_EXEC_CTRL0); 4519 u64 apic_virt_addr = vmcs_read(APIC_VIRT_ADDR); 4520 u64 threshold = vmcs_read(TPR_THRESHOLD); 4521 void *virtual_apic_page; 4522 4523 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) 4524 return; 4525 4526 virtual_apic_page = alloc_page(); 4527 memset(virtual_apic_page, 0xff, PAGE_SIZE); 4528 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 4529 4530 vmcs_write(CPU_EXEC_CTRL0, primary & ~(CPU_TPR_SHADOW | CPU_SECONDARY)); 4531 report_prefix_pushf("Use TPR shadow disabled, secondary controls disabled"); 4532 test_tpr_threshold_values(); 4533 report_prefix_pop(); 4534 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | CPU_TPR_SHADOW); 4535 report_prefix_pushf("Use TPR shadow enabled, secondary controls disabled"); 4536 test_tpr_threshold_values(); 4537 report_prefix_pop(); 4538 4539 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4540 (ctrl_cpu_rev[1].clr & (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)))) 4541 goto out; 4542 u32 secondary = vmcs_read(CPU_EXEC_CTRL1); 4543 4544 if (ctrl_cpu_rev[1].clr & CPU_VINTD) { 4545 vmcs_write(CPU_EXEC_CTRL1, CPU_VINTD); 4546 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4547 test_tpr_threshold_values(); 4548 report_prefix_pop(); 4549 4550 vmcs_write(CPU_EXEC_CTRL0, 4551 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4552 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses disabled"); 4553 test_tpr_threshold_values(); 4554 report_prefix_pop(); 4555 } 4556 4557 if (ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES) { 4558 vmcs_write(CPU_EXEC_CTRL0, 4559 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4560 vmcs_write(CPU_EXEC_CTRL1, CPU_VIRT_APIC_ACCESSES); 4561 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4562 test_tpr_threshold_values(); 4563 report_prefix_pop(); 4564 4565 vmcs_write(CPU_EXEC_CTRL0, 4566 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4567 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4568 test_tpr_threshold_values(); 4569 report_prefix_pop(); 4570 } 4571 4572 if ((ctrl_cpu_rev[1].clr & 4573 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) == 4574 (CPU_VINTD | CPU_VIRT_APIC_ACCESSES)) { 4575 vmcs_write(CPU_EXEC_CTRL0, 4576 vmcs_read(CPU_EXEC_CTRL0) & ~CPU_SECONDARY); 4577 vmcs_write(CPU_EXEC_CTRL1, 4578 CPU_VINTD | CPU_VIRT_APIC_ACCESSES); 4579 report_prefix_pushf("Use TPR shadow enabled; secondary controls disabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4580 test_tpr_threshold_values(); 4581 report_prefix_pop(); 4582 4583 vmcs_write(CPU_EXEC_CTRL0, 4584 vmcs_read(CPU_EXEC_CTRL0) | CPU_SECONDARY); 4585 report_prefix_pushf("Use TPR shadow enabled; secondary controls enabled; virtual-interrupt delivery enabled; virtualize APIC accesses enabled"); 4586 test_tpr_threshold_values(); 4587 report_prefix_pop(); 4588 } 4589 4590 vmcs_write(CPU_EXEC_CTRL1, secondary); 4591 out: 4592 vmcs_write(TPR_THRESHOLD, threshold); 4593 vmcs_write(APIC_VIRT_ADDR, apic_virt_addr); 4594 vmcs_write(CPU_EXEC_CTRL0, primary); 4595 } 4596 4597 /* 4598 * This test verifies the following two vmentry checks: 4599 * 4600 * If the "NMI exiting" VM-execution control is 0, "Virtual NMIs" 4601 * VM-execution control must be 0. 4602 * [Intel SDM] 4603 * 4604 * If the "virtual NMIs" VM-execution control is 0, the "NMI-window 4605 * exiting" VM-execution control must be 0. 4606 * [Intel SDM] 4607 */ 4608 static void test_nmi_ctrls(void) 4609 { 4610 u32 pin_ctrls, cpu_ctrls0, test_pin_ctrls, test_cpu_ctrls0; 4611 4612 if ((ctrl_pin_rev.clr & (PIN_NMI | PIN_VIRT_NMI)) != 4613 (PIN_NMI | PIN_VIRT_NMI)) { 4614 printf("NMI exiting and Virtual NMIs are not supported !\n"); 4615 return; 4616 } 4617 4618 /* Save the controls so that we can restore them after our tests */ 4619 pin_ctrls = vmcs_read(PIN_CONTROLS); 4620 cpu_ctrls0 = vmcs_read(CPU_EXEC_CTRL0); 4621 4622 test_pin_ctrls = pin_ctrls & ~(PIN_NMI | PIN_VIRT_NMI); 4623 test_cpu_ctrls0 = cpu_ctrls0 & ~CPU_NMI_WINDOW; 4624 4625 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4626 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs disabled"); 4627 test_vmx_valid_controls(); 4628 report_prefix_pop(); 4629 4630 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_VIRT_NMI); 4631 report_prefix_pushf("NMI-exiting disabled, virtual-NMIs enabled"); 4632 test_vmx_invalid_controls(); 4633 report_prefix_pop(); 4634 4635 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4636 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs enabled"); 4637 test_vmx_valid_controls(); 4638 report_prefix_pop(); 4639 4640 vmcs_write(PIN_CONTROLS, test_pin_ctrls | PIN_NMI); 4641 report_prefix_pushf("NMI-exiting enabled, virtual-NMIs disabled"); 4642 test_vmx_valid_controls(); 4643 report_prefix_pop(); 4644 4645 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 4646 report_info("NMI-window exiting is not supported, skipping..."); 4647 goto done; 4648 } 4649 4650 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4651 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4652 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting enabled"); 4653 test_vmx_invalid_controls(); 4654 report_prefix_pop(); 4655 4656 vmcs_write(PIN_CONTROLS, test_pin_ctrls); 4657 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4658 report_prefix_pushf("Virtual-NMIs disabled, NMI-window-exiting disabled"); 4659 test_vmx_valid_controls(); 4660 report_prefix_pop(); 4661 4662 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4663 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0 | CPU_NMI_WINDOW); 4664 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting enabled"); 4665 test_vmx_valid_controls(); 4666 report_prefix_pop(); 4667 4668 vmcs_write(PIN_CONTROLS, test_pin_ctrls | (PIN_NMI | PIN_VIRT_NMI)); 4669 vmcs_write(CPU_EXEC_CTRL0, test_cpu_ctrls0); 4670 report_prefix_pushf("Virtual-NMIs enabled, NMI-window-exiting disabled"); 4671 test_vmx_valid_controls(); 4672 report_prefix_pop(); 4673 4674 /* Restore the controls to their original values */ 4675 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrls0); 4676 done: 4677 vmcs_write(PIN_CONTROLS, pin_ctrls); 4678 } 4679 4680 static void test_eptp_ad_bit(u64 eptp, bool ctrl) 4681 { 4682 vmcs_write(EPTP, eptp); 4683 report_prefix_pushf("Enable-EPT enabled; EPT accessed and dirty flag %s", 4684 (eptp & EPTP_AD_FLAG) ? "1": "0"); 4685 if (ctrl) 4686 test_vmx_valid_controls(); 4687 else 4688 test_vmx_invalid_controls(); 4689 report_prefix_pop(); 4690 4691 } 4692 4693 /* 4694 * 1. If the "enable EPT" VM-execution control is 1, the "EPTP VM-execution" 4695 * control field must satisfy the following checks: 4696 * 4697 * - The EPT memory type (bits 2:0) must be a value supported by the 4698 * processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR. 4699 * - Bits 5:3 (1 less than the EPT page-walk length) must indicate a 4700 * supported EPT page-walk length. 4701 * - Bit 6 (enable bit for accessed and dirty flags for EPT) must be 4702 * 0 if bit 21 of the IA32_VMX_EPT_VPID_CAP MSR is read as 0, 4703 * indicating that the processor does not support accessed and dirty 4704 * dirty flags for EPT. 4705 * - Reserved bits 11:7 and 63:N (where N is the processor's 4706 * physical-address width) must all be 0. 4707 * 4708 * 2. If the "unrestricted guest" VM-execution control is 1, the 4709 * "enable EPT" VM-execution control must also be 1. 4710 */ 4711 static void test_ept_eptp(void) 4712 { 4713 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4714 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4715 u64 eptp_saved = vmcs_read(EPTP); 4716 u32 primary = primary_saved; 4717 u32 secondary = secondary_saved; 4718 u64 msr, eptp = eptp_saved; 4719 bool un_cache = false; 4720 bool wr_bk = false; 4721 bool ctrl; 4722 u32 i, maxphysaddr; 4723 u64 j, resv_bits_mask = 0; 4724 4725 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4726 (ctrl_cpu_rev[1].clr & CPU_EPT))) { 4727 printf("\"CPU secondary\" and/or \"enable EPT\" execution controls are not supported !\n"); 4728 return; 4729 } 4730 4731 /* 4732 * Memory type (bits 2:0) 4733 */ 4734 msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP); 4735 if (msr & EPT_CAP_UC) 4736 un_cache = true; 4737 if (msr & EPT_CAP_WB) 4738 wr_bk = true; 4739 4740 /* Support for 4-level EPT is mandatory. */ 4741 report(msr & EPT_CAP_PWL4, "4-level EPT support check"); 4742 4743 primary |= CPU_SECONDARY; 4744 vmcs_write(CPU_EXEC_CTRL0, primary); 4745 secondary |= CPU_EPT; 4746 vmcs_write(CPU_EXEC_CTRL1, secondary); 4747 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4748 (3ul << EPTP_PG_WALK_LEN_SHIFT); 4749 vmcs_write(EPTP, eptp); 4750 4751 for (i = 0; i < 8; i++) { 4752 if (i == 0) { 4753 if (un_cache) { 4754 report_info("EPT paging structure memory-type is Un-cacheable\n"); 4755 ctrl = true; 4756 } else { 4757 ctrl = false; 4758 } 4759 } else if (i == 6) { 4760 if (wr_bk) { 4761 report_info("EPT paging structure memory-type is Write-back\n"); 4762 ctrl = true; 4763 } else { 4764 ctrl = false; 4765 } 4766 } else { 4767 ctrl = false; 4768 } 4769 4770 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | i; 4771 vmcs_write(EPTP, eptp); 4772 report_prefix_pushf("Enable-EPT enabled; EPT memory type %lu", 4773 eptp & EPT_MEM_TYPE_MASK); 4774 if (ctrl) 4775 test_vmx_valid_controls(); 4776 else 4777 test_vmx_invalid_controls(); 4778 report_prefix_pop(); 4779 } 4780 4781 eptp = (eptp & ~EPT_MEM_TYPE_MASK) | 6ul; 4782 4783 /* 4784 * Page walk length (bits 5:3). Note, the value in VMCS.EPTP "is 1 4785 * less than the EPT page-walk length". 4786 */ 4787 for (i = 0; i < 8; i++) { 4788 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4789 (i << EPTP_PG_WALK_LEN_SHIFT); 4790 if (i == 3 || (i == 4 && (msr & EPT_CAP_PWL5))) 4791 ctrl = true; 4792 else 4793 ctrl = false; 4794 4795 vmcs_write(EPTP, eptp); 4796 report_prefix_pushf("Enable-EPT enabled; EPT page walk length %lu", 4797 eptp & EPTP_PG_WALK_LEN_MASK); 4798 if (ctrl) 4799 test_vmx_valid_controls(); 4800 else 4801 test_vmx_invalid_controls(); 4802 report_prefix_pop(); 4803 } 4804 4805 eptp = (eptp & ~EPTP_PG_WALK_LEN_MASK) | 4806 3ul << EPTP_PG_WALK_LEN_SHIFT; 4807 4808 /* 4809 * Accessed and dirty flag (bit 6) 4810 */ 4811 if (msr & EPT_CAP_AD_FLAG) { 4812 report_info("Processor supports accessed and dirty flag"); 4813 eptp &= ~EPTP_AD_FLAG; 4814 test_eptp_ad_bit(eptp, true); 4815 4816 eptp |= EPTP_AD_FLAG; 4817 test_eptp_ad_bit(eptp, true); 4818 } else { 4819 report_info("Processor does not supports accessed and dirty flag"); 4820 eptp &= ~EPTP_AD_FLAG; 4821 test_eptp_ad_bit(eptp, true); 4822 4823 eptp |= EPTP_AD_FLAG; 4824 test_eptp_ad_bit(eptp, false); 4825 } 4826 4827 /* 4828 * Reserved bits [11:7] and [63:N] 4829 */ 4830 for (i = 0; i < 32; i++) { 4831 eptp = (eptp & 4832 ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)) | 4833 (i << EPTP_RESERV_BITS_SHIFT); 4834 vmcs_write(EPTP, eptp); 4835 report_prefix_pushf("Enable-EPT enabled; reserved bits [11:7] %lu", 4836 (eptp >> EPTP_RESERV_BITS_SHIFT) & 4837 EPTP_RESERV_BITS_MASK); 4838 if (i == 0) 4839 test_vmx_valid_controls(); 4840 else 4841 test_vmx_invalid_controls(); 4842 report_prefix_pop(); 4843 } 4844 4845 eptp = (eptp & ~(EPTP_RESERV_BITS_MASK << EPTP_RESERV_BITS_SHIFT)); 4846 4847 maxphysaddr = cpuid_maxphyaddr(); 4848 for (i = 0; i < (63 - maxphysaddr + 1); i++) { 4849 resv_bits_mask |= 1ul << i; 4850 } 4851 4852 for (j = maxphysaddr - 1; j <= 63; j++) { 4853 eptp = (eptp & ~(resv_bits_mask << maxphysaddr)) | 4854 (j < maxphysaddr ? 0 : 1ul << j); 4855 vmcs_write(EPTP, eptp); 4856 report_prefix_pushf("Enable-EPT enabled; reserved bits [63:N] %lu", 4857 (eptp >> maxphysaddr) & resv_bits_mask); 4858 if (j < maxphysaddr) 4859 test_vmx_valid_controls(); 4860 else 4861 test_vmx_invalid_controls(); 4862 report_prefix_pop(); 4863 } 4864 4865 secondary &= ~(CPU_EPT | CPU_URG); 4866 vmcs_write(CPU_EXEC_CTRL1, secondary); 4867 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest disabled"); 4868 test_vmx_valid_controls(); 4869 report_prefix_pop(); 4870 4871 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) 4872 goto skip_unrestricted_guest; 4873 4874 secondary |= CPU_URG; 4875 vmcs_write(CPU_EXEC_CTRL1, secondary); 4876 report_prefix_pushf("Enable-EPT disabled, unrestricted-guest enabled"); 4877 test_vmx_invalid_controls(); 4878 report_prefix_pop(); 4879 4880 secondary |= CPU_EPT; 4881 setup_dummy_ept(); 4882 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest enabled"); 4883 test_vmx_valid_controls(); 4884 report_prefix_pop(); 4885 4886 skip_unrestricted_guest: 4887 secondary &= ~CPU_URG; 4888 vmcs_write(CPU_EXEC_CTRL1, secondary); 4889 report_prefix_pushf("Enable-EPT enabled, unrestricted-guest disabled"); 4890 test_vmx_valid_controls(); 4891 report_prefix_pop(); 4892 4893 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4894 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4895 vmcs_write(EPTP, eptp_saved); 4896 } 4897 4898 /* 4899 * If the 'enable PML' VM-execution control is 1, the 'enable EPT' 4900 * VM-execution control must also be 1. In addition, the PML address 4901 * must satisfy the following checks: 4902 * 4903 * * Bits 11:0 of the address must be 0. 4904 * * The address should not set any bits beyond the processor's 4905 * physical-address width. 4906 * 4907 * [Intel SDM] 4908 */ 4909 static void test_pml(void) 4910 { 4911 u32 primary_saved = vmcs_read(CPU_EXEC_CTRL0); 4912 u32 secondary_saved = vmcs_read(CPU_EXEC_CTRL1); 4913 u32 primary = primary_saved; 4914 u32 secondary = secondary_saved; 4915 4916 if (!((ctrl_cpu_rev[0].clr & CPU_SECONDARY) && 4917 (ctrl_cpu_rev[1].clr & CPU_EPT) && (ctrl_cpu_rev[1].clr & CPU_PML))) { 4918 printf("\"Secondary execution\" control or \"enable EPT\" control or \"enable PML\" control is not supported !\n"); 4919 return; 4920 } 4921 4922 primary |= CPU_SECONDARY; 4923 vmcs_write(CPU_EXEC_CTRL0, primary); 4924 secondary &= ~(CPU_PML | CPU_EPT); 4925 vmcs_write(CPU_EXEC_CTRL1, secondary); 4926 report_prefix_pushf("enable-PML disabled, enable-EPT disabled"); 4927 test_vmx_valid_controls(); 4928 report_prefix_pop(); 4929 4930 secondary |= CPU_PML; 4931 vmcs_write(CPU_EXEC_CTRL1, secondary); 4932 report_prefix_pushf("enable-PML enabled, enable-EPT disabled"); 4933 test_vmx_invalid_controls(); 4934 report_prefix_pop(); 4935 4936 secondary |= CPU_EPT; 4937 setup_dummy_ept(); 4938 report_prefix_pushf("enable-PML enabled, enable-EPT enabled"); 4939 test_vmx_valid_controls(); 4940 report_prefix_pop(); 4941 4942 secondary &= ~CPU_PML; 4943 vmcs_write(CPU_EXEC_CTRL1, secondary); 4944 report_prefix_pushf("enable-PML disabled, enable EPT enabled"); 4945 test_vmx_valid_controls(); 4946 report_prefix_pop(); 4947 4948 test_vmcs_addr_reference(CPU_PML, PMLADDR, "PML address", "PML", 4949 PAGE_SIZE, false, false); 4950 4951 vmcs_write(CPU_EXEC_CTRL0, primary_saved); 4952 vmcs_write(CPU_EXEC_CTRL1, secondary_saved); 4953 } 4954 4955 /* 4956 * If the "activate VMX-preemption timer" VM-execution control is 0, the 4957 * the "save VMX-preemption timer value" VM-exit control must also be 0. 4958 * 4959 * [Intel SDM] 4960 */ 4961 static void test_vmx_preemption_timer(void) 4962 { 4963 u32 saved_pin = vmcs_read(PIN_CONTROLS); 4964 u32 saved_exit = vmcs_read(EXI_CONTROLS); 4965 u32 pin = saved_pin; 4966 u32 exit = saved_exit; 4967 4968 if (!((ctrl_exit_rev.clr & EXI_SAVE_PREEMPT) || 4969 (ctrl_pin_rev.clr & PIN_PREEMPT))) { 4970 printf("\"Save-VMX-preemption-timer\" control and/or \"Enable-VMX-preemption-timer\" control is not supported\n"); 4971 return; 4972 } 4973 4974 pin |= PIN_PREEMPT; 4975 vmcs_write(PIN_CONTROLS, pin); 4976 exit &= ~EXI_SAVE_PREEMPT; 4977 vmcs_write(EXI_CONTROLS, exit); 4978 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer disabled"); 4979 test_vmx_valid_controls(); 4980 report_prefix_pop(); 4981 4982 exit |= EXI_SAVE_PREEMPT; 4983 vmcs_write(EXI_CONTROLS, exit); 4984 report_prefix_pushf("enable-VMX-preemption-timer enabled, save-VMX-preemption-timer enabled"); 4985 test_vmx_valid_controls(); 4986 report_prefix_pop(); 4987 4988 pin &= ~PIN_PREEMPT; 4989 vmcs_write(PIN_CONTROLS, pin); 4990 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer enabled"); 4991 test_vmx_invalid_controls(); 4992 report_prefix_pop(); 4993 4994 exit &= ~EXI_SAVE_PREEMPT; 4995 vmcs_write(EXI_CONTROLS, exit); 4996 report_prefix_pushf("enable-VMX-preemption-timer disabled, save-VMX-preemption-timer disabled"); 4997 test_vmx_valid_controls(); 4998 report_prefix_pop(); 4999 5000 vmcs_write(PIN_CONTROLS, saved_pin); 5001 vmcs_write(EXI_CONTROLS, saved_exit); 5002 } 5003 5004 extern unsigned char test_mtf1; 5005 extern unsigned char test_mtf2; 5006 extern unsigned char test_mtf3; 5007 extern unsigned char test_mtf4; 5008 5009 static void test_mtf_guest(void) 5010 { 5011 asm ("vmcall;\n\t" 5012 "out %al, $0x80;\n\t" 5013 "test_mtf1:\n\t" 5014 "vmcall;\n\t" 5015 "out %al, $0x80;\n\t" 5016 "test_mtf2:\n\t" 5017 /* 5018 * Prepare for the 'MOV CR3' test. Attempt to induce a 5019 * general-protection fault by moving a non-canonical address into 5020 * CR3. The 'MOV CR3' instruction does not take an imm64 operand, 5021 * so we must MOV the desired value into a register first. 5022 * 5023 * MOV RAX is done before the VMCALL such that MTF is only enabled 5024 * for the instruction under test. 5025 */ 5026 "mov $0xaaaaaaaaaaaaaaaa, %rax;\n\t" 5027 "vmcall;\n\t" 5028 "mov %rax, %cr3;\n\t" 5029 "test_mtf3:\n\t" 5030 "vmcall;\n\t" 5031 /* 5032 * ICEBP/INT1 instruction. Though the instruction is now 5033 * documented, don't rely on assemblers enumerating the 5034 * instruction. Resort to hand assembly. 5035 */ 5036 ".byte 0xf1;\n\t" 5037 "vmcall;\n\t" 5038 "test_mtf4:\n\t" 5039 "mov $0, %eax;\n\t"); 5040 } 5041 5042 static void test_mtf_gp_handler(struct ex_regs *regs) 5043 { 5044 regs->rip = (unsigned long) &test_mtf3; 5045 } 5046 5047 static void test_mtf_db_handler(struct ex_regs *regs) 5048 { 5049 } 5050 5051 static void enable_mtf(void) 5052 { 5053 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5054 5055 vmcs_write(CPU_EXEC_CTRL0, ctrl0 | CPU_MTF); 5056 } 5057 5058 static void disable_mtf(void) 5059 { 5060 u32 ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 5061 5062 vmcs_write(CPU_EXEC_CTRL0, ctrl0 & ~CPU_MTF); 5063 } 5064 5065 static void enable_tf(void) 5066 { 5067 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5068 5069 vmcs_write(GUEST_RFLAGS, rflags | X86_EFLAGS_TF); 5070 } 5071 5072 static void disable_tf(void) 5073 { 5074 unsigned long rflags = vmcs_read(GUEST_RFLAGS); 5075 5076 vmcs_write(GUEST_RFLAGS, rflags & ~X86_EFLAGS_TF); 5077 } 5078 5079 static void report_mtf(const char *insn_name, unsigned long exp_rip) 5080 { 5081 unsigned long rip = vmcs_read(GUEST_RIP); 5082 5083 assert_exit_reason(VMX_MTF); 5084 report(rip == exp_rip, "MTF VM-exit after %s. RIP: 0x%lx (expected 0x%lx)", 5085 insn_name, rip, exp_rip); 5086 } 5087 5088 static void vmx_mtf_test(void) 5089 { 5090 unsigned long pending_dbg; 5091 handler old_gp, old_db; 5092 5093 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5094 printf("CPU does not support the 'monitor trap flag' processor-based VM-execution control.\n"); 5095 return; 5096 } 5097 5098 test_set_guest(test_mtf_guest); 5099 5100 /* Expect an MTF VM-exit after OUT instruction */ 5101 enter_guest(); 5102 skip_exit_vmcall(); 5103 5104 enable_mtf(); 5105 enter_guest(); 5106 report_mtf("OUT", (unsigned long) &test_mtf1); 5107 disable_mtf(); 5108 5109 /* 5110 * Concurrent #DB trap and MTF on instruction boundary. Expect MTF 5111 * VM-exit with populated 'pending debug exceptions' VMCS field. 5112 */ 5113 enter_guest(); 5114 skip_exit_vmcall(); 5115 5116 enable_mtf(); 5117 enable_tf(); 5118 5119 enter_guest(); 5120 report_mtf("OUT", (unsigned long) &test_mtf2); 5121 pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 5122 report(pending_dbg & DR_STEP, 5123 "'pending debug exceptions' field after MTF VM-exit: 0x%lx (expected 0x%lx)", 5124 pending_dbg, (unsigned long) DR_STEP); 5125 5126 disable_mtf(); 5127 disable_tf(); 5128 vmcs_write(GUEST_PENDING_DEBUG, 0); 5129 5130 /* 5131 * #GP exception takes priority over MTF. Expect MTF VM-exit with RIP 5132 * advanced to first instruction of #GP handler. 5133 */ 5134 enter_guest(); 5135 skip_exit_vmcall(); 5136 5137 old_gp = handle_exception(GP_VECTOR, test_mtf_gp_handler); 5138 5139 enable_mtf(); 5140 enter_guest(); 5141 report_mtf("MOV CR3", (unsigned long) get_idt_addr(&boot_idt[GP_VECTOR])); 5142 disable_mtf(); 5143 5144 /* 5145 * Concurrent MTF and privileged software exception (i.e. ICEBP/INT1). 5146 * MTF should follow the delivery of #DB trap, though the SDM doesn't 5147 * provide clear indication of the relative priority. 5148 */ 5149 enter_guest(); 5150 skip_exit_vmcall(); 5151 5152 handle_exception(GP_VECTOR, old_gp); 5153 old_db = handle_exception(DB_VECTOR, test_mtf_db_handler); 5154 5155 enable_mtf(); 5156 enter_guest(); 5157 report_mtf("INT1", (unsigned long) get_idt_addr(&boot_idt[DB_VECTOR])); 5158 disable_mtf(); 5159 5160 enter_guest(); 5161 skip_exit_vmcall(); 5162 handle_exception(DB_VECTOR, old_db); 5163 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | INTR_TYPE_OTHER_EVENT); 5164 enter_guest(); 5165 report_mtf("injected MTF", (unsigned long) &test_mtf4); 5166 enter_guest(); 5167 } 5168 5169 extern char vmx_mtf_pdpte_guest_begin; 5170 extern char vmx_mtf_pdpte_guest_end; 5171 5172 asm("vmx_mtf_pdpte_guest_begin:\n\t" 5173 "mov %cr0, %rax\n\t" /* save CR0 with PG=1 */ 5174 "vmcall\n\t" /* on return from this CR0.PG=0 */ 5175 "mov %rax, %cr0\n\t" /* restore CR0.PG=1 to enter PAE mode */ 5176 "vmcall\n\t" 5177 "retq\n\t" 5178 "vmx_mtf_pdpte_guest_end:"); 5179 5180 static void vmx_mtf_pdpte_test(void) 5181 { 5182 void *test_mtf_pdpte_guest; 5183 pteval_t *pdpt; 5184 u32 guest_ar_cs; 5185 u64 guest_efer; 5186 pteval_t *pte; 5187 u64 guest_cr0; 5188 u64 guest_cr3; 5189 u64 guest_cr4; 5190 u64 ent_ctls; 5191 int i; 5192 5193 if (setup_ept(false)) 5194 return; 5195 5196 if (!(ctrl_cpu_rev[0].clr & CPU_MTF)) { 5197 printf("CPU does not support 'monitor trap flag.'\n"); 5198 return; 5199 } 5200 5201 if (!(ctrl_cpu_rev[1].clr & CPU_URG)) { 5202 printf("CPU does not support 'unrestricted guest.'\n"); 5203 return; 5204 } 5205 5206 vmcs_write(EXC_BITMAP, ~0); 5207 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | CPU_URG); 5208 5209 /* 5210 * Copy the guest code to an identity-mapped page. 5211 */ 5212 test_mtf_pdpte_guest = alloc_page(); 5213 memcpy(test_mtf_pdpte_guest, &vmx_mtf_pdpte_guest_begin, 5214 &vmx_mtf_pdpte_guest_end - &vmx_mtf_pdpte_guest_begin); 5215 5216 test_set_guest(test_mtf_pdpte_guest); 5217 5218 enter_guest(); 5219 skip_exit_vmcall(); 5220 5221 /* 5222 * Put the guest in non-paged 32-bit protected mode, ready to enter 5223 * PAE mode when CR0.PG is set. CR4.PAE will already have been set 5224 * when the guest started out in long mode. 5225 */ 5226 ent_ctls = vmcs_read(ENT_CONTROLS); 5227 vmcs_write(ENT_CONTROLS, ent_ctls & ~ENT_GUEST_64); 5228 5229 guest_efer = vmcs_read(GUEST_EFER); 5230 vmcs_write(GUEST_EFER, guest_efer & ~(EFER_LMA | EFER_LME)); 5231 5232 /* 5233 * Set CS access rights bits for 32-bit protected mode: 5234 * 3:0 B execute/read/accessed 5235 * 4 1 code or data 5236 * 6:5 0 descriptor privilege level 5237 * 7 1 present 5238 * 11:8 0 reserved 5239 * 12 0 available for use by system software 5240 * 13 0 64 bit mode not active 5241 * 14 1 default operation size 32-bit segment 5242 * 15 1 page granularity: segment limit in 4K units 5243 * 16 0 segment usable 5244 * 31:17 0 reserved 5245 */ 5246 guest_ar_cs = vmcs_read(GUEST_AR_CS); 5247 vmcs_write(GUEST_AR_CS, 0xc09b); 5248 5249 guest_cr0 = vmcs_read(GUEST_CR0); 5250 vmcs_write(GUEST_CR0, guest_cr0 & ~X86_CR0_PG); 5251 5252 guest_cr4 = vmcs_read(GUEST_CR4); 5253 vmcs_write(GUEST_CR4, guest_cr4 & ~X86_CR4_PCIDE); 5254 5255 guest_cr3 = vmcs_read(GUEST_CR3); 5256 5257 /* 5258 * Turn the 4-level page table into a PAE page table by following the 0th 5259 * PML4 entry to a PDPT page, and grab the first four PDPTEs from that 5260 * page. 5261 * 5262 * Why does this work? 5263 * 5264 * PAE uses 32-bit addressing which implies: 5265 * Bits 11:0 page offset 5266 * Bits 20:12 entry into 512-entry page table 5267 * Bits 29:21 entry into a 512-entry directory table 5268 * Bits 31:30 entry into the page directory pointer table. 5269 * Bits 63:32 zero 5270 * 5271 * As only 2 bits are needed to select the PDPTEs for the entire 5272 * 32-bit address space, take the first 4 PDPTEs in the level 3 page 5273 * directory pointer table. It doesn't matter which of these PDPTEs 5274 * are present because they must cover the guest code given that it 5275 * has already run successfully. 5276 * 5277 * Get a pointer to PTE for GVA=0 in the page directory pointer table 5278 */ 5279 pte = get_pte_level( 5280 (pgd_t *)phys_to_virt(guest_cr3 & ~X86_CR3_PCID_MASK), 0, 5281 PDPT_LEVEL); 5282 5283 /* 5284 * Need some memory for the 4-entry PAE page directory pointer 5285 * table. Use the end of the identity-mapped page where the guest code 5286 * is stored. There is definitely space as the guest code is only a 5287 * few bytes. 5288 */ 5289 pdpt = test_mtf_pdpte_guest + PAGE_SIZE - 4 * sizeof(pteval_t); 5290 5291 /* 5292 * Copy the first four PDPTEs into the PAE page table with reserved 5293 * bits cleared. Note that permission bits from the PML4E and PDPTE 5294 * are not propagated. 5295 */ 5296 for (i = 0; i < 4; i++) { 5297 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_RSVD_MASK), 5298 "PDPTE has invalid reserved bits"); 5299 TEST_ASSERT_EQ_MSG(0, (pte[i] & PDPTE64_PAGE_SIZE_MASK), 5300 "Cannot use 1GB super pages for PAE"); 5301 pdpt[i] = pte[i] & ~(PAE_PDPTE_RSVD_MASK); 5302 } 5303 vmcs_write(GUEST_CR3, virt_to_phys(pdpt)); 5304 5305 enable_mtf(); 5306 enter_guest(); 5307 assert_exit_reason(VMX_MTF); 5308 disable_mtf(); 5309 5310 /* 5311 * The four PDPTEs should have been loaded into the VMCS when 5312 * the guest set CR0.PG to enter PAE mode. 5313 */ 5314 for (i = 0; i < 4; i++) { 5315 u64 pdpte = vmcs_read(GUEST_PDPTE + 2 * i); 5316 5317 report(pdpte == pdpt[i], "PDPTE%d is 0x%lx (expected 0x%lx)", 5318 i, pdpte, pdpt[i]); 5319 } 5320 5321 /* 5322 * Now, try to enter the guest in PAE mode. If the PDPTEs in the 5323 * vmcs are wrong, this will fail. 5324 */ 5325 enter_guest(); 5326 skip_exit_vmcall(); 5327 5328 /* 5329 * Return guest to 64-bit mode and wrap up. 5330 */ 5331 vmcs_write(ENT_CONTROLS, ent_ctls); 5332 vmcs_write(GUEST_EFER, guest_efer); 5333 vmcs_write(GUEST_AR_CS, guest_ar_cs); 5334 vmcs_write(GUEST_CR0, guest_cr0); 5335 vmcs_write(GUEST_CR4, guest_cr4); 5336 vmcs_write(GUEST_CR3, guest_cr3); 5337 5338 enter_guest(); 5339 } 5340 5341 /* 5342 * Tests for VM-execution control fields 5343 */ 5344 static void test_vm_execution_ctls(void) 5345 { 5346 test_pin_based_ctls(); 5347 test_primary_processor_based_ctls(); 5348 test_secondary_processor_based_ctls(); 5349 test_cr3_targets(); 5350 test_io_bitmaps(); 5351 test_msr_bitmap(); 5352 test_apic_ctls(); 5353 test_tpr_threshold(); 5354 test_nmi_ctrls(); 5355 test_pml(); 5356 test_vpid(); 5357 test_ept_eptp(); 5358 test_vmx_preemption_timer(); 5359 } 5360 5361 /* 5362 * The following checks are performed for the VM-entry MSR-load address if 5363 * the VM-entry MSR-load count field is non-zero: 5364 * 5365 * - The lower 4 bits of the VM-entry MSR-load address must be 0. 5366 * The address should not set any bits beyond the processor's 5367 * physical-address width. 5368 * 5369 * - The address of the last byte in the VM-entry MSR-load area 5370 * should not set any bits beyond the processor's physical-address 5371 * width. The address of this last byte is VM-entry MSR-load address 5372 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5373 * uses more bits than the processor's physical-address width.) 5374 * 5375 * 5376 * [Intel SDM] 5377 */ 5378 static void test_entry_msr_load(void) 5379 { 5380 entry_msr_load = alloc_page(); 5381 u64 tmp; 5382 u32 entry_msr_ld_cnt = 1; 5383 int i; 5384 u32 addr_len = 64; 5385 5386 vmcs_write(ENT_MSR_LD_CNT, entry_msr_ld_cnt); 5387 5388 /* Check first 4 bits of VM-entry MSR-load address */ 5389 for (i = 0; i < 4; i++) { 5390 tmp = (u64)entry_msr_load | 1ull << i; 5391 vmcs_write(ENTER_MSR_LD_ADDR, tmp); 5392 report_prefix_pushf("VM-entry MSR-load addr [4:0] %lx", 5393 tmp & 0xf); 5394 test_vmx_invalid_controls(); 5395 report_prefix_pop(); 5396 } 5397 5398 if (basic.val & (1ul << 48)) 5399 addr_len = 32; 5400 5401 test_vmcs_addr_values("VM-entry-MSR-load address", 5402 ENTER_MSR_LD_ADDR, 16, false, false, 5403 4, addr_len - 1); 5404 5405 /* 5406 * Check last byte of VM-entry MSR-load address 5407 */ 5408 entry_msr_load = (struct vmx_msr_entry *)((u64)entry_msr_load & ~0xf); 5409 5410 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5411 i < 64; i++) { 5412 tmp = ((u64)entry_msr_load + entry_msr_ld_cnt * 16 - 1) | 5413 1ul << i; 5414 vmcs_write(ENTER_MSR_LD_ADDR, 5415 tmp - (entry_msr_ld_cnt * 16 - 1)); 5416 test_vmx_invalid_controls(); 5417 } 5418 5419 vmcs_write(ENT_MSR_LD_CNT, 2); 5420 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5421 test_vmx_invalid_controls(); 5422 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5423 test_vmx_valid_controls(); 5424 vmcs_write(ENTER_MSR_LD_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5425 test_vmx_valid_controls(); 5426 } 5427 5428 static struct vmx_state_area_test_data { 5429 u32 msr; 5430 u64 exp; 5431 bool enabled; 5432 } vmx_state_area_test_data; 5433 5434 static void guest_state_test_main(void) 5435 { 5436 u64 obs; 5437 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 5438 5439 while (1) { 5440 if (vmx_get_test_stage() == 2) 5441 break; 5442 5443 if (data->enabled) { 5444 obs = rdmsr(data->msr); 5445 report(data->exp == obs, 5446 "Guest state is 0x%lx (expected 0x%lx)", 5447 obs, data->exp); 5448 } 5449 5450 vmcall(); 5451 } 5452 5453 asm volatile("fnop"); 5454 } 5455 5456 static void test_guest_state(const char *test, bool xfail, u64 field, 5457 const char * field_name) 5458 { 5459 struct vmentry_result result; 5460 u8 abort_flags; 5461 5462 abort_flags = ABORT_ON_EARLY_VMENTRY_FAIL; 5463 if (!xfail) 5464 abort_flags = ABORT_ON_INVALID_GUEST_STATE; 5465 5466 __enter_guest(abort_flags, &result); 5467 5468 report(result.exit_reason.failed_vmentry == xfail && 5469 ((xfail && result.exit_reason.basic == VMX_FAIL_STATE) || 5470 (!xfail && result.exit_reason.basic == VMX_VMCALL)) && 5471 (!xfail || vmcs_read(EXI_QUALIFICATION) == ENTRY_FAIL_DEFAULT), 5472 "%s, %s = %lx", test, field_name, field); 5473 5474 if (!result.exit_reason.failed_vmentry) 5475 skip_exit_insn(); 5476 } 5477 5478 /* 5479 * Tests for VM-entry control fields 5480 */ 5481 static void test_vm_entry_ctls(void) 5482 { 5483 test_invalid_event_injection(); 5484 test_entry_msr_load(); 5485 } 5486 5487 /* 5488 * The following checks are performed for the VM-exit MSR-store address if 5489 * the VM-exit MSR-store count field is non-zero: 5490 * 5491 * - The lower 4 bits of the VM-exit MSR-store address must be 0. 5492 * The address should not set any bits beyond the processor's 5493 * physical-address width. 5494 * 5495 * - The address of the last byte in the VM-exit MSR-store area 5496 * should not set any bits beyond the processor's physical-address 5497 * width. The address of this last byte is VM-exit MSR-store address 5498 * + (MSR count * 16) - 1. (The arithmetic used for the computation 5499 * uses more bits than the processor's physical-address width.) 5500 * 5501 * If IA32_VMX_BASIC[48] is read as 1, neither address should set any bits 5502 * in the range 63:32. 5503 * 5504 * [Intel SDM] 5505 */ 5506 static void test_exit_msr_store(void) 5507 { 5508 exit_msr_store = alloc_page(); 5509 u64 tmp; 5510 u32 exit_msr_st_cnt = 1; 5511 int i; 5512 u32 addr_len = 64; 5513 5514 vmcs_write(EXI_MSR_ST_CNT, exit_msr_st_cnt); 5515 5516 /* Check first 4 bits of VM-exit MSR-store address */ 5517 for (i = 0; i < 4; i++) { 5518 tmp = (u64)exit_msr_store | 1ull << i; 5519 vmcs_write(EXIT_MSR_ST_ADDR, tmp); 5520 report_prefix_pushf("VM-exit MSR-store addr [4:0] %lx", 5521 tmp & 0xf); 5522 test_vmx_invalid_controls(); 5523 report_prefix_pop(); 5524 } 5525 5526 if (basic.val & (1ul << 48)) 5527 addr_len = 32; 5528 5529 test_vmcs_addr_values("VM-exit-MSR-store address", 5530 EXIT_MSR_ST_ADDR, 16, false, false, 5531 4, addr_len - 1); 5532 5533 /* 5534 * Check last byte of VM-exit MSR-store address 5535 */ 5536 exit_msr_store = (struct vmx_msr_entry *)((u64)exit_msr_store & ~0xf); 5537 5538 for (i = (addr_len == 64 ? cpuid_maxphyaddr(): addr_len); 5539 i < 64; i++) { 5540 tmp = ((u64)exit_msr_store + exit_msr_st_cnt * 16 - 1) | 5541 1ul << i; 5542 vmcs_write(EXIT_MSR_ST_ADDR, 5543 tmp - (exit_msr_st_cnt * 16 - 1)); 5544 test_vmx_invalid_controls(); 5545 } 5546 5547 vmcs_write(EXI_MSR_ST_CNT, 2); 5548 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 16); 5549 test_vmx_invalid_controls(); 5550 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 32); 5551 test_vmx_valid_controls(); 5552 vmcs_write(EXIT_MSR_ST_ADDR, (1ULL << cpuid_maxphyaddr()) - 48); 5553 test_vmx_valid_controls(); 5554 } 5555 5556 /* 5557 * Tests for VM-exit controls 5558 */ 5559 static void test_vm_exit_ctls(void) 5560 { 5561 test_exit_msr_store(); 5562 } 5563 5564 /* 5565 * Check that the virtual CPU checks all of the VMX controls as 5566 * documented in the Intel SDM. 5567 */ 5568 static void vmx_controls_test(void) 5569 { 5570 /* 5571 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 5572 * fail due to invalid guest state, should we make it that 5573 * far. 5574 */ 5575 vmcs_write(GUEST_RFLAGS, 0); 5576 5577 test_vm_execution_ctls(); 5578 test_vm_exit_ctls(); 5579 test_vm_entry_ctls(); 5580 } 5581 5582 struct apic_reg_virt_config { 5583 bool apic_register_virtualization; 5584 bool use_tpr_shadow; 5585 bool virtualize_apic_accesses; 5586 bool virtualize_x2apic_mode; 5587 bool activate_secondary_controls; 5588 }; 5589 5590 struct apic_reg_test { 5591 const char *name; 5592 struct apic_reg_virt_config apic_reg_virt_config; 5593 }; 5594 5595 struct apic_reg_virt_expectation { 5596 enum Reason rd_exit_reason; 5597 enum Reason wr_exit_reason; 5598 u32 val; 5599 u32 (*virt_fn)(u32); 5600 5601 /* 5602 * If false, accessing the APIC access address from L2 is treated as a 5603 * normal memory operation, rather than triggering virtualization. 5604 */ 5605 bool virtualize_apic_accesses; 5606 }; 5607 5608 static u32 apic_virt_identity(u32 val) 5609 { 5610 return val; 5611 } 5612 5613 static u32 apic_virt_nibble1(u32 val) 5614 { 5615 return val & 0xf0; 5616 } 5617 5618 static u32 apic_virt_byte3(u32 val) 5619 { 5620 return val & (0xff << 24); 5621 } 5622 5623 static bool apic_reg_virt_exit_expectation( 5624 u32 reg, struct apic_reg_virt_config *config, 5625 struct apic_reg_virt_expectation *expectation) 5626 { 5627 /* Good configs, where some L2 APIC accesses are virtualized. */ 5628 bool virtualize_apic_accesses_only = 5629 config->virtualize_apic_accesses && 5630 !config->use_tpr_shadow && 5631 !config->apic_register_virtualization && 5632 !config->virtualize_x2apic_mode && 5633 config->activate_secondary_controls; 5634 bool virtualize_apic_accesses_and_use_tpr_shadow = 5635 config->virtualize_apic_accesses && 5636 config->use_tpr_shadow && 5637 !config->apic_register_virtualization && 5638 !config->virtualize_x2apic_mode && 5639 config->activate_secondary_controls; 5640 bool apic_register_virtualization = 5641 config->virtualize_apic_accesses && 5642 config->use_tpr_shadow && 5643 config->apic_register_virtualization && 5644 !config->virtualize_x2apic_mode && 5645 config->activate_secondary_controls; 5646 5647 expectation->val = MAGIC_VAL_1; 5648 expectation->virt_fn = apic_virt_identity; 5649 expectation->virtualize_apic_accesses = 5650 config->virtualize_apic_accesses && 5651 config->activate_secondary_controls; 5652 if (virtualize_apic_accesses_only) { 5653 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5654 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5655 } else if (virtualize_apic_accesses_and_use_tpr_shadow) { 5656 switch (reg) { 5657 case APIC_TASKPRI: 5658 expectation->rd_exit_reason = VMX_VMCALL; 5659 expectation->wr_exit_reason = VMX_VMCALL; 5660 expectation->virt_fn = apic_virt_nibble1; 5661 break; 5662 default: 5663 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5664 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5665 } 5666 } else if (apic_register_virtualization) { 5667 expectation->rd_exit_reason = VMX_VMCALL; 5668 5669 switch (reg) { 5670 case APIC_ID: 5671 case APIC_EOI: 5672 case APIC_LDR: 5673 case APIC_DFR: 5674 case APIC_SPIV: 5675 case APIC_ESR: 5676 case APIC_ICR: 5677 case APIC_LVTT: 5678 case APIC_LVTTHMR: 5679 case APIC_LVTPC: 5680 case APIC_LVT0: 5681 case APIC_LVT1: 5682 case APIC_LVTERR: 5683 case APIC_TMICT: 5684 case APIC_TDCR: 5685 expectation->wr_exit_reason = VMX_APIC_WRITE; 5686 break; 5687 case APIC_LVR: 5688 case APIC_ISR ... APIC_ISR + 0x70: 5689 case APIC_TMR ... APIC_TMR + 0x70: 5690 case APIC_IRR ... APIC_IRR + 0x70: 5691 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5692 break; 5693 case APIC_TASKPRI: 5694 expectation->wr_exit_reason = VMX_VMCALL; 5695 expectation->virt_fn = apic_virt_nibble1; 5696 break; 5697 case APIC_ICR2: 5698 expectation->wr_exit_reason = VMX_VMCALL; 5699 expectation->virt_fn = apic_virt_byte3; 5700 break; 5701 default: 5702 expectation->rd_exit_reason = VMX_APIC_ACCESS; 5703 expectation->wr_exit_reason = VMX_APIC_ACCESS; 5704 } 5705 } else if (!expectation->virtualize_apic_accesses) { 5706 /* 5707 * No APIC registers are directly virtualized. This includes 5708 * VTPR, which can be virtualized through MOV to/from CR8 via 5709 * the use TPR shadow control, but not through directly 5710 * accessing VTPR. 5711 */ 5712 expectation->rd_exit_reason = VMX_VMCALL; 5713 expectation->wr_exit_reason = VMX_VMCALL; 5714 } else { 5715 printf("Cannot parse APIC register virtualization config:\n" 5716 "\tvirtualize_apic_accesses: %d\n" 5717 "\tuse_tpr_shadow: %d\n" 5718 "\tapic_register_virtualization: %d\n" 5719 "\tvirtualize_x2apic_mode: %d\n" 5720 "\tactivate_secondary_controls: %d\n", 5721 config->virtualize_apic_accesses, 5722 config->use_tpr_shadow, 5723 config->apic_register_virtualization, 5724 config->virtualize_x2apic_mode, 5725 config->activate_secondary_controls); 5726 5727 return false; 5728 } 5729 5730 return true; 5731 } 5732 5733 struct apic_reg_test apic_reg_tests[] = { 5734 /* Good configs, where some L2 APIC accesses are virtualized. */ 5735 { 5736 .name = "Virtualize APIC accesses", 5737 .apic_reg_virt_config = { 5738 .virtualize_apic_accesses = true, 5739 .use_tpr_shadow = false, 5740 .apic_register_virtualization = false, 5741 .virtualize_x2apic_mode = false, 5742 .activate_secondary_controls = true, 5743 }, 5744 }, 5745 { 5746 .name = "Virtualize APIC accesses + Use TPR shadow", 5747 .apic_reg_virt_config = { 5748 .virtualize_apic_accesses = true, 5749 .use_tpr_shadow = true, 5750 .apic_register_virtualization = false, 5751 .virtualize_x2apic_mode = false, 5752 .activate_secondary_controls = true, 5753 }, 5754 }, 5755 { 5756 .name = "APIC-register virtualization", 5757 .apic_reg_virt_config = { 5758 .virtualize_apic_accesses = true, 5759 .use_tpr_shadow = true, 5760 .apic_register_virtualization = true, 5761 .virtualize_x2apic_mode = false, 5762 .activate_secondary_controls = true, 5763 }, 5764 }, 5765 5766 /* 5767 * Test that the secondary processor-based VM-execution controls are 5768 * correctly ignored when "activate secondary controls" is disabled. 5769 */ 5770 { 5771 .name = "Activate secondary controls off", 5772 .apic_reg_virt_config = { 5773 .virtualize_apic_accesses = true, 5774 .use_tpr_shadow = false, 5775 .apic_register_virtualization = true, 5776 .virtualize_x2apic_mode = true, 5777 .activate_secondary_controls = false, 5778 }, 5779 }, 5780 { 5781 .name = "Activate secondary controls off + Use TPR shadow", 5782 .apic_reg_virt_config = { 5783 .virtualize_apic_accesses = true, 5784 .use_tpr_shadow = true, 5785 .apic_register_virtualization = true, 5786 .virtualize_x2apic_mode = true, 5787 .activate_secondary_controls = false, 5788 }, 5789 }, 5790 5791 /* 5792 * Test that the APIC access address is treated like an arbitrary memory 5793 * address when "virtualize APIC accesses" is disabled. 5794 */ 5795 { 5796 .name = "Virtualize APIC accesses off + Use TPR shadow", 5797 .apic_reg_virt_config = { 5798 .virtualize_apic_accesses = false, 5799 .use_tpr_shadow = true, 5800 .apic_register_virtualization = true, 5801 .virtualize_x2apic_mode = true, 5802 .activate_secondary_controls = true, 5803 }, 5804 }, 5805 5806 /* 5807 * Test that VM entry fails due to invalid controls when 5808 * "APIC-register virtualization" is enabled while "use TPR shadow" is 5809 * disabled. 5810 */ 5811 { 5812 .name = "APIC-register virtualization + Use TPR shadow off", 5813 .apic_reg_virt_config = { 5814 .virtualize_apic_accesses = true, 5815 .use_tpr_shadow = false, 5816 .apic_register_virtualization = true, 5817 .virtualize_x2apic_mode = false, 5818 .activate_secondary_controls = true, 5819 }, 5820 }, 5821 5822 /* 5823 * Test that VM entry fails due to invalid controls when 5824 * "Virtualize x2APIC mode" is enabled while "use TPR shadow" is 5825 * disabled. 5826 */ 5827 { 5828 .name = "Virtualize x2APIC mode + Use TPR shadow off", 5829 .apic_reg_virt_config = { 5830 .virtualize_apic_accesses = false, 5831 .use_tpr_shadow = false, 5832 .apic_register_virtualization = false, 5833 .virtualize_x2apic_mode = true, 5834 .activate_secondary_controls = true, 5835 }, 5836 }, 5837 { 5838 .name = "Virtualize x2APIC mode + Use TPR shadow off v2", 5839 .apic_reg_virt_config = { 5840 .virtualize_apic_accesses = false, 5841 .use_tpr_shadow = false, 5842 .apic_register_virtualization = true, 5843 .virtualize_x2apic_mode = true, 5844 .activate_secondary_controls = true, 5845 }, 5846 }, 5847 5848 /* 5849 * Test that VM entry fails due to invalid controls when 5850 * "virtualize x2APIC mode" is enabled while "virtualize APIC accesses" 5851 * is enabled. 5852 */ 5853 { 5854 .name = "Virtualize x2APIC mode + Virtualize APIC accesses", 5855 .apic_reg_virt_config = { 5856 .virtualize_apic_accesses = true, 5857 .use_tpr_shadow = true, 5858 .apic_register_virtualization = false, 5859 .virtualize_x2apic_mode = true, 5860 .activate_secondary_controls = true, 5861 }, 5862 }, 5863 { 5864 .name = "Virtualize x2APIC mode + Virtualize APIC accesses v2", 5865 .apic_reg_virt_config = { 5866 .virtualize_apic_accesses = true, 5867 .use_tpr_shadow = true, 5868 .apic_register_virtualization = true, 5869 .virtualize_x2apic_mode = true, 5870 .activate_secondary_controls = true, 5871 }, 5872 }, 5873 }; 5874 5875 enum Apic_op { 5876 APIC_OP_XAPIC_RD, 5877 APIC_OP_XAPIC_WR, 5878 TERMINATE, 5879 }; 5880 5881 static u32 vmx_xapic_read(u32 *apic_access_address, u32 reg) 5882 { 5883 return *(volatile u32 *)((uintptr_t)apic_access_address + reg); 5884 } 5885 5886 static void vmx_xapic_write(u32 *apic_access_address, u32 reg, u32 val) 5887 { 5888 *(volatile u32 *)((uintptr_t)apic_access_address + reg) = val; 5889 } 5890 5891 struct apic_reg_virt_guest_args { 5892 enum Apic_op op; 5893 u32 *apic_access_address; 5894 u32 reg; 5895 u32 val; 5896 bool check_rd; 5897 u32 (*virt_fn)(u32); 5898 } apic_reg_virt_guest_args; 5899 5900 static void apic_reg_virt_guest(void) 5901 { 5902 volatile struct apic_reg_virt_guest_args *args = 5903 &apic_reg_virt_guest_args; 5904 5905 for (;;) { 5906 enum Apic_op op = args->op; 5907 u32 *apic_access_address = args->apic_access_address; 5908 u32 reg = args->reg; 5909 u32 val = args->val; 5910 bool check_rd = args->check_rd; 5911 u32 (*virt_fn)(u32) = args->virt_fn; 5912 5913 if (op == TERMINATE) 5914 break; 5915 5916 if (op == APIC_OP_XAPIC_RD) { 5917 u32 ret = vmx_xapic_read(apic_access_address, reg); 5918 5919 if (check_rd) { 5920 u32 want = virt_fn(val); 5921 u32 got = virt_fn(ret); 5922 5923 report(got == want, 5924 "read 0x%x, expected 0x%x.", got, want); 5925 } 5926 } else if (op == APIC_OP_XAPIC_WR) { 5927 vmx_xapic_write(apic_access_address, reg, val); 5928 } 5929 5930 /* 5931 * The L1 should always execute a vmcall after it's done testing 5932 * an individual APIC operation. This helps to validate that the 5933 * L1 and L2 are in sync with each other, as expected. 5934 */ 5935 vmcall(); 5936 } 5937 } 5938 5939 static void test_xapic_rd( 5940 u32 reg, struct apic_reg_virt_expectation *expectation, 5941 u32 *apic_access_address, u32 *virtual_apic_page) 5942 { 5943 u32 val = expectation->val; 5944 u32 exit_reason_want = expectation->rd_exit_reason; 5945 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5946 5947 report_prefix_pushf("xapic - reading 0x%03x", reg); 5948 5949 /* Configure guest to do an xapic read */ 5950 args->op = APIC_OP_XAPIC_RD; 5951 args->apic_access_address = apic_access_address; 5952 args->reg = reg; 5953 args->val = val; 5954 args->check_rd = exit_reason_want == VMX_VMCALL; 5955 args->virt_fn = expectation->virt_fn; 5956 5957 /* Setup virtual APIC page */ 5958 if (!expectation->virtualize_apic_accesses) { 5959 apic_access_address[apic_reg_index(reg)] = val; 5960 virtual_apic_page[apic_reg_index(reg)] = 0; 5961 } else if (exit_reason_want == VMX_VMCALL) { 5962 apic_access_address[apic_reg_index(reg)] = 0; 5963 virtual_apic_page[apic_reg_index(reg)] = val; 5964 } 5965 5966 /* Enter guest */ 5967 enter_guest(); 5968 5969 /* 5970 * Validate the behavior and 5971 * pass a magic value back to the guest. 5972 */ 5973 if (exit_reason_want == VMX_APIC_ACCESS) { 5974 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 5975 5976 assert_exit_reason(exit_reason_want); 5977 report(apic_page_offset == reg, 5978 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 5979 apic_page_offset, reg); 5980 skip_exit_insn(); 5981 5982 /* Reenter guest so it can consume/check rcx and exit again. */ 5983 enter_guest(); 5984 } else if (exit_reason_want != VMX_VMCALL) { 5985 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 5986 } 5987 5988 skip_exit_vmcall(); 5989 report_prefix_pop(); 5990 } 5991 5992 static void test_xapic_wr( 5993 u32 reg, struct apic_reg_virt_expectation *expectation, 5994 u32 *apic_access_address, u32 *virtual_apic_page) 5995 { 5996 u32 val = expectation->val; 5997 u32 exit_reason_want = expectation->wr_exit_reason; 5998 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 5999 bool virtualized = 6000 expectation->virtualize_apic_accesses && 6001 (exit_reason_want == VMX_APIC_WRITE || 6002 exit_reason_want == VMX_VMCALL); 6003 bool checked = false; 6004 6005 report_prefix_pushf("xapic - writing 0x%x to 0x%03x", val, reg); 6006 6007 /* Configure guest to do an xapic read */ 6008 args->op = APIC_OP_XAPIC_WR; 6009 args->apic_access_address = apic_access_address; 6010 args->reg = reg; 6011 args->val = val; 6012 6013 /* Setup virtual APIC page */ 6014 if (virtualized || !expectation->virtualize_apic_accesses) { 6015 apic_access_address[apic_reg_index(reg)] = 0; 6016 virtual_apic_page[apic_reg_index(reg)] = 0; 6017 } 6018 6019 /* Enter guest */ 6020 enter_guest(); 6021 6022 /* 6023 * Validate the behavior and 6024 * pass a magic value back to the guest. 6025 */ 6026 if (exit_reason_want == VMX_APIC_ACCESS) { 6027 u32 apic_page_offset = vmcs_read(EXI_QUALIFICATION) & 0xfff; 6028 6029 assert_exit_reason(exit_reason_want); 6030 report(apic_page_offset == reg, 6031 "got APIC access exit @ page offset 0x%03x, want 0x%03x", 6032 apic_page_offset, reg); 6033 skip_exit_insn(); 6034 6035 /* Reenter guest so it can consume/check rcx and exit again. */ 6036 enter_guest(); 6037 } else if (exit_reason_want == VMX_APIC_WRITE) { 6038 assert_exit_reason(exit_reason_want); 6039 report(virtual_apic_page[apic_reg_index(reg)] == val, 6040 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%x", 6041 apic_reg_index(reg), 6042 virtual_apic_page[apic_reg_index(reg)], val); 6043 checked = true; 6044 6045 /* Reenter guest so it can consume/check rcx and exit again. */ 6046 enter_guest(); 6047 } else if (exit_reason_want != VMX_VMCALL) { 6048 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6049 } 6050 6051 assert_exit_reason(VMX_VMCALL); 6052 if (virtualized && !checked) { 6053 u32 want = expectation->virt_fn(val); 6054 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6055 got = expectation->virt_fn(got); 6056 6057 report(got == want, "exitless write; val is 0x%x, want 0x%x", 6058 got, want); 6059 } else if (!expectation->virtualize_apic_accesses && !checked) { 6060 u32 got = apic_access_address[apic_reg_index(reg)]; 6061 6062 report(got == val, 6063 "non-virtualized write; val is 0x%x, want 0x%x", got, 6064 val); 6065 } else if (!expectation->virtualize_apic_accesses && checked) { 6066 report_fail("Non-virtualized write was prematurely checked!"); 6067 } 6068 6069 skip_exit_vmcall(); 6070 report_prefix_pop(); 6071 } 6072 6073 enum Config_type { 6074 CONFIG_TYPE_GOOD, 6075 CONFIG_TYPE_UNSUPPORTED, 6076 CONFIG_TYPE_VMENTRY_FAILS_EARLY, 6077 }; 6078 6079 static enum Config_type configure_apic_reg_virt_test( 6080 struct apic_reg_virt_config *apic_reg_virt_config) 6081 { 6082 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6083 u32 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6084 /* Configs where L2 entry fails early, due to invalid controls. */ 6085 bool use_tpr_shadow_incorrectly_off = 6086 !apic_reg_virt_config->use_tpr_shadow && 6087 (apic_reg_virt_config->apic_register_virtualization || 6088 apic_reg_virt_config->virtualize_x2apic_mode) && 6089 apic_reg_virt_config->activate_secondary_controls; 6090 bool virtualize_apic_accesses_incorrectly_on = 6091 apic_reg_virt_config->virtualize_apic_accesses && 6092 apic_reg_virt_config->virtualize_x2apic_mode && 6093 apic_reg_virt_config->activate_secondary_controls; 6094 bool vmentry_fails_early = 6095 use_tpr_shadow_incorrectly_off || 6096 virtualize_apic_accesses_incorrectly_on; 6097 6098 if (apic_reg_virt_config->activate_secondary_controls) { 6099 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 6100 printf("VM-execution control \"activate secondary controls\" NOT supported.\n"); 6101 return CONFIG_TYPE_UNSUPPORTED; 6102 } 6103 cpu_exec_ctrl0 |= CPU_SECONDARY; 6104 } else { 6105 cpu_exec_ctrl0 &= ~CPU_SECONDARY; 6106 } 6107 6108 if (apic_reg_virt_config->virtualize_apic_accesses) { 6109 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_APIC_ACCESSES)) { 6110 printf("VM-execution control \"virtualize APIC accesses\" NOT supported.\n"); 6111 return CONFIG_TYPE_UNSUPPORTED; 6112 } 6113 cpu_exec_ctrl1 |= CPU_VIRT_APIC_ACCESSES; 6114 } else { 6115 cpu_exec_ctrl1 &= ~CPU_VIRT_APIC_ACCESSES; 6116 } 6117 6118 if (apic_reg_virt_config->use_tpr_shadow) { 6119 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6120 printf("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6121 return CONFIG_TYPE_UNSUPPORTED; 6122 } 6123 cpu_exec_ctrl0 |= CPU_TPR_SHADOW; 6124 } else { 6125 cpu_exec_ctrl0 &= ~CPU_TPR_SHADOW; 6126 } 6127 6128 if (apic_reg_virt_config->apic_register_virtualization) { 6129 if (!(ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT)) { 6130 printf("VM-execution control \"APIC-register virtualization\" NOT supported.\n"); 6131 return CONFIG_TYPE_UNSUPPORTED; 6132 } 6133 cpu_exec_ctrl1 |= CPU_APIC_REG_VIRT; 6134 } else { 6135 cpu_exec_ctrl1 &= ~CPU_APIC_REG_VIRT; 6136 } 6137 6138 if (apic_reg_virt_config->virtualize_x2apic_mode) { 6139 if (!(ctrl_cpu_rev[1].clr & CPU_VIRT_X2APIC)) { 6140 printf("VM-execution control \"virtualize x2APIC mode\" NOT supported.\n"); 6141 return CONFIG_TYPE_UNSUPPORTED; 6142 } 6143 cpu_exec_ctrl1 |= CPU_VIRT_X2APIC; 6144 } else { 6145 cpu_exec_ctrl1 &= ~CPU_VIRT_X2APIC; 6146 } 6147 6148 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6149 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6150 6151 if (vmentry_fails_early) 6152 return CONFIG_TYPE_VMENTRY_FAILS_EARLY; 6153 6154 return CONFIG_TYPE_GOOD; 6155 } 6156 6157 static bool cpu_has_apicv(void) 6158 { 6159 return ((ctrl_cpu_rev[1].clr & CPU_APIC_REG_VIRT) && 6160 (ctrl_cpu_rev[1].clr & CPU_VINTD) && 6161 (ctrl_pin_rev.clr & PIN_POST_INTR)); 6162 } 6163 6164 /* Validates APIC register access across valid virtualization configurations. */ 6165 static void apic_reg_virt_test(void) 6166 { 6167 u32 *apic_access_address; 6168 u32 *virtual_apic_page; 6169 u64 control; 6170 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6171 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6172 int i; 6173 struct apic_reg_virt_guest_args *args = &apic_reg_virt_guest_args; 6174 6175 if (!cpu_has_apicv()) { 6176 report_skip(__func__); 6177 return; 6178 } 6179 6180 control = cpu_exec_ctrl1; 6181 control &= ~CPU_VINTD; 6182 vmcs_write(CPU_EXEC_CTRL1, control); 6183 6184 test_set_guest(apic_reg_virt_guest); 6185 6186 /* 6187 * From the SDM: The 1-setting of the "virtualize APIC accesses" 6188 * VM-execution is guaranteed to apply only if translations to the 6189 * APIC-access address use a 4-KByte page. 6190 */ 6191 apic_access_address = alloc_page(); 6192 force_4k_page(apic_access_address); 6193 vmcs_write(APIC_ACCS_ADDR, virt_to_phys(apic_access_address)); 6194 6195 virtual_apic_page = alloc_page(); 6196 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6197 6198 for (i = 0; i < ARRAY_SIZE(apic_reg_tests); i++) { 6199 struct apic_reg_test *apic_reg_test = &apic_reg_tests[i]; 6200 struct apic_reg_virt_config *apic_reg_virt_config = 6201 &apic_reg_test->apic_reg_virt_config; 6202 enum Config_type config_type; 6203 u32 reg; 6204 6205 printf("--- %s test ---\n", apic_reg_test->name); 6206 config_type = 6207 configure_apic_reg_virt_test(apic_reg_virt_config); 6208 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 6209 printf("Skip because of missing features.\n"); 6210 continue; 6211 } 6212 6213 if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 6214 enter_guest_with_bad_controls(); 6215 continue; 6216 } 6217 6218 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 6219 struct apic_reg_virt_expectation expectation = {}; 6220 bool ok; 6221 6222 ok = apic_reg_virt_exit_expectation( 6223 reg, apic_reg_virt_config, &expectation); 6224 if (!ok) { 6225 report_fail("Malformed test."); 6226 break; 6227 } 6228 6229 test_xapic_rd(reg, &expectation, apic_access_address, 6230 virtual_apic_page); 6231 test_xapic_wr(reg, &expectation, apic_access_address, 6232 virtual_apic_page); 6233 } 6234 } 6235 6236 /* Terminate the guest */ 6237 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6238 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6239 args->op = TERMINATE; 6240 enter_guest(); 6241 assert_exit_reason(VMX_VMCALL); 6242 } 6243 6244 struct virt_x2apic_mode_config { 6245 struct apic_reg_virt_config apic_reg_virt_config; 6246 bool virtual_interrupt_delivery; 6247 bool use_msr_bitmaps; 6248 bool disable_x2apic_msr_intercepts; 6249 bool disable_x2apic; 6250 }; 6251 6252 struct virt_x2apic_mode_test_case { 6253 const char *name; 6254 struct virt_x2apic_mode_config virt_x2apic_mode_config; 6255 }; 6256 6257 enum Virt_x2apic_mode_behavior_type { 6258 X2APIC_ACCESS_VIRTUALIZED, 6259 X2APIC_ACCESS_PASSED_THROUGH, 6260 X2APIC_ACCESS_TRIGGERS_GP, 6261 }; 6262 6263 struct virt_x2apic_mode_expectation { 6264 enum Reason rd_exit_reason; 6265 enum Reason wr_exit_reason; 6266 6267 /* 6268 * RDMSR and WRMSR handle 64-bit values. However, except for ICR, all of 6269 * the x2APIC registers are 32 bits. Notice: 6270 * 1. vmx_x2apic_read() clears the upper 32 bits for 32-bit registers. 6271 * 2. vmx_x2apic_write() expects the val arg to be well-formed. 6272 */ 6273 u64 rd_val; 6274 u64 wr_val; 6275 6276 /* 6277 * Compares input to virtualized output; 6278 * 1st arg is pointer to return expected virtualization output. 6279 */ 6280 u64 (*virt_fn)(u64); 6281 6282 enum Virt_x2apic_mode_behavior_type rd_behavior; 6283 enum Virt_x2apic_mode_behavior_type wr_behavior; 6284 bool wr_only; 6285 }; 6286 6287 static u64 virt_x2apic_mode_identity(u64 val) 6288 { 6289 return val; 6290 } 6291 6292 static u64 virt_x2apic_mode_nibble1(u64 val) 6293 { 6294 return val & 0xf0; 6295 } 6296 6297 static void virt_x2apic_mode_rd_expectation( 6298 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6299 bool apic_register_virtualization, bool virtual_interrupt_delivery, 6300 struct virt_x2apic_mode_expectation *expectation) 6301 { 6302 bool readable = 6303 !x2apic_reg_reserved(reg) && 6304 reg != APIC_EOI; 6305 6306 expectation->rd_exit_reason = VMX_VMCALL; 6307 expectation->virt_fn = virt_x2apic_mode_identity; 6308 if (virt_x2apic_mode_on && apic_register_virtualization) { 6309 expectation->rd_val = MAGIC_VAL_1; 6310 if (reg == APIC_PROCPRI && virtual_interrupt_delivery) 6311 expectation->virt_fn = virt_x2apic_mode_nibble1; 6312 else if (reg == APIC_TASKPRI) 6313 expectation->virt_fn = virt_x2apic_mode_nibble1; 6314 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6315 } else if (virt_x2apic_mode_on && !apic_register_virtualization && 6316 reg == APIC_TASKPRI) { 6317 expectation->rd_val = MAGIC_VAL_1; 6318 expectation->virt_fn = virt_x2apic_mode_nibble1; 6319 expectation->rd_behavior = X2APIC_ACCESS_VIRTUALIZED; 6320 } else if (!disable_x2apic && readable) { 6321 expectation->rd_val = apic_read(reg); 6322 expectation->rd_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6323 } else { 6324 expectation->rd_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6325 } 6326 } 6327 6328 /* 6329 * get_x2apic_wr_val() creates an innocuous write value for an x2APIC register. 6330 * 6331 * For writable registers, get_x2apic_wr_val() deposits the write value into the 6332 * val pointer arg and returns true. For non-writable registers, val is not 6333 * modified and get_x2apic_wr_val() returns false. 6334 */ 6335 static bool get_x2apic_wr_val(u32 reg, u64 *val) 6336 { 6337 switch (reg) { 6338 case APIC_TASKPRI: 6339 /* Bits 31:8 are reserved. */ 6340 *val &= 0xff; 6341 break; 6342 case APIC_EOI: 6343 case APIC_ESR: 6344 case APIC_TMICT: 6345 /* 6346 * EOI, ESR: WRMSR of a non-zero value causes #GP(0). 6347 * TMICT: A write of 0 to the initial-count register effectively 6348 * stops the local APIC timer, in both one-shot and 6349 * periodic mode. 6350 */ 6351 *val = 0; 6352 break; 6353 case APIC_SPIV: 6354 case APIC_LVTT: 6355 case APIC_LVTTHMR: 6356 case APIC_LVTPC: 6357 case APIC_LVT0: 6358 case APIC_LVT1: 6359 case APIC_LVTERR: 6360 case APIC_TDCR: 6361 /* 6362 * To avoid writing a 1 to a reserved bit or causing some other 6363 * unintended side effect, read the current value and use it as 6364 * the write value. 6365 */ 6366 *val = apic_read(reg); 6367 break; 6368 case APIC_CMCI: 6369 if (!apic_lvt_entry_supported(6)) 6370 return false; 6371 *val = apic_read(reg); 6372 break; 6373 case APIC_ICR: 6374 *val = 0x40000 | 0xf1; 6375 break; 6376 case APIC_SELF_IPI: 6377 /* 6378 * With special processing (i.e., virtualize x2APIC mode + 6379 * virtual interrupt delivery), writing zero causes an 6380 * APIC-write VM exit. We plan to add a test for enabling 6381 * "virtual-interrupt delivery" in VMCS12, and that's where we 6382 * will test a self IPI with special processing. 6383 */ 6384 *val = 0x0; 6385 break; 6386 default: 6387 return false; 6388 } 6389 6390 return true; 6391 } 6392 6393 static bool special_processing_applies(u32 reg, u64 *val, 6394 bool virt_int_delivery) 6395 { 6396 bool special_processing = 6397 (reg == APIC_TASKPRI) || 6398 (virt_int_delivery && 6399 (reg == APIC_EOI || reg == APIC_SELF_IPI)); 6400 6401 if (special_processing) { 6402 TEST_ASSERT(get_x2apic_wr_val(reg, val)); 6403 return true; 6404 } 6405 6406 return false; 6407 } 6408 6409 static void virt_x2apic_mode_wr_expectation( 6410 u32 reg, bool virt_x2apic_mode_on, bool disable_x2apic, 6411 bool virt_int_delivery, 6412 struct virt_x2apic_mode_expectation *expectation) 6413 { 6414 expectation->wr_exit_reason = VMX_VMCALL; 6415 expectation->wr_val = MAGIC_VAL_1; 6416 expectation->wr_only = false; 6417 6418 if (virt_x2apic_mode_on && 6419 special_processing_applies(reg, &expectation->wr_val, 6420 virt_int_delivery)) { 6421 expectation->wr_behavior = X2APIC_ACCESS_VIRTUALIZED; 6422 if (reg == APIC_SELF_IPI) 6423 expectation->wr_exit_reason = VMX_APIC_WRITE; 6424 } else if (!disable_x2apic && 6425 get_x2apic_wr_val(reg, &expectation->wr_val)) { 6426 expectation->wr_behavior = X2APIC_ACCESS_PASSED_THROUGH; 6427 if (reg == APIC_EOI || reg == APIC_SELF_IPI) 6428 expectation->wr_only = true; 6429 if (reg == APIC_ICR) 6430 expectation->wr_exit_reason = VMX_EXTINT; 6431 } else { 6432 expectation->wr_behavior = X2APIC_ACCESS_TRIGGERS_GP; 6433 /* 6434 * Writing 1 to a reserved bit triggers a #GP. 6435 * Thus, set the write value to 0, which seems 6436 * the most likely to detect a missed #GP. 6437 */ 6438 expectation->wr_val = 0; 6439 } 6440 } 6441 6442 static void virt_x2apic_mode_exit_expectation( 6443 u32 reg, struct virt_x2apic_mode_config *config, 6444 struct virt_x2apic_mode_expectation *expectation) 6445 { 6446 struct apic_reg_virt_config *base_config = 6447 &config->apic_reg_virt_config; 6448 bool virt_x2apic_mode_on = 6449 base_config->virtualize_x2apic_mode && 6450 config->use_msr_bitmaps && 6451 config->disable_x2apic_msr_intercepts && 6452 base_config->activate_secondary_controls; 6453 6454 virt_x2apic_mode_wr_expectation( 6455 reg, virt_x2apic_mode_on, config->disable_x2apic, 6456 config->virtual_interrupt_delivery, expectation); 6457 virt_x2apic_mode_rd_expectation( 6458 reg, virt_x2apic_mode_on, config->disable_x2apic, 6459 base_config->apic_register_virtualization, 6460 config->virtual_interrupt_delivery, expectation); 6461 } 6462 6463 struct virt_x2apic_mode_test_case virt_x2apic_mode_tests[] = { 6464 /* 6465 * Baseline "virtualize x2APIC mode" configuration: 6466 * - virtualize x2APIC mode 6467 * - virtual-interrupt delivery 6468 * - APIC-register virtualization 6469 * - x2APIC MSR intercepts disabled 6470 * 6471 * Reads come from virtual APIC page, special processing applies to 6472 * VTPR, EOI, and SELF IPI, and all other writes pass through to L1 6473 * APIC. 6474 */ 6475 { 6476 .name = "Baseline", 6477 .virt_x2apic_mode_config = { 6478 .virtual_interrupt_delivery = true, 6479 .use_msr_bitmaps = true, 6480 .disable_x2apic_msr_intercepts = true, 6481 .disable_x2apic = false, 6482 .apic_reg_virt_config = { 6483 .apic_register_virtualization = true, 6484 .use_tpr_shadow = true, 6485 .virtualize_apic_accesses = false, 6486 .virtualize_x2apic_mode = true, 6487 .activate_secondary_controls = true, 6488 }, 6489 }, 6490 }, 6491 { 6492 .name = "Baseline w/ x2apic disabled", 6493 .virt_x2apic_mode_config = { 6494 .virtual_interrupt_delivery = true, 6495 .use_msr_bitmaps = true, 6496 .disable_x2apic_msr_intercepts = true, 6497 .disable_x2apic = true, 6498 .apic_reg_virt_config = { 6499 .apic_register_virtualization = true, 6500 .use_tpr_shadow = true, 6501 .virtualize_apic_accesses = false, 6502 .virtualize_x2apic_mode = true, 6503 .activate_secondary_controls = true, 6504 }, 6505 }, 6506 }, 6507 6508 /* 6509 * Baseline, minus virtual-interrupt delivery. Reads come from virtual 6510 * APIC page, special processing applies to VTPR, and all other writes 6511 * pass through to L1 APIC. 6512 */ 6513 { 6514 .name = "Baseline - virtual interrupt delivery", 6515 .virt_x2apic_mode_config = { 6516 .virtual_interrupt_delivery = false, 6517 .use_msr_bitmaps = true, 6518 .disable_x2apic_msr_intercepts = true, 6519 .disable_x2apic = false, 6520 .apic_reg_virt_config = { 6521 .apic_register_virtualization = true, 6522 .use_tpr_shadow = true, 6523 .virtualize_apic_accesses = false, 6524 .virtualize_x2apic_mode = true, 6525 .activate_secondary_controls = true, 6526 }, 6527 }, 6528 }, 6529 6530 /* 6531 * Baseline, minus APIC-register virtualization. x2APIC reads pass 6532 * through to L1's APIC, unless reading VTPR 6533 */ 6534 { 6535 .name = "Virtualize x2APIC mode, no APIC reg virt", 6536 .virt_x2apic_mode_config = { 6537 .virtual_interrupt_delivery = true, 6538 .use_msr_bitmaps = true, 6539 .disable_x2apic_msr_intercepts = true, 6540 .disable_x2apic = false, 6541 .apic_reg_virt_config = { 6542 .apic_register_virtualization = false, 6543 .use_tpr_shadow = true, 6544 .virtualize_apic_accesses = false, 6545 .virtualize_x2apic_mode = true, 6546 .activate_secondary_controls = true, 6547 }, 6548 }, 6549 }, 6550 { 6551 .name = "Virtualize x2APIC mode, no APIC reg virt, x2APIC off", 6552 .virt_x2apic_mode_config = { 6553 .virtual_interrupt_delivery = true, 6554 .use_msr_bitmaps = true, 6555 .disable_x2apic_msr_intercepts = true, 6556 .disable_x2apic = true, 6557 .apic_reg_virt_config = { 6558 .apic_register_virtualization = false, 6559 .use_tpr_shadow = true, 6560 .virtualize_apic_accesses = false, 6561 .virtualize_x2apic_mode = true, 6562 .activate_secondary_controls = true, 6563 }, 6564 }, 6565 }, 6566 6567 /* 6568 * Enable "virtualize x2APIC mode" and "APIC-register virtualization", 6569 * and disable intercepts for the x2APIC MSRs, but fail to enable 6570 * "activate secondary controls" (i.e. L2 gets access to L1's x2APIC 6571 * MSRs). 6572 */ 6573 { 6574 .name = "Fail to enable activate secondary controls", 6575 .virt_x2apic_mode_config = { 6576 .virtual_interrupt_delivery = true, 6577 .use_msr_bitmaps = true, 6578 .disable_x2apic_msr_intercepts = true, 6579 .disable_x2apic = false, 6580 .apic_reg_virt_config = { 6581 .apic_register_virtualization = true, 6582 .use_tpr_shadow = true, 6583 .virtualize_apic_accesses = false, 6584 .virtualize_x2apic_mode = true, 6585 .activate_secondary_controls = false, 6586 }, 6587 }, 6588 }, 6589 6590 /* 6591 * Enable "APIC-register virtualization" and enable "activate secondary 6592 * controls" and disable intercepts for the x2APIC MSRs, but do not 6593 * enable the "virtualize x2APIC mode" VM-execution control (i.e. L2 6594 * gets access to L1's x2APIC MSRs). 6595 */ 6596 { 6597 .name = "Fail to enable virtualize x2APIC mode", 6598 .virt_x2apic_mode_config = { 6599 .virtual_interrupt_delivery = true, 6600 .use_msr_bitmaps = true, 6601 .disable_x2apic_msr_intercepts = true, 6602 .disable_x2apic = false, 6603 .apic_reg_virt_config = { 6604 .apic_register_virtualization = true, 6605 .use_tpr_shadow = true, 6606 .virtualize_apic_accesses = false, 6607 .virtualize_x2apic_mode = false, 6608 .activate_secondary_controls = true, 6609 }, 6610 }, 6611 }, 6612 6613 /* 6614 * Disable "Virtualize x2APIC mode", disable x2APIC MSR intercepts, and 6615 * enable "APIC-register virtualization" --> L2 gets L1's x2APIC MSRs. 6616 */ 6617 { 6618 .name = "Baseline", 6619 .virt_x2apic_mode_config = { 6620 .virtual_interrupt_delivery = true, 6621 .use_msr_bitmaps = true, 6622 .disable_x2apic_msr_intercepts = true, 6623 .disable_x2apic = false, 6624 .apic_reg_virt_config = { 6625 .apic_register_virtualization = true, 6626 .use_tpr_shadow = true, 6627 .virtualize_apic_accesses = false, 6628 .virtualize_x2apic_mode = false, 6629 .activate_secondary_controls = true, 6630 }, 6631 }, 6632 }, 6633 }; 6634 6635 enum X2apic_op { 6636 X2APIC_OP_RD, 6637 X2APIC_OP_WR, 6638 X2APIC_TERMINATE, 6639 }; 6640 6641 static u64 vmx_x2apic_read(u32 reg) 6642 { 6643 u32 msr_addr = x2apic_msr(reg); 6644 u64 val; 6645 6646 val = rdmsr(msr_addr); 6647 6648 return val; 6649 } 6650 6651 static void vmx_x2apic_write(u32 reg, u64 val) 6652 { 6653 u32 msr_addr = x2apic_msr(reg); 6654 6655 wrmsr(msr_addr, val); 6656 } 6657 6658 struct virt_x2apic_mode_guest_args { 6659 enum X2apic_op op; 6660 u32 reg; 6661 u64 val; 6662 bool should_gp; 6663 u64 (*virt_fn)(u64); 6664 } virt_x2apic_mode_guest_args; 6665 6666 static volatile bool handle_x2apic_gp_ran; 6667 static volatile u32 handle_x2apic_gp_insn_len; 6668 static void handle_x2apic_gp(struct ex_regs *regs) 6669 { 6670 handle_x2apic_gp_ran = true; 6671 regs->rip += handle_x2apic_gp_insn_len; 6672 } 6673 6674 static handler setup_x2apic_gp_handler(void) 6675 { 6676 handler old_handler; 6677 6678 old_handler = handle_exception(GP_VECTOR, handle_x2apic_gp); 6679 /* RDMSR and WRMSR are both 2 bytes, assuming no prefixes. */ 6680 handle_x2apic_gp_insn_len = 2; 6681 6682 return old_handler; 6683 } 6684 6685 static void teardown_x2apic_gp_handler(handler old_handler) 6686 { 6687 handle_exception(GP_VECTOR, old_handler); 6688 6689 /* 6690 * Defensively reset instruction length, so that if the handler is 6691 * incorrectly used, it will loop infinitely, rather than run off into 6692 * la la land. 6693 */ 6694 handle_x2apic_gp_insn_len = 0; 6695 handle_x2apic_gp_ran = false; 6696 } 6697 6698 static void virt_x2apic_mode_guest(void) 6699 { 6700 volatile struct virt_x2apic_mode_guest_args *args = 6701 &virt_x2apic_mode_guest_args; 6702 6703 for (;;) { 6704 enum X2apic_op op = args->op; 6705 u32 reg = args->reg; 6706 u64 val = args->val; 6707 bool should_gp = args->should_gp; 6708 u64 (*virt_fn)(u64) = args->virt_fn; 6709 handler old_handler; 6710 6711 if (op == X2APIC_TERMINATE) 6712 break; 6713 6714 if (should_gp) { 6715 TEST_ASSERT(!handle_x2apic_gp_ran); 6716 old_handler = setup_x2apic_gp_handler(); 6717 } 6718 6719 if (op == X2APIC_OP_RD) { 6720 u64 ret = vmx_x2apic_read(reg); 6721 6722 if (!should_gp) { 6723 u64 want = virt_fn(val); 6724 u64 got = virt_fn(ret); 6725 6726 report(got == want, 6727 "APIC read; got 0x%lx, want 0x%lx.", 6728 got, want); 6729 } 6730 } else if (op == X2APIC_OP_WR) { 6731 vmx_x2apic_write(reg, val); 6732 } 6733 6734 if (should_gp) { 6735 report(handle_x2apic_gp_ran, 6736 "x2APIC op triggered GP."); 6737 teardown_x2apic_gp_handler(old_handler); 6738 } 6739 6740 /* 6741 * The L1 should always execute a vmcall after it's done testing 6742 * an individual APIC operation. This helps to validate that the 6743 * L1 and L2 are in sync with each other, as expected. 6744 */ 6745 vmcall(); 6746 } 6747 } 6748 6749 static void test_x2apic_rd( 6750 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6751 u32 *virtual_apic_page) 6752 { 6753 u64 val = expectation->rd_val; 6754 u32 exit_reason_want = expectation->rd_exit_reason; 6755 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6756 6757 report_prefix_pushf("x2apic - reading 0x%03x", reg); 6758 6759 /* Configure guest to do an x2apic read */ 6760 args->op = X2APIC_OP_RD; 6761 args->reg = reg; 6762 args->val = val; 6763 args->should_gp = expectation->rd_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6764 args->virt_fn = expectation->virt_fn; 6765 6766 /* Setup virtual APIC page */ 6767 if (expectation->rd_behavior == X2APIC_ACCESS_VIRTUALIZED) 6768 virtual_apic_page[apic_reg_index(reg)] = (u32)val; 6769 6770 /* Enter guest */ 6771 enter_guest(); 6772 6773 if (exit_reason_want != VMX_VMCALL) { 6774 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6775 } 6776 6777 skip_exit_vmcall(); 6778 report_prefix_pop(); 6779 } 6780 6781 static volatile bool handle_x2apic_ipi_ran; 6782 static void handle_x2apic_ipi(isr_regs_t *regs) 6783 { 6784 handle_x2apic_ipi_ran = true; 6785 eoi(); 6786 } 6787 6788 static void test_x2apic_wr( 6789 u32 reg, struct virt_x2apic_mode_expectation *expectation, 6790 u32 *virtual_apic_page) 6791 { 6792 u64 val = expectation->wr_val; 6793 u32 exit_reason_want = expectation->wr_exit_reason; 6794 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6795 int ipi_vector = 0xf1; 6796 u32 restore_val = 0; 6797 6798 report_prefix_pushf("x2apic - writing 0x%lx to 0x%03x", val, reg); 6799 6800 /* Configure guest to do an x2apic read */ 6801 args->op = X2APIC_OP_WR; 6802 args->reg = reg; 6803 args->val = val; 6804 args->should_gp = expectation->wr_behavior == X2APIC_ACCESS_TRIGGERS_GP; 6805 6806 /* Setup virtual APIC page */ 6807 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) 6808 virtual_apic_page[apic_reg_index(reg)] = 0; 6809 if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH && !expectation->wr_only) 6810 restore_val = apic_read(reg); 6811 6812 /* Setup IPI handler */ 6813 handle_x2apic_ipi_ran = false; 6814 handle_irq(ipi_vector, handle_x2apic_ipi); 6815 6816 /* Enter guest */ 6817 enter_guest(); 6818 6819 /* 6820 * Validate the behavior and 6821 * pass a magic value back to the guest. 6822 */ 6823 if (exit_reason_want == VMX_EXTINT) { 6824 assert_exit_reason(exit_reason_want); 6825 6826 /* Clear the external interrupt. */ 6827 irq_enable(); 6828 asm volatile ("nop"); 6829 irq_disable(); 6830 report(handle_x2apic_ipi_ran, 6831 "Got pending interrupt after IRQ enabled."); 6832 6833 enter_guest(); 6834 } else if (exit_reason_want == VMX_APIC_WRITE) { 6835 assert_exit_reason(exit_reason_want); 6836 report(virtual_apic_page[apic_reg_index(reg)] == val, 6837 "got APIC write exit @ page offset 0x%03x; val is 0x%x, want 0x%lx", 6838 apic_reg_index(reg), 6839 virtual_apic_page[apic_reg_index(reg)], val); 6840 6841 /* Reenter guest so it can consume/check rcx and exit again. */ 6842 enter_guest(); 6843 } else if (exit_reason_want != VMX_VMCALL) { 6844 report_fail("Oops, bad exit expectation: %u.", exit_reason_want); 6845 } 6846 6847 assert_exit_reason(VMX_VMCALL); 6848 if (expectation->wr_behavior == X2APIC_ACCESS_VIRTUALIZED) { 6849 u64 want = val; 6850 u32 got = virtual_apic_page[apic_reg_index(reg)]; 6851 6852 report(got == want, "x2APIC write; got 0x%x, want 0x%lx", got, 6853 want); 6854 } else if (expectation->wr_behavior == X2APIC_ACCESS_PASSED_THROUGH) { 6855 if (!expectation->wr_only) { 6856 u32 got = apic_read(reg); 6857 bool ok; 6858 6859 /* 6860 * When L1's TPR is passed through to L2, the lower 6861 * nibble can be lost. For example, if L2 executes 6862 * WRMSR(0x808, 0x78), then, L1 might read 0x70. 6863 * 6864 * Here's how the lower nibble can get lost: 6865 * 1. L2 executes WRMSR(0x808, 0x78). 6866 * 2. L2 exits to L0 with a WRMSR exit. 6867 * 3. L0 emulates WRMSR, by writing L1's TPR. 6868 * 4. L0 re-enters L2. 6869 * 5. L2 exits to L0 (reason doesn't matter). 6870 * 6. L0 reflects L2's exit to L1. 6871 * 7. Before entering L1, L0 exits to user-space 6872 * (e.g., to satisfy TPR access reporting). 6873 * 8. User-space executes KVM_SET_REGS ioctl, which 6874 * clears the lower nibble of L1's TPR. 6875 */ 6876 if (reg == APIC_TASKPRI) { 6877 got = apic_virt_nibble1(got); 6878 val = apic_virt_nibble1(val); 6879 } 6880 6881 ok = got == val; 6882 report(ok, 6883 "non-virtualized write; val is 0x%x, want 0x%lx", 6884 got, val); 6885 apic_write(reg, restore_val); 6886 } else { 6887 report_pass("non-virtualized and write-only OK"); 6888 } 6889 } 6890 skip_exit_insn(); 6891 6892 report_prefix_pop(); 6893 } 6894 6895 static enum Config_type configure_virt_x2apic_mode_test( 6896 struct virt_x2apic_mode_config *virt_x2apic_mode_config, 6897 u8 *msr_bitmap_page) 6898 { 6899 int msr; 6900 u32 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6901 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6902 6903 /* x2apic-specific VMCS config */ 6904 if (virt_x2apic_mode_config->use_msr_bitmaps) { 6905 /* virt_x2apic_mode_test() checks for MSR bitmaps support */ 6906 cpu_exec_ctrl0 |= CPU_MSR_BITMAP; 6907 } else { 6908 cpu_exec_ctrl0 &= ~CPU_MSR_BITMAP; 6909 } 6910 6911 if (virt_x2apic_mode_config->virtual_interrupt_delivery) { 6912 if (!(ctrl_cpu_rev[1].clr & CPU_VINTD)) { 6913 report_skip("VM-execution control \"virtual-interrupt delivery\" NOT supported.\n"); 6914 return CONFIG_TYPE_UNSUPPORTED; 6915 } 6916 cpu_exec_ctrl1 |= CPU_VINTD; 6917 } else { 6918 cpu_exec_ctrl1 &= ~CPU_VINTD; 6919 } 6920 6921 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 6922 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 6923 6924 /* x2APIC MSR intercepts are usually off for "Virtualize x2APIC mode" */ 6925 for (msr = 0x800; msr <= 0x8ff; msr++) { 6926 if (virt_x2apic_mode_config->disable_x2apic_msr_intercepts) { 6927 clear_bit(msr, msr_bitmap_page + 0x000); 6928 clear_bit(msr, msr_bitmap_page + 0x800); 6929 } else { 6930 set_bit(msr, msr_bitmap_page + 0x000); 6931 set_bit(msr, msr_bitmap_page + 0x800); 6932 } 6933 } 6934 6935 /* x2APIC mode can impact virtualization */ 6936 reset_apic(); 6937 if (!virt_x2apic_mode_config->disable_x2apic) 6938 enable_x2apic(); 6939 6940 return configure_apic_reg_virt_test( 6941 &virt_x2apic_mode_config->apic_reg_virt_config); 6942 } 6943 6944 static void virt_x2apic_mode_test(void) 6945 { 6946 u32 *virtual_apic_page; 6947 u8 *msr_bitmap_page; 6948 u64 cpu_exec_ctrl0 = vmcs_read(CPU_EXEC_CTRL0); 6949 u64 cpu_exec_ctrl1 = vmcs_read(CPU_EXEC_CTRL1); 6950 int i; 6951 struct virt_x2apic_mode_guest_args *args = &virt_x2apic_mode_guest_args; 6952 6953 if (!cpu_has_apicv()) { 6954 report_skip(__func__); 6955 return; 6956 } 6957 6958 /* 6959 * This is to exercise an issue in KVM's logic to merge L0's and L1's 6960 * MSR bitmaps. Previously, an L1 could get at L0's x2APIC MSRs by 6961 * writing the IA32_SPEC_CTRL MSR or the IA32_PRED_CMD MSRs. KVM would 6962 * then proceed to manipulate the MSR bitmaps, as if VMCS12 had the 6963 * "Virtualize x2APIC mod" control set, even when it didn't. 6964 */ 6965 if (has_spec_ctrl()) 6966 wrmsr(MSR_IA32_SPEC_CTRL, 1); 6967 6968 /* 6969 * Check that VMCS12 supports: 6970 * - "Virtual-APIC address", indicated by "use TPR shadow" 6971 * - "MSR-bitmap address", indicated by "use MSR bitmaps" 6972 */ 6973 if (!(ctrl_cpu_rev[0].clr & CPU_TPR_SHADOW)) { 6974 report_skip("VM-execution control \"use TPR shadow\" NOT supported.\n"); 6975 return; 6976 } else if (!(ctrl_cpu_rev[0].clr & CPU_MSR_BITMAP)) { 6977 report_skip("VM-execution control \"use MSR bitmaps\" NOT supported.\n"); 6978 return; 6979 } 6980 6981 test_set_guest(virt_x2apic_mode_guest); 6982 6983 virtual_apic_page = alloc_page(); 6984 vmcs_write(APIC_VIRT_ADDR, virt_to_phys(virtual_apic_page)); 6985 6986 msr_bitmap_page = alloc_page(); 6987 memset(msr_bitmap_page, 0xff, PAGE_SIZE); 6988 vmcs_write(MSR_BITMAP, virt_to_phys(msr_bitmap_page)); 6989 6990 for (i = 0; i < ARRAY_SIZE(virt_x2apic_mode_tests); i++) { 6991 struct virt_x2apic_mode_test_case *virt_x2apic_mode_test_case = 6992 &virt_x2apic_mode_tests[i]; 6993 struct virt_x2apic_mode_config *virt_x2apic_mode_config = 6994 &virt_x2apic_mode_test_case->virt_x2apic_mode_config; 6995 enum Config_type config_type; 6996 u32 reg; 6997 6998 printf("--- %s test ---\n", virt_x2apic_mode_test_case->name); 6999 config_type = 7000 configure_virt_x2apic_mode_test(virt_x2apic_mode_config, 7001 msr_bitmap_page); 7002 if (config_type == CONFIG_TYPE_UNSUPPORTED) { 7003 report_skip("Skip because of missing features.\n"); 7004 continue; 7005 } else if (config_type == CONFIG_TYPE_VMENTRY_FAILS_EARLY) { 7006 enter_guest_with_bad_controls(); 7007 continue; 7008 } 7009 7010 for (reg = 0; reg < PAGE_SIZE / sizeof(u32); reg += 0x10) { 7011 struct virt_x2apic_mode_expectation expectation; 7012 7013 virt_x2apic_mode_exit_expectation( 7014 reg, virt_x2apic_mode_config, &expectation); 7015 7016 test_x2apic_rd(reg, &expectation, virtual_apic_page); 7017 test_x2apic_wr(reg, &expectation, virtual_apic_page); 7018 } 7019 } 7020 7021 7022 /* Terminate the guest */ 7023 vmcs_write(CPU_EXEC_CTRL0, cpu_exec_ctrl0); 7024 vmcs_write(CPU_EXEC_CTRL1, cpu_exec_ctrl1); 7025 args->op = X2APIC_TERMINATE; 7026 enter_guest(); 7027 assert_exit_reason(VMX_VMCALL); 7028 } 7029 7030 static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1) 7031 { 7032 u64 val; 7033 u64 cr_saved = vmcs_read(cr); 7034 int i; 7035 7036 val = fixed0 & fixed1; 7037 if (cr == HOST_CR4) 7038 vmcs_write(cr, val | X86_CR4_PAE); 7039 else 7040 vmcs_write(cr, val); 7041 report_prefix_pushf("%s %lx", cr_name, val); 7042 if (val == fixed0) 7043 test_vmx_vmlaunch(0); 7044 else 7045 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7046 report_prefix_pop(); 7047 7048 for (i = 0; i < 64; i++) { 7049 7050 /* Set a bit when the corresponding bit in fixed1 is 0 */ 7051 if ((fixed1 & (1ull << i)) == 0) { 7052 if (cr == HOST_CR4 && ((1ull << i) & X86_CR4_SMEP || 7053 (1ull << i) & X86_CR4_SMAP)) 7054 continue; 7055 7056 vmcs_write(cr, cr_saved | (1ull << i)); 7057 report_prefix_pushf("%s %llx", cr_name, 7058 cr_saved | (1ull << i)); 7059 test_vmx_vmlaunch( 7060 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7061 report_prefix_pop(); 7062 } 7063 7064 /* Unset a bit when the corresponding bit in fixed0 is 1 */ 7065 if (fixed0 & (1ull << i)) { 7066 vmcs_write(cr, cr_saved & ~(1ull << i)); 7067 report_prefix_pushf("%s %llx", cr_name, 7068 cr_saved & ~(1ull << i)); 7069 test_vmx_vmlaunch( 7070 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7071 report_prefix_pop(); 7072 } 7073 } 7074 7075 vmcs_write(cr, cr_saved); 7076 } 7077 7078 /* 7079 * 1. The CR0 field must not set any bit to a value not supported in VMX 7080 * operation. 7081 * 2. The CR4 field must not set any bit to a value not supported in VMX 7082 * operation. 7083 * 3. On processors that support Intel 64 architecture, the CR3 field must 7084 * be such that bits 63:52 and bits in the range 51:32 beyond the 7085 * processor's physical-address width must be 0. 7086 * 7087 * [Intel SDM] 7088 */ 7089 static void test_host_ctl_regs(void) 7090 { 7091 u64 fixed0, fixed1, cr3, cr3_saved; 7092 int i; 7093 7094 /* Test CR0 */ 7095 fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0); 7096 fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1); 7097 test_ctl_reg("HOST_CR0", HOST_CR0, fixed0, fixed1); 7098 7099 /* Test CR4 */ 7100 fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0); 7101 fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1) & 7102 ~(X86_CR4_SMEP | X86_CR4_SMAP); 7103 test_ctl_reg("HOST_CR4", HOST_CR4, fixed0, fixed1); 7104 7105 /* Test CR3 */ 7106 cr3_saved = vmcs_read(HOST_CR3); 7107 for (i = cpuid_maxphyaddr(); i < 64; i++) { 7108 cr3 = cr3_saved | (1ul << i); 7109 vmcs_write(HOST_CR3, cr3); 7110 report_prefix_pushf("HOST_CR3 %lx", cr3); 7111 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7112 report_prefix_pop(); 7113 } 7114 7115 vmcs_write(HOST_CR3, cr3_saved); 7116 } 7117 7118 static void test_efer_vmlaunch(u32 fld, bool ok) 7119 { 7120 if (fld == HOST_EFER) { 7121 if (ok) 7122 test_vmx_vmlaunch(0); 7123 else 7124 test_vmx_vmlaunch2(VMXERR_ENTRY_INVALID_CONTROL_FIELD, 7125 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7126 } else { 7127 test_guest_state("EFER test", !ok, GUEST_EFER, "GUEST_EFER"); 7128 } 7129 } 7130 7131 static void test_efer_one(u32 fld, const char * fld_name, u64 efer, 7132 u32 ctrl_fld, u64 ctrl, 7133 int i, const char *efer_bit_name) 7134 { 7135 bool ok; 7136 7137 ok = true; 7138 if (ctrl_fld == EXI_CONTROLS && (ctrl & EXI_LOAD_EFER)) { 7139 if (!!(efer & EFER_LMA) != !!(ctrl & EXI_HOST_64)) 7140 ok = false; 7141 if (!!(efer & EFER_LME) != !!(ctrl & EXI_HOST_64)) 7142 ok = false; 7143 } 7144 if (ctrl_fld == ENT_CONTROLS && (ctrl & ENT_LOAD_EFER)) { 7145 /* Check LMA too since CR0.PG is set. */ 7146 if (!!(efer & EFER_LMA) != !!(ctrl & ENT_GUEST_64)) 7147 ok = false; 7148 if (!!(efer & EFER_LME) != !!(ctrl & ENT_GUEST_64)) 7149 ok = false; 7150 } 7151 7152 /* 7153 * Skip the test if it would enter the guest in 32-bit mode. 7154 * Perhaps write the test in assembly and make sure it 7155 * can be run in either mode? 7156 */ 7157 if (fld == GUEST_EFER && ok && !(ctrl & ENT_GUEST_64)) 7158 return; 7159 7160 vmcs_write(ctrl_fld, ctrl); 7161 vmcs_write(fld, efer); 7162 report_prefix_pushf("%s %s bit turned %s, controls %s", 7163 fld_name, efer_bit_name, 7164 (i & 1) ? "on" : "off", 7165 (i & 2) ? "on" : "off"); 7166 7167 test_efer_vmlaunch(fld, ok); 7168 report_prefix_pop(); 7169 } 7170 7171 static void test_efer_bit(u32 fld, const char * fld_name, 7172 u32 ctrl_fld, u64 ctrl_bit, u64 efer_bit, 7173 const char *efer_bit_name) 7174 { 7175 u64 efer_saved = vmcs_read(fld); 7176 u32 ctrl_saved = vmcs_read(ctrl_fld); 7177 int i; 7178 7179 for (i = 0; i < 4; i++) { 7180 u64 efer = efer_saved & ~efer_bit; 7181 u64 ctrl = ctrl_saved & ~ctrl_bit; 7182 7183 if (i & 1) 7184 efer |= efer_bit; 7185 if (i & 2) 7186 ctrl |= ctrl_bit; 7187 7188 test_efer_one(fld, fld_name, efer, ctrl_fld, ctrl, 7189 i, efer_bit_name); 7190 } 7191 7192 vmcs_write(ctrl_fld, ctrl_saved); 7193 vmcs_write(fld, efer_saved); 7194 } 7195 7196 static void test_efer(u32 fld, const char * fld_name, u32 ctrl_fld, 7197 u64 ctrl_bit1, u64 ctrl_bit2) 7198 { 7199 u64 efer_saved = vmcs_read(fld); 7200 u32 ctrl_saved = vmcs_read(ctrl_fld); 7201 u64 efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); 7202 u64 i; 7203 u64 efer; 7204 7205 if (cpu_has_efer_nx()) 7206 efer_reserved_bits &= ~EFER_NX; 7207 7208 if (!ctrl_bit1) { 7209 printf("\"Load-IA32-EFER\" exit control not supported\n"); 7210 goto test_entry_exit_mode; 7211 } 7212 7213 report_prefix_pushf("%s %lx", fld_name, efer_saved); 7214 test_efer_vmlaunch(fld, true); 7215 report_prefix_pop(); 7216 7217 /* 7218 * Check reserved bits 7219 */ 7220 vmcs_write(ctrl_fld, ctrl_saved & ~ctrl_bit1); 7221 for (i = 0; i < 64; i++) { 7222 if ((1ull << i) & efer_reserved_bits) { 7223 efer = efer_saved | (1ull << i); 7224 vmcs_write(fld, efer); 7225 report_prefix_pushf("%s %lx", fld_name, efer); 7226 test_efer_vmlaunch(fld, true); 7227 report_prefix_pop(); 7228 } 7229 } 7230 7231 vmcs_write(ctrl_fld, ctrl_saved | ctrl_bit1); 7232 for (i = 0; i < 64; i++) { 7233 if ((1ull << i) & efer_reserved_bits) { 7234 efer = efer_saved | (1ull << i); 7235 vmcs_write(fld, efer); 7236 report_prefix_pushf("%s %lx", fld_name, efer); 7237 test_efer_vmlaunch(fld, false); 7238 report_prefix_pop(); 7239 } 7240 } 7241 7242 vmcs_write(ctrl_fld, ctrl_saved); 7243 vmcs_write(fld, efer_saved); 7244 7245 /* 7246 * Check LMA and LME bits 7247 */ 7248 test_efer_bit(fld, fld_name, 7249 ctrl_fld, ctrl_bit1, 7250 EFER_LMA, 7251 "EFER_LMA"); 7252 test_efer_bit(fld, fld_name, 7253 ctrl_fld, ctrl_bit1, 7254 EFER_LME, 7255 "EFER_LME"); 7256 7257 test_entry_exit_mode: 7258 test_efer_bit(fld, fld_name, 7259 ctrl_fld, ctrl_bit2, 7260 EFER_LMA, 7261 "EFER_LMA"); 7262 test_efer_bit(fld, fld_name, 7263 ctrl_fld, ctrl_bit2, 7264 EFER_LME, 7265 "EFER_LME"); 7266 } 7267 7268 /* 7269 * If the 'load IA32_EFER' VM-exit control is 1, bits reserved in the 7270 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7271 * the values of the LMA and LME bits in the field must each be that of 7272 * the 'host address-space size' VM-exit control. 7273 * 7274 * [Intel SDM] 7275 */ 7276 static void test_host_efer(void) 7277 { 7278 test_efer(HOST_EFER, "HOST_EFER", EXI_CONTROLS, 7279 ctrl_exit_rev.clr & EXI_LOAD_EFER, 7280 EXI_HOST_64); 7281 } 7282 7283 /* 7284 * If the 'load IA32_EFER' VM-enter control is 1, bits reserved in the 7285 * IA32_EFER MSR must be 0 in the field for that register. In addition, 7286 * the values of the LMA and LME bits in the field must each be that of 7287 * the 'IA32e-mode guest' VM-exit control. 7288 */ 7289 static void test_guest_efer(void) 7290 { 7291 if (!(ctrl_enter_rev.clr & ENT_LOAD_EFER)) { 7292 printf("\"Load-IA32-EFER\" entry control not supported\n"); 7293 return; 7294 } 7295 7296 vmcs_write(GUEST_EFER, rdmsr(MSR_EFER)); 7297 test_efer(GUEST_EFER, "GUEST_EFER", ENT_CONTROLS, 7298 ctrl_enter_rev.clr & ENT_LOAD_EFER, 7299 ENT_GUEST_64); 7300 } 7301 7302 /* 7303 * PAT values higher than 8 are uninteresting since they're likely lumped 7304 * in with "8". We only test values above 8 one bit at a time, 7305 * in order to reduce the number of VM-Entries and keep the runtime reasonable. 7306 */ 7307 #define PAT_VAL_LIMIT 8 7308 7309 static void test_pat(u32 field, const char * field_name, u32 ctrl_field, 7310 u64 ctrl_bit) 7311 { 7312 u32 ctrl_saved = vmcs_read(ctrl_field); 7313 u64 pat_saved = vmcs_read(field); 7314 u64 i, val; 7315 u32 j; 7316 int error; 7317 7318 vmcs_clear_bits(ctrl_field, ctrl_bit); 7319 7320 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7321 /* Test PAT0..PAT7 fields */ 7322 for (j = 0; j < (i ? 8 : 1); j++) { 7323 val = i << j * 8; 7324 vmcs_write(field, val); 7325 if (field == HOST_PAT) { 7326 report_prefix_pushf("%s %lx", field_name, val); 7327 test_vmx_vmlaunch(0); 7328 report_prefix_pop(); 7329 7330 } else { // GUEST_PAT 7331 test_guest_state("ENT_LOAD_PAT enabled", false, 7332 val, "GUEST_PAT"); 7333 } 7334 } 7335 } 7336 7337 vmcs_set_bits(ctrl_field, ctrl_bit); 7338 for (i = 0; i < 256; i = (i < PAT_VAL_LIMIT) ? i + 1 : i * 2) { 7339 /* Test PAT0..PAT7 fields */ 7340 for (j = 0; j < (i ? 8 : 1); j++) { 7341 val = i << j * 8; 7342 vmcs_write(field, val); 7343 7344 if (field == HOST_PAT) { 7345 report_prefix_pushf("%s %lx", field_name, val); 7346 if (i == 0x2 || i == 0x3 || i >= 0x8) 7347 error = 7348 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD; 7349 else 7350 error = 0; 7351 7352 test_vmx_vmlaunch(error); 7353 report_prefix_pop(); 7354 7355 } else { // GUEST_PAT 7356 error = (i == 0x2 || i == 0x3 || i >= 0x8); 7357 test_guest_state("ENT_LOAD_PAT enabled", !!error, 7358 val, "GUEST_PAT"); 7359 } 7360 7361 } 7362 } 7363 7364 vmcs_write(ctrl_field, ctrl_saved); 7365 vmcs_write(field, pat_saved); 7366 } 7367 7368 /* 7369 * If the "load IA32_PAT" VM-exit control is 1, the value of the field 7370 * for the IA32_PAT MSR must be one that could be written by WRMSR 7371 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7372 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7373 * 6 (WB), or 7 (UC-). 7374 * 7375 * [Intel SDM] 7376 */ 7377 static void test_load_host_pat(void) 7378 { 7379 /* 7380 * "load IA32_PAT" VM-exit control 7381 */ 7382 if (!(ctrl_exit_rev.clr & EXI_LOAD_PAT)) { 7383 printf("\"Load-IA32-PAT\" exit control not supported\n"); 7384 return; 7385 } 7386 7387 test_pat(HOST_PAT, "HOST_PAT", EXI_CONTROLS, EXI_LOAD_PAT); 7388 } 7389 7390 union cpuidA_eax { 7391 struct { 7392 unsigned int version_id:8; 7393 unsigned int num_counters_gp:8; 7394 unsigned int bit_width:8; 7395 unsigned int mask_length:8; 7396 } split; 7397 unsigned int full; 7398 }; 7399 7400 union cpuidA_edx { 7401 struct { 7402 unsigned int num_counters_fixed:5; 7403 unsigned int bit_width_fixed:8; 7404 unsigned int reserved:9; 7405 } split; 7406 unsigned int full; 7407 }; 7408 7409 static bool valid_pgc(u64 val) 7410 { 7411 struct cpuid id; 7412 union cpuidA_eax eax; 7413 union cpuidA_edx edx; 7414 u64 mask; 7415 7416 id = cpuid(0xA); 7417 eax.full = id.a; 7418 edx.full = id.d; 7419 mask = ~(((1ull << eax.split.num_counters_gp) - 1) | 7420 (((1ull << edx.split.num_counters_fixed) - 1) << 32)); 7421 7422 return !(val & mask); 7423 } 7424 7425 static void test_pgc_vmlaunch(u32 xerror, u32 xreason, bool xfail, bool host) 7426 { 7427 u32 inst_err; 7428 u64 obs; 7429 bool success; 7430 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7431 7432 if (host) { 7433 success = vmlaunch_succeeds(); 7434 obs = rdmsr(data->msr); 7435 if (!success) { 7436 inst_err = vmcs_read(VMX_INST_ERROR); 7437 report(xerror == inst_err, "vmlaunch failed, " 7438 "VMX Inst Error is %d (expected %d)", 7439 inst_err, xerror); 7440 } else { 7441 report(!data->enabled || data->exp == obs, 7442 "Host state is 0x%lx (expected 0x%lx)", 7443 obs, data->exp); 7444 report(success != xfail, "vmlaunch succeeded"); 7445 } 7446 } else { 7447 test_guest_state("load GUEST_PERF_GLOBAL_CTRL", xfail, 7448 GUEST_PERF_GLOBAL_CTRL, 7449 "GUEST_PERF_GLOBAL_CTRL"); 7450 } 7451 } 7452 7453 /* 7454 * test_load_perf_global_ctrl is a generic function for testing the 7455 * "load IA32_PERF_GLOBAL_CTRL" VM-{Entry,Exit} controls. This test function 7456 * tests the provided ctrl_val when disabled and enabled. 7457 * 7458 * @nr: VMCS field number corresponding to the host/guest state field 7459 * @name: Name of the above VMCS field for printing in test report 7460 * @ctrl_nr: VMCS field number corresponding to the VM-{Entry,Exit} control 7461 * @ctrl_val: Bit to set on the ctrl_field 7462 */ 7463 static void test_perf_global_ctrl(u32 nr, const char *name, u32 ctrl_nr, 7464 const char *ctrl_name, u64 ctrl_val) 7465 { 7466 u64 ctrl_saved = vmcs_read(ctrl_nr); 7467 u64 pgc_saved = vmcs_read(nr); 7468 u64 i, val; 7469 bool host = nr == HOST_PERF_GLOBAL_CTRL; 7470 struct vmx_state_area_test_data *data = &vmx_state_area_test_data; 7471 7472 data->msr = MSR_CORE_PERF_GLOBAL_CTRL; 7473 msr_bmp_init(); 7474 vmcs_write(ctrl_nr, ctrl_saved & ~ctrl_val); 7475 data->enabled = false; 7476 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=0 on %s", 7477 ctrl_name); 7478 7479 for (i = 0; i < 64; i++) { 7480 val = 1ull << i; 7481 vmcs_write(nr, val); 7482 report_prefix_pushf("%s = 0x%lx", name, val); 7483 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7484 report_prefix_pop(); 7485 } 7486 report_prefix_pop(); 7487 7488 vmcs_write(ctrl_nr, ctrl_saved | ctrl_val); 7489 data->enabled = true; 7490 report_prefix_pushf("\"load IA32_PERF_GLOBAL_CTRL\"=1 on %s", 7491 ctrl_name); 7492 for (i = 0; i < 64; i++) { 7493 val = 1ull << i; 7494 data->exp = val; 7495 vmcs_write(nr, val); 7496 report_prefix_pushf("%s = 0x%lx", name, val); 7497 if (valid_pgc(val)) { 7498 test_pgc_vmlaunch(0, VMX_VMCALL, false, host); 7499 } else { 7500 if (host) 7501 test_pgc_vmlaunch( 7502 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, 7503 0, 7504 true, 7505 host); 7506 else 7507 test_pgc_vmlaunch( 7508 0, 7509 VMX_ENTRY_FAILURE | VMX_FAIL_STATE, 7510 true, 7511 host); 7512 } 7513 report_prefix_pop(); 7514 } 7515 7516 data->enabled = false; 7517 report_prefix_pop(); 7518 vmcs_write(ctrl_nr, ctrl_saved); 7519 vmcs_write(nr, pgc_saved); 7520 } 7521 7522 static void test_load_host_perf_global_ctrl(void) 7523 { 7524 if (!(ctrl_exit_rev.clr & EXI_LOAD_PERF)) { 7525 printf("\"load IA32_PERF_GLOBAL_CTRL\" exit control not supported\n"); 7526 return; 7527 } 7528 7529 test_perf_global_ctrl(HOST_PERF_GLOBAL_CTRL, "HOST_PERF_GLOBAL_CTRL", 7530 EXI_CONTROLS, "EXI_CONTROLS", EXI_LOAD_PERF); 7531 } 7532 7533 7534 static void test_load_guest_perf_global_ctrl(void) 7535 { 7536 if (!(ctrl_enter_rev.clr & ENT_LOAD_PERF)) { 7537 printf("\"load IA32_PERF_GLOBAL_CTRL\" entry control not supported\n"); 7538 return; 7539 } 7540 7541 test_perf_global_ctrl(GUEST_PERF_GLOBAL_CTRL, "GUEST_PERF_GLOBAL_CTRL", 7542 ENT_CONTROLS, "ENT_CONTROLS", ENT_LOAD_PERF); 7543 } 7544 7545 7546 /* 7547 * test_vmcs_field - test a value for the given VMCS field 7548 * @field: VMCS field 7549 * @field_name: string name of VMCS field 7550 * @bit_start: starting bit 7551 * @bit_end: ending bit 7552 * @val: value that the bit range must or must not contain 7553 * @valid_val: whether value given in 'val' must be valid or not 7554 * @error: expected VMCS error when vmentry fails for an invalid value 7555 */ 7556 static void test_vmcs_field(u64 field, const char *field_name, u32 bit_start, 7557 u32 bit_end, u64 val, bool valid_val, u32 error) 7558 { 7559 u64 field_saved = vmcs_read(field); 7560 u32 i; 7561 u64 tmp; 7562 u32 bit_on; 7563 u64 mask = ~0ull; 7564 7565 mask = (mask >> bit_end) << bit_end; 7566 mask = mask | ((1 << bit_start) - 1); 7567 tmp = (field_saved & mask) | (val << bit_start); 7568 7569 vmcs_write(field, tmp); 7570 report_prefix_pushf("%s %lx", field_name, tmp); 7571 if (valid_val) 7572 test_vmx_vmlaunch(0); 7573 else 7574 test_vmx_vmlaunch(error); 7575 report_prefix_pop(); 7576 7577 for (i = bit_start; i <= bit_end; i = i + 2) { 7578 bit_on = ((1ull < i) & (val << bit_start)) ? 0 : 1; 7579 if (bit_on) 7580 tmp = field_saved | (1ull << i); 7581 else 7582 tmp = field_saved & ~(1ull << i); 7583 vmcs_write(field, tmp); 7584 report_prefix_pushf("%s %lx", field_name, tmp); 7585 if (valid_val) 7586 test_vmx_vmlaunch(error); 7587 else 7588 test_vmx_vmlaunch(0); 7589 report_prefix_pop(); 7590 } 7591 7592 vmcs_write(field, field_saved); 7593 } 7594 7595 static void test_canonical(u64 field, const char * field_name, bool host) 7596 { 7597 u64 addr_saved = vmcs_read(field); 7598 7599 /* 7600 * Use the existing value if possible. Writing a random canonical 7601 * value is not an option as doing so would corrupt the field being 7602 * tested and likely hose the test. 7603 */ 7604 if (is_canonical(addr_saved)) { 7605 if (host) { 7606 report_prefix_pushf("%s %lx", field_name, addr_saved); 7607 test_vmx_vmlaunch(0); 7608 report_prefix_pop(); 7609 } else { 7610 test_guest_state("Test canonical address", false, 7611 addr_saved, field_name); 7612 } 7613 } 7614 7615 vmcs_write(field, NONCANONICAL); 7616 7617 if (host) { 7618 report_prefix_pushf("%s %llx", field_name, NONCANONICAL); 7619 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7620 report_prefix_pop(); 7621 } else { 7622 test_guest_state("Test non-canonical address", true, 7623 NONCANONICAL, field_name); 7624 } 7625 7626 vmcs_write(field, addr_saved); 7627 } 7628 7629 #define TEST_RPL_TI_FLAGS(reg, name) \ 7630 test_vmcs_field(reg, name, 0, 2, 0x0, true, \ 7631 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7632 7633 #define TEST_CS_TR_FLAGS(reg, name) \ 7634 test_vmcs_field(reg, name, 3, 15, 0x0000, false, \ 7635 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7636 7637 /* 7638 * 1. In the selector field for each of CS, SS, DS, ES, FS, GS and TR, the 7639 * RPL (bits 1:0) and the TI flag (bit 2) must be 0. 7640 * 2. The selector fields for CS and TR cannot be 0000H. 7641 * 3. The selector field for SS cannot be 0000H if the "host address-space 7642 * size" VM-exit control is 0. 7643 * 4. On processors that support Intel 64 architecture, the base-address 7644 * fields for FS, GS and TR must contain canonical addresses. 7645 */ 7646 static void test_host_segment_regs(void) 7647 { 7648 u16 selector_saved; 7649 7650 /* 7651 * Test RPL and TI flags 7652 */ 7653 TEST_RPL_TI_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7654 TEST_RPL_TI_FLAGS(HOST_SEL_SS, "HOST_SEL_SS"); 7655 TEST_RPL_TI_FLAGS(HOST_SEL_DS, "HOST_SEL_DS"); 7656 TEST_RPL_TI_FLAGS(HOST_SEL_ES, "HOST_SEL_ES"); 7657 TEST_RPL_TI_FLAGS(HOST_SEL_FS, "HOST_SEL_FS"); 7658 TEST_RPL_TI_FLAGS(HOST_SEL_GS, "HOST_SEL_GS"); 7659 TEST_RPL_TI_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7660 7661 /* 7662 * Test that CS and TR fields can not be 0x0000 7663 */ 7664 TEST_CS_TR_FLAGS(HOST_SEL_CS, "HOST_SEL_CS"); 7665 TEST_CS_TR_FLAGS(HOST_SEL_TR, "HOST_SEL_TR"); 7666 7667 /* 7668 * SS field can not be 0x0000 if "host address-space size" VM-exit 7669 * control is 0 7670 */ 7671 selector_saved = vmcs_read(HOST_SEL_SS); 7672 vmcs_write(HOST_SEL_SS, 0); 7673 report_prefix_pushf("HOST_SEL_SS 0"); 7674 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7675 test_vmx_vmlaunch(0); 7676 } else { 7677 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7678 } 7679 report_prefix_pop(); 7680 7681 vmcs_write(HOST_SEL_SS, selector_saved); 7682 7683 /* 7684 * Base address for FS, GS and TR must be canonical 7685 */ 7686 test_canonical(HOST_BASE_FS, "HOST_BASE_FS", true); 7687 test_canonical(HOST_BASE_GS, "HOST_BASE_GS", true); 7688 test_canonical(HOST_BASE_TR, "HOST_BASE_TR", true); 7689 } 7690 7691 /* 7692 * On processors that support Intel 64 architecture, the base-address 7693 * fields for GDTR and IDTR must contain canonical addresses. 7694 */ 7695 static void test_host_desc_tables(void) 7696 { 7697 test_canonical(HOST_BASE_GDTR, "HOST_BASE_GDTR", true); 7698 test_canonical(HOST_BASE_IDTR, "HOST_BASE_IDTR", true); 7699 } 7700 7701 /* 7702 * If the "host address-space size" VM-exit control is 0, the following must 7703 * hold: 7704 * - The "IA-32e mode guest" VM-entry control is 0. 7705 * - Bit 17 of the CR4 field (corresponding to CR4.PCIDE) is 0. 7706 * - Bits 63:32 in the RIP field are 0. 7707 * 7708 * If the "host address-space size" VM-exit control is 1, the following must 7709 * hold: 7710 * - Bit 5 of the CR4 field (corresponding to CR4.PAE) is 1. 7711 * - The RIP field contains a canonical address. 7712 * 7713 */ 7714 static void test_host_addr_size(void) 7715 { 7716 u64 cr4_saved = vmcs_read(HOST_CR4); 7717 u64 rip_saved = vmcs_read(HOST_RIP); 7718 u64 entry_ctrl_saved = vmcs_read(ENT_CONTROLS); 7719 int i; 7720 u64 tmp; 7721 7722 if (vmcs_read(EXI_CONTROLS) & EXI_HOST_64) { 7723 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7724 report_prefix_pushf("\"IA-32e mode guest\" enabled"); 7725 test_vmx_vmlaunch(0); 7726 report_prefix_pop(); 7727 7728 vmcs_write(HOST_CR4, cr4_saved | X86_CR4_PCIDE); 7729 report_prefix_pushf("\"CR4.PCIDE\" set"); 7730 test_vmx_vmlaunch(0); 7731 report_prefix_pop(); 7732 7733 for (i = 32; i <= 63; i = i + 4) { 7734 tmp = rip_saved | 1ull << i; 7735 vmcs_write(HOST_RIP, tmp); 7736 report_prefix_pushf("HOST_RIP %lx", tmp); 7737 test_vmx_vmlaunch(0); 7738 report_prefix_pop(); 7739 } 7740 7741 if (cr4_saved & X86_CR4_PAE) { 7742 vmcs_write(HOST_CR4, cr4_saved & ~X86_CR4_PAE); 7743 report_prefix_pushf("\"CR4.PAE\" unset"); 7744 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7745 } else { 7746 report_prefix_pushf("\"CR4.PAE\" set"); 7747 test_vmx_vmlaunch(0); 7748 } 7749 report_prefix_pop(); 7750 7751 vmcs_write(HOST_RIP, NONCANONICAL); 7752 report_prefix_pushf("HOST_RIP %llx", NONCANONICAL); 7753 test_vmx_vmlaunch(VMXERR_ENTRY_INVALID_HOST_STATE_FIELD); 7754 report_prefix_pop(); 7755 7756 vmcs_write(ENT_CONTROLS, entry_ctrl_saved | ENT_GUEST_64); 7757 vmcs_write(HOST_RIP, rip_saved); 7758 vmcs_write(HOST_CR4, cr4_saved); 7759 7760 /* Restore host's active RIP and CR4 values. */ 7761 report_prefix_pushf("restore host state"); 7762 test_vmx_vmlaunch(0); 7763 report_prefix_pop(); 7764 } 7765 } 7766 7767 /* 7768 * Check that the virtual CPU checks the VMX Host State Area as 7769 * documented in the Intel SDM. 7770 */ 7771 static void vmx_host_state_area_test(void) 7772 { 7773 /* 7774 * Bit 1 of the guest's RFLAGS must be 1, or VM-entry will 7775 * fail due to invalid guest state, should we make it that 7776 * far. 7777 */ 7778 vmcs_write(GUEST_RFLAGS, 0); 7779 7780 test_host_ctl_regs(); 7781 7782 test_canonical(HOST_SYSENTER_ESP, "HOST_SYSENTER_ESP", true); 7783 test_canonical(HOST_SYSENTER_EIP, "HOST_SYSENTER_EIP", true); 7784 7785 test_host_efer(); 7786 test_load_host_pat(); 7787 test_host_segment_regs(); 7788 test_host_desc_tables(); 7789 test_host_addr_size(); 7790 test_load_host_perf_global_ctrl(); 7791 } 7792 7793 /* 7794 * If the "load debug controls" VM-entry control is 1, bits 63:32 in 7795 * the DR7 field must be 0. 7796 * 7797 * [Intel SDM] 7798 */ 7799 static void test_guest_dr7(void) 7800 { 7801 u32 ent_saved = vmcs_read(ENT_CONTROLS); 7802 u64 dr7_saved = vmcs_read(GUEST_DR7); 7803 u64 val; 7804 int i; 7805 7806 if (ctrl_enter_rev.set & ENT_LOAD_DBGCTLS) { 7807 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7808 for (i = 0; i < 64; i++) { 7809 val = 1ull << i; 7810 vmcs_write(GUEST_DR7, val); 7811 test_guest_state("ENT_LOAD_DBGCTLS disabled", false, 7812 val, "GUEST_DR7"); 7813 } 7814 } 7815 if (ctrl_enter_rev.clr & ENT_LOAD_DBGCTLS) { 7816 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_DBGCTLS); 7817 for (i = 0; i < 64; i++) { 7818 val = 1ull << i; 7819 vmcs_write(GUEST_DR7, val); 7820 test_guest_state("ENT_LOAD_DBGCTLS enabled", i >= 32, 7821 val, "GUEST_DR7"); 7822 } 7823 } 7824 vmcs_write(GUEST_DR7, dr7_saved); 7825 vmcs_write(ENT_CONTROLS, ent_saved); 7826 } 7827 7828 /* 7829 * If the "load IA32_PAT" VM-entry control is 1, the value of the field 7830 * for the IA32_PAT MSR must be one that could be written by WRMSR 7831 * without fault at CPL 0. Specifically, each of the 8 bytes in the 7832 * field must have one of the values 0 (UC), 1 (WC), 4 (WT), 5 (WP), 7833 * 6 (WB), or 7 (UC-). 7834 * 7835 * [Intel SDM] 7836 */ 7837 static void test_load_guest_pat(void) 7838 { 7839 /* 7840 * "load IA32_PAT" VM-entry control 7841 */ 7842 if (!(ctrl_enter_rev.clr & ENT_LOAD_PAT)) { 7843 printf("\"Load-IA32-PAT\" entry control not supported\n"); 7844 return; 7845 } 7846 7847 test_pat(GUEST_PAT, "GUEST_PAT", ENT_CONTROLS, ENT_LOAD_PAT); 7848 } 7849 7850 #define MSR_IA32_BNDCFGS_RSVD_MASK 0x00000ffc 7851 7852 /* 7853 * If the "load IA32_BNDCFGS" VM-entry control is 1, the following 7854 * checks are performed on the field for the IA32_BNDCFGS MSR: 7855 * 7856 * - Bits reserved in the IA32_BNDCFGS MSR must be 0. 7857 * - The linear address in bits 63:12 must be canonical. 7858 * 7859 * [Intel SDM] 7860 */ 7861 static void test_load_guest_bndcfgs(void) 7862 { 7863 u64 bndcfgs_saved = vmcs_read(GUEST_BNDCFGS); 7864 u64 bndcfgs; 7865 7866 if (!(ctrl_enter_rev.clr & ENT_LOAD_BNDCFGS)) { 7867 printf("\"Load-IA32-BNDCFGS\" entry control not supported\n"); 7868 return; 7869 } 7870 7871 vmcs_clear_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7872 7873 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7874 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7875 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7876 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7877 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7878 test_guest_state("ENT_LOAD_BNDCFGS disabled", false, 7879 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7880 7881 vmcs_set_bits(ENT_CONTROLS, ENT_LOAD_BNDCFGS); 7882 7883 vmcs_write(GUEST_BNDCFGS, NONCANONICAL); 7884 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7885 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7886 bndcfgs = bndcfgs_saved | MSR_IA32_BNDCFGS_RSVD_MASK; 7887 vmcs_write(GUEST_BNDCFGS, bndcfgs); 7888 test_guest_state("ENT_LOAD_BNDCFGS enabled", true, 7889 GUEST_BNDCFGS, "GUEST_BNDCFGS"); 7890 7891 vmcs_write(GUEST_BNDCFGS, bndcfgs_saved); 7892 } 7893 7894 #define GUEST_SEG_UNUSABLE_MASK (1u << 16) 7895 #define GUEST_SEG_SEL_TI_MASK (1u << 2) 7896 7897 7898 #define TEST_SEGMENT_SEL(test, xfail, sel, val) \ 7899 do { \ 7900 vmcs_write(sel, val); \ 7901 test_guest_state(test " segment", xfail, val, xstr(sel)); \ 7902 } while (0) 7903 7904 #define TEST_INVALID_SEG_SEL(sel, val) \ 7905 TEST_SEGMENT_SEL("Invalid: " xstr(val), true, sel, val); 7906 7907 #define TEST_VALID_SEG_SEL(sel, val) \ 7908 TEST_SEGMENT_SEL("Valid: " xstr(val), false, sel, val); 7909 7910 /* 7911 * The following checks are done on the Selector field of the Guest Segment 7912 * Registers: 7913 * - TR. The TI flag (bit 2) must be 0. 7914 * - LDTR. If LDTR is usable, the TI flag (bit 2) must be 0. 7915 * - SS. If the guest will not be virtual-8086 and the "unrestricted 7916 * guest" VM-execution control is 0, the RPL (bits 1:0) must equal 7917 * the RPL of the selector field for CS. 7918 * 7919 * [Intel SDM] 7920 */ 7921 static void test_guest_segment_sel_fields(void) 7922 { 7923 u16 sel_saved; 7924 u32 ar_saved; 7925 u32 cpu_ctrl0_saved; 7926 u32 cpu_ctrl1_saved; 7927 u16 cs_rpl_bits; 7928 7929 /* 7930 * Test for GUEST_SEL_TR 7931 */ 7932 sel_saved = vmcs_read(GUEST_SEL_TR); 7933 TEST_INVALID_SEG_SEL(GUEST_SEL_TR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7934 vmcs_write(GUEST_SEL_TR, sel_saved); 7935 7936 /* 7937 * Test for GUEST_SEL_LDTR 7938 */ 7939 sel_saved = vmcs_read(GUEST_SEL_LDTR); 7940 ar_saved = vmcs_read(GUEST_AR_LDTR); 7941 /* LDTR is set unusable */ 7942 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7943 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7944 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7945 /* LDTR is set usable */ 7946 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7947 TEST_INVALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved | GUEST_SEG_SEL_TI_MASK); 7948 7949 TEST_VALID_SEG_SEL(GUEST_SEL_LDTR, sel_saved & ~GUEST_SEG_SEL_TI_MASK); 7950 7951 vmcs_write(GUEST_AR_LDTR, ar_saved); 7952 vmcs_write(GUEST_SEL_LDTR, sel_saved); 7953 7954 /* 7955 * Test for GUEST_SEL_SS 7956 */ 7957 cpu_ctrl0_saved = vmcs_read(CPU_EXEC_CTRL0); 7958 cpu_ctrl1_saved = vmcs_read(CPU_EXEC_CTRL1); 7959 ar_saved = vmcs_read(GUEST_AR_SS); 7960 /* Turn off "unrestricted guest" vm-execution control */ 7961 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved & ~CPU_URG); 7962 cs_rpl_bits = vmcs_read(GUEST_SEL_CS) & 0x3; 7963 sel_saved = vmcs_read(GUEST_SEL_SS); 7964 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7965 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7966 /* Make SS usable if it's unusable or vice-versa */ 7967 if (ar_saved & GUEST_SEG_UNUSABLE_MASK) 7968 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7969 else 7970 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7971 TEST_INVALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7972 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7973 7974 /* Need a valid EPTP as the passing case fully enters the guest. */ 7975 if (enable_unrestricted_guest(true)) 7976 goto skip_ss_tests; 7977 7978 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7979 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7980 7981 /* Make SS usable if it's unusable or vice-versa */ 7982 if (vmcs_read(GUEST_AR_SS) & GUEST_SEG_UNUSABLE_MASK) 7983 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 7984 else 7985 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 7986 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (~cs_rpl_bits & 0x3))); 7987 TEST_VALID_SEG_SEL(GUEST_SEL_SS, ((sel_saved & ~0x3) | (cs_rpl_bits & 0x3))); 7988 skip_ss_tests: 7989 7990 vmcs_write(GUEST_AR_SS, ar_saved); 7991 vmcs_write(GUEST_SEL_SS, sel_saved); 7992 vmcs_write(CPU_EXEC_CTRL0, cpu_ctrl0_saved); 7993 vmcs_write(CPU_EXEC_CTRL1, cpu_ctrl1_saved); 7994 } 7995 7996 #define TEST_SEGMENT_BASE_ADDR_UPPER_BITS(xfail, seg_base) \ 7997 do { \ 7998 addr_saved = vmcs_read(seg_base); \ 7999 for (i = 32; i < 63; i = i + 4) { \ 8000 addr = addr_saved | 1ull << i; \ 8001 vmcs_write(seg_base, addr); \ 8002 test_guest_state("seg.BASE[63:32] != 0, usable = " xstr(xfail), \ 8003 xfail, addr, xstr(seg_base)); \ 8004 } \ 8005 vmcs_write(seg_base, addr_saved); \ 8006 } while (0) 8007 8008 #define TEST_SEGMENT_BASE_ADDR_CANONICAL(xfail, seg_base) \ 8009 do { \ 8010 addr_saved = vmcs_read(seg_base); \ 8011 vmcs_write(seg_base, NONCANONICAL); \ 8012 test_guest_state("seg.BASE non-canonical, usable = " xstr(xfail), \ 8013 xfail, NONCANONICAL, xstr(seg_base)); \ 8014 vmcs_write(seg_base, addr_saved); \ 8015 } while (0) 8016 8017 /* 8018 * The following checks are done on the Base Address field of the Guest 8019 * Segment Registers on processors that support Intel 64 architecture: 8020 * - TR, FS, GS : The address must be canonical. 8021 * - LDTR : If LDTR is usable, the address must be canonical. 8022 * - CS : Bits 63:32 of the address must be zero. 8023 * - SS, DS, ES : If the register is usable, bits 63:32 of the address 8024 * must be zero. 8025 * 8026 * [Intel SDM] 8027 */ 8028 static void test_guest_segment_base_addr_fields(void) 8029 { 8030 u64 addr_saved; 8031 u64 addr; 8032 u32 ar_saved; 8033 int i; 8034 8035 /* 8036 * The address of TR, FS, GS and LDTR must be canonical. 8037 */ 8038 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_TR); 8039 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_FS); 8040 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_GS); 8041 ar_saved = vmcs_read(GUEST_AR_LDTR); 8042 /* Make LDTR unusable */ 8043 vmcs_write(GUEST_AR_LDTR, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8044 TEST_SEGMENT_BASE_ADDR_CANONICAL(false, GUEST_BASE_LDTR); 8045 /* Make LDTR usable */ 8046 vmcs_write(GUEST_AR_LDTR, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8047 TEST_SEGMENT_BASE_ADDR_CANONICAL(true, GUEST_BASE_LDTR); 8048 8049 vmcs_write(GUEST_AR_LDTR, ar_saved); 8050 8051 /* 8052 * Bits 63:32 in CS, SS, DS and ES base address must be zero 8053 */ 8054 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_CS); 8055 ar_saved = vmcs_read(GUEST_AR_SS); 8056 /* Make SS unusable */ 8057 vmcs_write(GUEST_AR_SS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8058 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_SS); 8059 /* Make SS usable */ 8060 vmcs_write(GUEST_AR_SS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8061 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_SS); 8062 vmcs_write(GUEST_AR_SS, ar_saved); 8063 8064 ar_saved = vmcs_read(GUEST_AR_DS); 8065 /* Make DS unusable */ 8066 vmcs_write(GUEST_AR_DS, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8067 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_DS); 8068 /* Make DS usable */ 8069 vmcs_write(GUEST_AR_DS, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8070 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_DS); 8071 vmcs_write(GUEST_AR_DS, ar_saved); 8072 8073 ar_saved = vmcs_read(GUEST_AR_ES); 8074 /* Make ES unusable */ 8075 vmcs_write(GUEST_AR_ES, ar_saved | GUEST_SEG_UNUSABLE_MASK); 8076 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(false, GUEST_BASE_ES); 8077 /* Make ES usable */ 8078 vmcs_write(GUEST_AR_ES, ar_saved & ~GUEST_SEG_UNUSABLE_MASK); 8079 TEST_SEGMENT_BASE_ADDR_UPPER_BITS(true, GUEST_BASE_ES); 8080 vmcs_write(GUEST_AR_ES, ar_saved); 8081 } 8082 8083 /* 8084 * Check that the virtual CPU checks the VMX Guest State Area as 8085 * documented in the Intel SDM. 8086 */ 8087 static void vmx_guest_state_area_test(void) 8088 { 8089 vmx_set_test_stage(1); 8090 test_set_guest(guest_state_test_main); 8091 8092 /* 8093 * The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field 8094 * must each contain a canonical address. 8095 */ 8096 test_canonical(GUEST_SYSENTER_ESP, "GUEST_SYSENTER_ESP", false); 8097 test_canonical(GUEST_SYSENTER_EIP, "GUEST_SYSENTER_EIP", false); 8098 8099 test_guest_dr7(); 8100 test_load_guest_pat(); 8101 test_guest_efer(); 8102 test_load_guest_perf_global_ctrl(); 8103 test_load_guest_bndcfgs(); 8104 8105 test_guest_segment_sel_fields(); 8106 test_guest_segment_base_addr_fields(); 8107 8108 test_canonical(GUEST_BASE_GDTR, "GUEST_BASE_GDTR", false); 8109 test_canonical(GUEST_BASE_IDTR, "GUEST_BASE_IDTR", false); 8110 8111 u32 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_GDTR); 8112 int i; 8113 for (i = 16; i <= 31; i++) { 8114 u32 tmp = guest_desc_limit_saved | (1ull << i); 8115 vmcs_write(GUEST_LIMIT_GDTR, tmp); 8116 test_guest_state("GDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_GDTR"); 8117 } 8118 vmcs_write(GUEST_LIMIT_GDTR, guest_desc_limit_saved); 8119 8120 guest_desc_limit_saved = vmcs_read(GUEST_LIMIT_IDTR); 8121 for (i = 16; i <= 31; i++) { 8122 u32 tmp = guest_desc_limit_saved | (1ull << i); 8123 vmcs_write(GUEST_LIMIT_IDTR, tmp); 8124 test_guest_state("IDT.limit > 0xffff", true, tmp, "GUEST_LIMIT_IDTR"); 8125 } 8126 vmcs_write(GUEST_LIMIT_IDTR, guest_desc_limit_saved); 8127 8128 /* 8129 * Let the guest finish execution 8130 */ 8131 vmx_set_test_stage(2); 8132 enter_guest(); 8133 } 8134 8135 extern void unrestricted_guest_main(void); 8136 asm (".code32\n" 8137 "unrestricted_guest_main:\n" 8138 "vmcall\n" 8139 "nop\n" 8140 "mov $1, %edi\n" 8141 "call hypercall\n" 8142 ".code64\n"); 8143 8144 static void setup_unrestricted_guest(void) 8145 { 8146 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) & ~(X86_CR0_PG)); 8147 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) & ~ENT_GUEST_64); 8148 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) & ~EFER_LMA); 8149 vmcs_write(GUEST_RIP, virt_to_phys(unrestricted_guest_main)); 8150 } 8151 8152 static void unsetup_unrestricted_guest(void) 8153 { 8154 vmcs_write(GUEST_CR0, vmcs_read(GUEST_CR0) | X86_CR0_PG); 8155 vmcs_write(ENT_CONTROLS, vmcs_read(ENT_CONTROLS) | ENT_GUEST_64); 8156 vmcs_write(GUEST_EFER, vmcs_read(GUEST_EFER) | EFER_LMA); 8157 vmcs_write(GUEST_RIP, (u64) phys_to_virt(vmcs_read(GUEST_RIP))); 8158 vmcs_write(GUEST_RSP, (u64) phys_to_virt(vmcs_read(GUEST_RSP))); 8159 } 8160 8161 /* 8162 * If "unrestricted guest" secondary VM-execution control is set, guests 8163 * can run in unpaged protected mode. 8164 */ 8165 static void vmentry_unrestricted_guest_test(void) 8166 { 8167 if (enable_unrestricted_guest(true)) { 8168 report_skip("Unrestricted guest not supported"); 8169 return; 8170 } 8171 8172 test_set_guest(unrestricted_guest_main); 8173 setup_unrestricted_guest(); 8174 test_guest_state("Unrestricted guest test", false, CPU_URG, "CPU_URG"); 8175 8176 /* 8177 * Let the guest finish execution as a regular guest 8178 */ 8179 unsetup_unrestricted_guest(); 8180 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) & ~CPU_URG); 8181 enter_guest(); 8182 } 8183 8184 static bool valid_vmcs_for_vmentry(void) 8185 { 8186 struct vmcs *current_vmcs = NULL; 8187 8188 if (vmcs_save(¤t_vmcs)) 8189 return false; 8190 8191 return current_vmcs && !current_vmcs->hdr.shadow_vmcs; 8192 } 8193 8194 static void try_vmentry_in_movss_shadow(void) 8195 { 8196 u32 vm_inst_err; 8197 u32 flags; 8198 bool early_failure = false; 8199 u32 expected_flags = X86_EFLAGS_FIXED; 8200 bool valid_vmcs = valid_vmcs_for_vmentry(); 8201 8202 expected_flags |= valid_vmcs ? X86_EFLAGS_ZF : X86_EFLAGS_CF; 8203 8204 /* 8205 * Indirectly set VM_INST_ERR to 12 ("VMREAD/VMWRITE from/to 8206 * unsupported VMCS component"). 8207 */ 8208 vmcs_write(~0u, 0); 8209 8210 __asm__ __volatile__ ("mov %[host_rsp], %%edx;" 8211 "vmwrite %%rsp, %%rdx;" 8212 "mov 0f, %%rax;" 8213 "mov %[host_rip], %%edx;" 8214 "vmwrite %%rax, %%rdx;" 8215 "mov $-1, %%ah;" 8216 "sahf;" 8217 "mov %%ss, %%ax;" 8218 "mov %%ax, %%ss;" 8219 "vmlaunch;" 8220 "mov $1, %[early_failure];" 8221 "0: lahf;" 8222 "movzbl %%ah, %[flags]" 8223 : [early_failure] "+r" (early_failure), 8224 [flags] "=&a" (flags) 8225 : [host_rsp] "i" (HOST_RSP), 8226 [host_rip] "i" (HOST_RIP) 8227 : "rdx", "cc", "memory"); 8228 vm_inst_err = vmcs_read(VMX_INST_ERROR); 8229 8230 report(early_failure, "Early VM-entry failure"); 8231 report(flags == expected_flags, "RFLAGS[8:0] is %x (actual %x)", 8232 expected_flags, flags); 8233 if (valid_vmcs) 8234 report(vm_inst_err == VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, 8235 "VM-instruction error is %d (actual %d)", 8236 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, vm_inst_err); 8237 } 8238 8239 static void vmentry_movss_shadow_test(void) 8240 { 8241 struct vmcs *orig_vmcs; 8242 8243 TEST_ASSERT(!vmcs_save(&orig_vmcs)); 8244 8245 /* 8246 * Set the launched flag on the current VMCS to verify the correct 8247 * error priority, below. 8248 */ 8249 test_set_guest(v2_null_test_guest); 8250 enter_guest(); 8251 8252 /* 8253 * With bit 1 of the guest's RFLAGS clear, VM-entry should 8254 * fail due to invalid guest state (if we make it that far). 8255 */ 8256 vmcs_write(GUEST_RFLAGS, 0); 8257 8258 /* 8259 * "VM entry with events blocked by MOV SS" takes precedence over 8260 * "VMLAUNCH with non-clear VMCS." 8261 */ 8262 report_prefix_push("valid current-VMCS"); 8263 try_vmentry_in_movss_shadow(); 8264 report_prefix_pop(); 8265 8266 /* 8267 * VMfailInvalid takes precedence over "VM entry with events 8268 * blocked by MOV SS." 8269 */ 8270 TEST_ASSERT(!vmcs_clear(orig_vmcs)); 8271 report_prefix_push("no current-VMCS"); 8272 try_vmentry_in_movss_shadow(); 8273 report_prefix_pop(); 8274 8275 TEST_ASSERT(!make_vmcs_current(orig_vmcs)); 8276 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8277 } 8278 8279 static void vmx_ldtr_test_guest(void) 8280 { 8281 u16 ldtr = sldt(); 8282 8283 report(ldtr == NP_SEL, "Expected %x for L2 LDTR selector (got %x)", 8284 NP_SEL, ldtr); 8285 } 8286 8287 /* 8288 * Ensure that the L1 LDTR is set to 0 on VM-exit. 8289 */ 8290 static void vmx_ldtr_test(void) 8291 { 8292 const u8 ldt_ar = 0x82; /* Present LDT */ 8293 u16 sel = FIRST_SPARE_SEL; 8294 8295 /* Set up a non-zero L1 LDTR prior to VM-entry. */ 8296 set_gdt_entry(sel, 0, 0, ldt_ar, 0); 8297 lldt(sel); 8298 8299 test_set_guest(vmx_ldtr_test_guest); 8300 /* 8301 * Set up a different LDTR for L2. The actual GDT contents are 8302 * irrelevant, since we stuff the hidden descriptor state 8303 * straight into the VMCS rather than reading it from the GDT. 8304 */ 8305 vmcs_write(GUEST_SEL_LDTR, NP_SEL); 8306 vmcs_write(GUEST_AR_LDTR, ldt_ar); 8307 enter_guest(); 8308 8309 /* 8310 * VM-exit should clear LDTR (and make it unusable, but we 8311 * won't verify that here). 8312 */ 8313 sel = sldt(); 8314 report(!sel, "Expected 0 for L1 LDTR selector (got %x)", sel); 8315 } 8316 8317 static void vmx_single_vmcall_guest(void) 8318 { 8319 vmcall(); 8320 } 8321 8322 static void vmx_cr_load_test(void) 8323 { 8324 unsigned long cr3, cr4, orig_cr3, orig_cr4; 8325 u32 ctrls[2] = {0}; 8326 pgd_t *pml5; 8327 8328 orig_cr4 = read_cr4(); 8329 orig_cr3 = read_cr3(); 8330 8331 if (!this_cpu_has(X86_FEATURE_PCID)) { 8332 report_skip("PCID not detected"); 8333 return; 8334 } 8335 if (!this_cpu_has(X86_FEATURE_MCE)) { 8336 report_skip("MCE not detected"); 8337 return; 8338 } 8339 8340 TEST_ASSERT(!(orig_cr3 & X86_CR3_PCID_MASK)); 8341 8342 /* Enable PCID for L1. */ 8343 cr4 = orig_cr4 | X86_CR4_PCIDE; 8344 cr3 = orig_cr3 | 0x1; 8345 TEST_ASSERT(!write_cr4_checking(cr4)); 8346 write_cr3(cr3); 8347 8348 test_set_guest(vmx_single_vmcall_guest); 8349 vmcs_write(HOST_CR4, cr4); 8350 vmcs_write(HOST_CR3, cr3); 8351 enter_guest(); 8352 8353 /* 8354 * No exception is expected. 8355 * 8356 * NB. KVM loads the last guest write to CR4 into CR4 read 8357 * shadow. In order to trigger an exit to KVM, we can toggle a 8358 * bit that is owned by KVM. We use CR4.MCE, which shall 8359 * have no side effect because normally no guest MCE (e.g., as the 8360 * result of bad memory) would happen during this test. 8361 */ 8362 TEST_ASSERT(!write_cr4_checking(cr4 ^ X86_CR4_MCE)); 8363 8364 /* Cleanup L1 state. */ 8365 write_cr3(orig_cr3); 8366 TEST_ASSERT(!write_cr4_checking(orig_cr4)); 8367 8368 if (!this_cpu_has(X86_FEATURE_LA57)) 8369 goto done; 8370 8371 /* 8372 * Allocate a full page for PML5 to guarantee alignment, though only 8373 * the first entry needs to be filled (the test's virtual addresses 8374 * most definitely do not have any of bits 56:48 set). 8375 */ 8376 pml5 = alloc_page(); 8377 *pml5 = orig_cr3 | PT_PRESENT_MASK | PT_WRITABLE_MASK; 8378 8379 /* 8380 * Transition to/from 5-level paging in the host via VM-Exit. CR4.LA57 8381 * can't be toggled while long is active via MOV CR4, but there are no 8382 * such restrictions on VM-Exit. 8383 */ 8384 lol_5level: 8385 vmcs_write(HOST_CR4, orig_cr4 | X86_CR4_LA57); 8386 vmcs_write(HOST_CR3, virt_to_phys(pml5)); 8387 enter_guest(); 8388 8389 /* 8390 * VMREAD with a memory operand to verify KVM detects the LA57 change, 8391 * e.g. uses the correct guest root level in gva_to_gpa(). 8392 */ 8393 TEST_ASSERT(vmcs_readm(HOST_CR3) == virt_to_phys(pml5)); 8394 TEST_ASSERT(vmcs_readm(HOST_CR4) == (orig_cr4 | X86_CR4_LA57)); 8395 8396 vmcs_write(HOST_CR4, orig_cr4); 8397 vmcs_write(HOST_CR3, orig_cr3); 8398 enter_guest(); 8399 8400 TEST_ASSERT(vmcs_readm(HOST_CR3) == orig_cr3); 8401 TEST_ASSERT(vmcs_readm(HOST_CR4) == orig_cr4); 8402 8403 /* 8404 * And now do the same LA57 shenanigans with EPT enabled. KVM uses 8405 * two separate MMUs when L1 uses TDP, whereas the above shadow paging 8406 * version shares an MMU between L1 and L2. 8407 * 8408 * If the saved execution controls are non-zero then the EPT version 8409 * has already run. In that case, restore the old controls. If EPT 8410 * setup fails, e.g. EPT isn't supported, fall through and finish up. 8411 */ 8412 if (ctrls[0]) { 8413 vmcs_write(CPU_EXEC_CTRL0, ctrls[0]); 8414 vmcs_write(CPU_EXEC_CTRL1, ctrls[1]); 8415 } else if (!setup_ept(false)) { 8416 ctrls[0] = vmcs_read(CPU_EXEC_CTRL0); 8417 ctrls[1] = vmcs_read(CPU_EXEC_CTRL1); 8418 goto lol_5level; 8419 } 8420 8421 free_page(pml5); 8422 8423 done: 8424 skip_exit_vmcall(); 8425 enter_guest(); 8426 } 8427 8428 static void vmx_cr4_osxsave_test_guest(void) 8429 { 8430 write_cr4(read_cr4() & ~X86_CR4_OSXSAVE); 8431 } 8432 8433 /* 8434 * Ensure that kvm recalculates the L1 guest's CPUID.01H:ECX.OSXSAVE 8435 * after VM-exit from an L2 guest that sets CR4.OSXSAVE to a different 8436 * value than in L1. 8437 */ 8438 static void vmx_cr4_osxsave_test(void) 8439 { 8440 if (!this_cpu_has(X86_FEATURE_XSAVE)) { 8441 report_skip("XSAVE not detected"); 8442 return; 8443 } 8444 8445 if (!(read_cr4() & X86_CR4_OSXSAVE)) { 8446 unsigned long cr4 = read_cr4() | X86_CR4_OSXSAVE; 8447 8448 write_cr4(cr4); 8449 vmcs_write(GUEST_CR4, cr4); 8450 vmcs_write(HOST_CR4, cr4); 8451 } 8452 8453 TEST_ASSERT(cpuid_osxsave()); 8454 8455 test_set_guest(vmx_cr4_osxsave_test_guest); 8456 enter_guest(); 8457 8458 TEST_ASSERT(cpuid_osxsave()); 8459 } 8460 8461 static void vmx_nm_test_guest(void) 8462 { 8463 write_cr0(read_cr0() | X86_CR0_TS); 8464 asm volatile("fnop"); 8465 } 8466 8467 static void check_nm_exit(const char *test) 8468 { 8469 u32 reason = vmcs_read(EXI_REASON); 8470 u32 intr_info = vmcs_read(EXI_INTR_INFO); 8471 const u32 expected = INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8472 NM_VECTOR; 8473 8474 report(reason == VMX_EXC_NMI && intr_info == expected, "%s", test); 8475 } 8476 8477 /* 8478 * This test checks that: 8479 * 8480 * (a) If L2 launches with CR0.TS clear, but later sets CR0.TS, then 8481 * a subsequent #NM VM-exit is reflected to L1. 8482 * 8483 * (b) If L2 launches with CR0.TS clear and CR0.EM set, then a 8484 * subsequent #NM VM-exit is reflected to L1. 8485 */ 8486 static void vmx_nm_test(void) 8487 { 8488 unsigned long cr0 = read_cr0(); 8489 8490 test_set_guest(vmx_nm_test_guest); 8491 8492 /* 8493 * L1 wants to intercept #NM exceptions encountered in L2. 8494 */ 8495 vmcs_write(EXC_BITMAP, 1 << NM_VECTOR); 8496 8497 /* 8498 * Launch L2 with CR0.TS clear, but don't claim host ownership of 8499 * any CR0 bits. L2 will set CR0.TS and then try to execute fnop, 8500 * which will raise #NM. L0 should reflect the #NM VM-exit to L1. 8501 */ 8502 vmcs_write(CR0_MASK, 0); 8503 vmcs_write(GUEST_CR0, cr0 & ~X86_CR0_TS); 8504 enter_guest(); 8505 check_nm_exit("fnop with CR0.TS set in L2 triggers #NM VM-exit to L1"); 8506 8507 /* 8508 * Re-enter L2 at the fnop instruction, with CR0.TS clear but 8509 * CR0.EM set. The fnop will still raise #NM, and L0 should 8510 * reflect the #NM VM-exit to L1. 8511 */ 8512 vmcs_write(GUEST_CR0, (cr0 & ~X86_CR0_TS) | X86_CR0_EM); 8513 enter_guest(); 8514 check_nm_exit("fnop with CR0.EM set in L2 triggers #NM VM-exit to L1"); 8515 8516 /* 8517 * Re-enter L2 at the fnop instruction, with both CR0.TS and 8518 * CR0.EM clear. There will be no #NM, and the L2 guest should 8519 * exit normally. 8520 */ 8521 vmcs_write(GUEST_CR0, cr0 & ~(X86_CR0_TS | X86_CR0_EM)); 8522 enter_guest(); 8523 } 8524 8525 bool vmx_pending_event_ipi_fired; 8526 static void vmx_pending_event_ipi_isr(isr_regs_t *regs) 8527 { 8528 vmx_pending_event_ipi_fired = true; 8529 eoi(); 8530 } 8531 8532 bool vmx_pending_event_guest_run; 8533 static void vmx_pending_event_guest(void) 8534 { 8535 vmcall(); 8536 vmx_pending_event_guest_run = true; 8537 } 8538 8539 static void vmx_pending_event_test_core(bool guest_hlt) 8540 { 8541 int ipi_vector = 0xf1; 8542 8543 vmx_pending_event_ipi_fired = false; 8544 handle_irq(ipi_vector, vmx_pending_event_ipi_isr); 8545 8546 vmx_pending_event_guest_run = false; 8547 test_set_guest(vmx_pending_event_guest); 8548 8549 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 8550 8551 enter_guest(); 8552 skip_exit_vmcall(); 8553 8554 if (guest_hlt) 8555 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8556 8557 irq_disable(); 8558 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 8559 APIC_DM_FIXED | ipi_vector, 8560 0); 8561 8562 enter_guest(); 8563 8564 assert_exit_reason(VMX_EXTINT); 8565 report(!vmx_pending_event_guest_run, 8566 "Guest did not run before host received IPI"); 8567 8568 irq_enable(); 8569 asm volatile ("nop"); 8570 irq_disable(); 8571 report(vmx_pending_event_ipi_fired, 8572 "Got pending interrupt after IRQ enabled"); 8573 8574 if (guest_hlt) 8575 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8576 8577 enter_guest(); 8578 report(vmx_pending_event_guest_run, 8579 "Guest finished running when no interrupt"); 8580 } 8581 8582 static void vmx_pending_event_test(void) 8583 { 8584 vmx_pending_event_test_core(false); 8585 } 8586 8587 static void vmx_pending_event_hlt_test(void) 8588 { 8589 vmx_pending_event_test_core(true); 8590 } 8591 8592 static int vmx_window_test_db_count; 8593 8594 static void vmx_window_test_db_handler(struct ex_regs *regs) 8595 { 8596 vmx_window_test_db_count++; 8597 } 8598 8599 static void vmx_nmi_window_test_guest(void) 8600 { 8601 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8602 8603 asm volatile("vmcall\n\t" 8604 "nop\n\t"); 8605 8606 handle_exception(DB_VECTOR, NULL); 8607 } 8608 8609 static void verify_nmi_window_exit(u64 rip) 8610 { 8611 u32 exit_reason = vmcs_read(EXI_REASON); 8612 8613 report(exit_reason == VMX_NMI_WINDOW, 8614 "Exit reason (%d) is 'NMI window'", exit_reason); 8615 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8616 vmcs_read(GUEST_RIP), rip); 8617 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8618 } 8619 8620 static void vmx_nmi_window_test(void) 8621 { 8622 u64 nop_addr; 8623 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8624 8625 if (!(ctrl_pin_rev.clr & PIN_VIRT_NMI)) { 8626 report_skip("CPU does not support the \"Virtual NMIs\" VM-execution control."); 8627 return; 8628 } 8629 8630 if (!(ctrl_cpu_rev[0].clr & CPU_NMI_WINDOW)) { 8631 report_skip("CPU does not support the \"NMI-window exiting\" VM-execution control."); 8632 return; 8633 } 8634 8635 vmx_window_test_db_count = 0; 8636 8637 report_prefix_push("NMI-window"); 8638 test_set_guest(vmx_nmi_window_test_guest); 8639 vmcs_set_bits(PIN_CONTROLS, PIN_VIRT_NMI); 8640 enter_guest(); 8641 skip_exit_vmcall(); 8642 nop_addr = vmcs_read(GUEST_RIP); 8643 8644 /* 8645 * Ask for "NMI-window exiting," and expect an immediate VM-exit. 8646 * RIP will not advance. 8647 */ 8648 report_prefix_push("active, no blocking"); 8649 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8650 enter_guest(); 8651 verify_nmi_window_exit(nop_addr); 8652 report_prefix_pop(); 8653 8654 /* 8655 * Ask for "NMI-window exiting" in a MOV-SS shadow, and expect 8656 * a VM-exit on the next instruction after the nop. (The nop 8657 * is one byte.) 8658 */ 8659 report_prefix_push("active, blocking by MOV-SS"); 8660 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8661 enter_guest(); 8662 verify_nmi_window_exit(nop_addr + 1); 8663 report_prefix_pop(); 8664 8665 /* 8666 * Ask for "NMI-window exiting" (with event injection), and 8667 * expect a VM-exit after the event is injected. (RIP should 8668 * be at the address specified in the IDT entry for #DB.) 8669 */ 8670 report_prefix_push("active, no blocking, injecting #DB"); 8671 vmcs_write(ENT_INTR_INFO, 8672 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8673 enter_guest(); 8674 verify_nmi_window_exit((u64)db_fault_addr); 8675 report_prefix_pop(); 8676 8677 /* 8678 * Ask for "NMI-window exiting" with NMI blocking, and expect 8679 * a VM-exit after the next IRET (i.e. after the #DB handler 8680 * returns). So, RIP should be back at one byte past the nop. 8681 */ 8682 report_prefix_push("active, blocking by NMI"); 8683 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_NMI); 8684 enter_guest(); 8685 verify_nmi_window_exit(nop_addr + 1); 8686 report(vmx_window_test_db_count == 1, 8687 "#DB handler executed once (actual %d times)", 8688 vmx_window_test_db_count); 8689 report_prefix_pop(); 8690 8691 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8692 report_skip("CPU does not support activity state HLT."); 8693 } else { 8694 /* 8695 * Ask for "NMI-window exiting" when entering activity 8696 * state HLT, and expect an immediate VM-exit. RIP is 8697 * still one byte past the nop. 8698 */ 8699 report_prefix_push("halted, no blocking"); 8700 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8701 enter_guest(); 8702 verify_nmi_window_exit(nop_addr + 1); 8703 report_prefix_pop(); 8704 8705 /* 8706 * Ask for "NMI-window exiting" when entering activity 8707 * state HLT (with event injection), and expect a 8708 * VM-exit after the event is injected. (RIP should be 8709 * at the address specified in the IDT entry for #DB.) 8710 */ 8711 report_prefix_push("halted, no blocking, injecting #DB"); 8712 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8713 vmcs_write(ENT_INTR_INFO, 8714 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8715 DB_VECTOR); 8716 enter_guest(); 8717 verify_nmi_window_exit((u64)db_fault_addr); 8718 report_prefix_pop(); 8719 } 8720 8721 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_NMI_WINDOW); 8722 enter_guest(); 8723 report_prefix_pop(); 8724 } 8725 8726 static void vmx_intr_window_test_guest(void) 8727 { 8728 handle_exception(DB_VECTOR, vmx_window_test_db_handler); 8729 8730 /* 8731 * The two consecutive STIs are to ensure that only the first 8732 * one has a shadow. Note that NOP and STI are one byte 8733 * instructions. 8734 */ 8735 asm volatile("vmcall\n\t" 8736 "nop\n\t" 8737 "sti\n\t" 8738 "sti\n\t"); 8739 8740 handle_exception(DB_VECTOR, NULL); 8741 } 8742 8743 static void verify_intr_window_exit(u64 rip) 8744 { 8745 u32 exit_reason = vmcs_read(EXI_REASON); 8746 8747 report(exit_reason == VMX_INTR_WINDOW, 8748 "Exit reason (%d) is 'interrupt window'", exit_reason); 8749 report(vmcs_read(GUEST_RIP) == rip, "RIP (%#lx) is %#lx", 8750 vmcs_read(GUEST_RIP), rip); 8751 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 8752 } 8753 8754 static void vmx_intr_window_test(void) 8755 { 8756 u64 vmcall_addr; 8757 u64 nop_addr; 8758 unsigned int orig_db_gate_type; 8759 void *db_fault_addr = get_idt_addr(&boot_idt[DB_VECTOR]); 8760 8761 if (!(ctrl_cpu_rev[0].clr & CPU_INTR_WINDOW)) { 8762 report_skip("CPU does not support the \"interrupt-window exiting\" VM-execution control."); 8763 return; 8764 } 8765 8766 /* 8767 * Change the IDT entry for #DB from interrupt gate to trap gate, 8768 * so that it won't clear RFLAGS.IF. We don't want interrupts to 8769 * be disabled after vectoring a #DB. 8770 */ 8771 orig_db_gate_type = boot_idt[DB_VECTOR].type; 8772 boot_idt[DB_VECTOR].type = 15; 8773 8774 report_prefix_push("interrupt-window"); 8775 test_set_guest(vmx_intr_window_test_guest); 8776 enter_guest(); 8777 assert_exit_reason(VMX_VMCALL); 8778 vmcall_addr = vmcs_read(GUEST_RIP); 8779 8780 /* 8781 * Ask for "interrupt-window exiting" with RFLAGS.IF set and 8782 * no blocking; expect an immediate VM-exit. Note that we have 8783 * not advanced past the vmcall instruction yet, so RIP should 8784 * point to the vmcall instruction. 8785 */ 8786 report_prefix_push("active, no blocking, RFLAGS.IF=1"); 8787 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8788 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_IF); 8789 enter_guest(); 8790 verify_intr_window_exit(vmcall_addr); 8791 report_prefix_pop(); 8792 8793 /* 8794 * Ask for "interrupt-window exiting" (with event injection) 8795 * with RFLAGS.IF set and no blocking; expect a VM-exit after 8796 * the event is injected. That is, RIP should should be at the 8797 * address specified in the IDT entry for #DB. 8798 */ 8799 report_prefix_push("active, no blocking, RFLAGS.IF=1, injecting #DB"); 8800 vmcs_write(ENT_INTR_INFO, 8801 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8802 vmcall_addr = vmcs_read(GUEST_RIP); 8803 enter_guest(); 8804 verify_intr_window_exit((u64)db_fault_addr); 8805 report_prefix_pop(); 8806 8807 /* 8808 * Let the L2 guest run through the IRET, back to the VMCALL. 8809 * We have to clear the "interrupt-window exiting" 8810 * VM-execution control, or it would just keep causing 8811 * VM-exits. Then, advance past the VMCALL and set the 8812 * "interrupt-window exiting" VM-execution control again. 8813 */ 8814 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8815 enter_guest(); 8816 skip_exit_vmcall(); 8817 nop_addr = vmcs_read(GUEST_RIP); 8818 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8819 8820 /* 8821 * Ask for "interrupt-window exiting" in a MOV-SS shadow with 8822 * RFLAGS.IF set, and expect a VM-exit on the next 8823 * instruction. (NOP is one byte.) 8824 */ 8825 report_prefix_push("active, blocking by MOV-SS, RFLAGS.IF=1"); 8826 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 8827 enter_guest(); 8828 verify_intr_window_exit(nop_addr + 1); 8829 report_prefix_pop(); 8830 8831 /* 8832 * Back up to the NOP and ask for "interrupt-window exiting" 8833 * in an STI shadow with RFLAGS.IF set, and expect a VM-exit 8834 * on the next instruction. (NOP is one byte.) 8835 */ 8836 report_prefix_push("active, blocking by STI, RFLAGS.IF=1"); 8837 vmcs_write(GUEST_RIP, nop_addr); 8838 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_STI); 8839 enter_guest(); 8840 verify_intr_window_exit(nop_addr + 1); 8841 report_prefix_pop(); 8842 8843 /* 8844 * Ask for "interrupt-window exiting" with RFLAGS.IF clear, 8845 * and expect a VM-exit on the instruction following the STI 8846 * shadow. Only the first STI (which is one byte past the NOP) 8847 * should have a shadow. The second STI (which is two bytes 8848 * past the NOP) has no shadow. Therefore, the interrupt 8849 * window opens at three bytes past the NOP. 8850 */ 8851 report_prefix_push("active, RFLAGS.IF = 0"); 8852 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 8853 enter_guest(); 8854 verify_intr_window_exit(nop_addr + 3); 8855 report_prefix_pop(); 8856 8857 if (!(rdmsr(MSR_IA32_VMX_MISC) & (1 << 6))) { 8858 report_skip("CPU does not support activity state HLT."); 8859 } else { 8860 /* 8861 * Ask for "interrupt-window exiting" when entering 8862 * activity state HLT, and expect an immediate 8863 * VM-exit. RIP is still three bytes past the nop. 8864 */ 8865 report_prefix_push("halted, no blocking"); 8866 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8867 enter_guest(); 8868 verify_intr_window_exit(nop_addr + 3); 8869 report_prefix_pop(); 8870 8871 /* 8872 * Ask for "interrupt-window exiting" when entering 8873 * activity state HLT (with event injection), and 8874 * expect a VM-exit after the event is injected. That 8875 * is, RIP should should be at the address specified 8876 * in the IDT entry for #DB. 8877 */ 8878 report_prefix_push("halted, no blocking, injecting #DB"); 8879 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 8880 vmcs_write(ENT_INTR_INFO, 8881 INTR_INFO_VALID_MASK | INTR_TYPE_HARD_EXCEPTION | 8882 DB_VECTOR); 8883 enter_guest(); 8884 verify_intr_window_exit((u64)db_fault_addr); 8885 report_prefix_pop(); 8886 } 8887 8888 boot_idt[DB_VECTOR].type = orig_db_gate_type; 8889 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_INTR_WINDOW); 8890 enter_guest(); 8891 report_prefix_pop(); 8892 } 8893 8894 #define GUEST_TSC_OFFSET (1u << 30) 8895 8896 static u64 guest_tsc; 8897 8898 static void vmx_store_tsc_test_guest(void) 8899 { 8900 guest_tsc = rdtsc(); 8901 } 8902 8903 /* 8904 * This test ensures that when IA32_TSC is in the VM-exit MSR-store 8905 * list, the value saved is not subject to the TSC offset that is 8906 * applied to RDTSC/RDTSCP/RDMSR(IA32_TSC) in guest execution. 8907 */ 8908 static void vmx_store_tsc_test(void) 8909 { 8910 struct vmx_msr_entry msr_entry = { .index = MSR_IA32_TSC }; 8911 u64 low, high; 8912 8913 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) { 8914 report_skip("'Use TSC offsetting' not supported"); 8915 return; 8916 } 8917 8918 test_set_guest(vmx_store_tsc_test_guest); 8919 8920 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 8921 vmcs_write(EXI_MSR_ST_CNT, 1); 8922 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(&msr_entry)); 8923 vmcs_write(TSC_OFFSET, GUEST_TSC_OFFSET); 8924 8925 low = rdtsc(); 8926 enter_guest(); 8927 high = rdtsc(); 8928 8929 report(low + GUEST_TSC_OFFSET <= guest_tsc && 8930 guest_tsc <= high + GUEST_TSC_OFFSET, 8931 "RDTSC value in the guest (%lu) is in range [%lu, %lu]", 8932 guest_tsc, low + GUEST_TSC_OFFSET, high + GUEST_TSC_OFFSET); 8933 report(low <= msr_entry.value && msr_entry.value <= high, 8934 "IA32_TSC value saved in the VM-exit MSR-store list (%lu) is in range [%lu, %lu]", 8935 msr_entry.value, low, high); 8936 } 8937 8938 static void vmx_preemption_timer_zero_test_db_handler(struct ex_regs *regs) 8939 { 8940 } 8941 8942 static void vmx_preemption_timer_zero_test_guest(void) 8943 { 8944 while (vmx_get_test_stage() < 3) 8945 vmcall(); 8946 } 8947 8948 static void vmx_preemption_timer_zero_activate_preemption_timer(void) 8949 { 8950 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 8951 vmcs_write(PREEMPT_TIMER_VALUE, 0); 8952 } 8953 8954 static void vmx_preemption_timer_zero_advance_past_vmcall(void) 8955 { 8956 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 8957 enter_guest(); 8958 skip_exit_vmcall(); 8959 } 8960 8961 static void vmx_preemption_timer_zero_inject_db(bool intercept_db) 8962 { 8963 vmx_preemption_timer_zero_activate_preemption_timer(); 8964 vmcs_write(ENT_INTR_INFO, INTR_INFO_VALID_MASK | 8965 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR); 8966 vmcs_write(EXC_BITMAP, intercept_db ? 1 << DB_VECTOR : 0); 8967 enter_guest(); 8968 } 8969 8970 static void vmx_preemption_timer_zero_set_pending_dbg(u32 exception_bitmap) 8971 { 8972 vmx_preemption_timer_zero_activate_preemption_timer(); 8973 vmcs_write(GUEST_PENDING_DEBUG, BIT(12) | DR_TRAP1); 8974 vmcs_write(EXC_BITMAP, exception_bitmap); 8975 enter_guest(); 8976 } 8977 8978 static void vmx_preemption_timer_zero_expect_preempt_at_rip(u64 expected_rip) 8979 { 8980 u32 reason = (u32)vmcs_read(EXI_REASON); 8981 u64 guest_rip = vmcs_read(GUEST_RIP); 8982 8983 report(reason == VMX_PREEMPT && guest_rip == expected_rip, 8984 "Exit reason is 0x%x (expected 0x%x) and guest RIP is %lx (0x%lx expected).", 8985 reason, VMX_PREEMPT, guest_rip, expected_rip); 8986 } 8987 8988 /* 8989 * This test ensures that when the VMX preemption timer is zero at 8990 * VM-entry, a VM-exit occurs after any event injection and after any 8991 * pending debug exceptions are raised, but before execution of any 8992 * guest instructions. 8993 */ 8994 static void vmx_preemption_timer_zero_test(void) 8995 { 8996 u64 db_fault_address = (u64)get_idt_addr(&boot_idt[DB_VECTOR]); 8997 handler old_db; 8998 u32 reason; 8999 9000 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9001 report_skip("'Activate VMX-preemption timer' not supported"); 9002 return; 9003 } 9004 9005 /* 9006 * Install a custom #DB handler that doesn't abort. 9007 */ 9008 old_db = handle_exception(DB_VECTOR, 9009 vmx_preemption_timer_zero_test_db_handler); 9010 9011 test_set_guest(vmx_preemption_timer_zero_test_guest); 9012 9013 /* 9014 * VMX-preemption timer should fire after event injection. 9015 */ 9016 vmx_set_test_stage(0); 9017 vmx_preemption_timer_zero_inject_db(0); 9018 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9019 vmx_preemption_timer_zero_advance_past_vmcall(); 9020 9021 /* 9022 * VMX-preemption timer should fire after event injection. 9023 * Exception bitmap is irrelevant, since you can't intercept 9024 * an event that you injected. 9025 */ 9026 vmx_set_test_stage(1); 9027 vmx_preemption_timer_zero_inject_db(true); 9028 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9029 vmx_preemption_timer_zero_advance_past_vmcall(); 9030 9031 /* 9032 * VMX-preemption timer should fire after pending debug exceptions 9033 * have delivered a #DB trap. 9034 */ 9035 vmx_set_test_stage(2); 9036 vmx_preemption_timer_zero_set_pending_dbg(0); 9037 vmx_preemption_timer_zero_expect_preempt_at_rip(db_fault_address); 9038 vmx_preemption_timer_zero_advance_past_vmcall(); 9039 9040 /* 9041 * VMX-preemption timer would fire after pending debug exceptions 9042 * have delivered a #DB trap, but in this case, the #DB trap is 9043 * intercepted. 9044 */ 9045 vmx_set_test_stage(3); 9046 vmx_preemption_timer_zero_set_pending_dbg(1 << DB_VECTOR); 9047 reason = (u32)vmcs_read(EXI_REASON); 9048 report(reason == VMX_EXC_NMI, "Exit reason is 0x%x (expected 0x%x)", 9049 reason, VMX_EXC_NMI); 9050 9051 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9052 enter_guest(); 9053 9054 handle_exception(DB_VECTOR, old_db); 9055 } 9056 9057 static u64 vmx_preemption_timer_tf_test_prev_rip; 9058 9059 static void vmx_preemption_timer_tf_test_db_handler(struct ex_regs *regs) 9060 { 9061 extern char vmx_preemption_timer_tf_test_endloop; 9062 9063 if (vmx_get_test_stage() == 2) { 9064 /* 9065 * Stage 2 means that we're done, one way or another. 9066 * Arrange for the iret to drop us out of the wbinvd 9067 * loop and stop single-stepping. 9068 */ 9069 regs->rip = (u64)&vmx_preemption_timer_tf_test_endloop; 9070 regs->rflags &= ~X86_EFLAGS_TF; 9071 } else if (regs->rip == vmx_preemption_timer_tf_test_prev_rip) { 9072 /* 9073 * The RIP should alternate between the wbinvd and the 9074 * jmp instruction in the code below. If we ever see 9075 * the same instruction twice in a row, that means a 9076 * single-step trap has been dropped. Let the 9077 * hypervisor know about the failure by executing a 9078 * VMCALL. 9079 */ 9080 vmcall(); 9081 } 9082 vmx_preemption_timer_tf_test_prev_rip = regs->rip; 9083 } 9084 9085 static void vmx_preemption_timer_tf_test_guest(void) 9086 { 9087 /* 9088 * The hypervisor doesn't intercept WBINVD, so the loop below 9089 * shouldn't be a problem--it's just two instructions 9090 * executing in VMX non-root mode. However, when the 9091 * hypervisor is running in a virtual environment, the parent 9092 * hypervisor might intercept WBINVD and emulate it. If the 9093 * parent hypervisor is broken, the single-step trap after the 9094 * WBINVD might be lost. 9095 */ 9096 asm volatile("vmcall\n\t" 9097 "0: wbinvd\n\t" 9098 "1: jmp 0b\n\t" 9099 "vmx_preemption_timer_tf_test_endloop:"); 9100 } 9101 9102 /* 9103 * Ensure that the delivery of a "VMX-preemption timer expired" 9104 * VM-exit doesn't disrupt single-stepping in the guest. Note that 9105 * passing this test doesn't ensure correctness, because the test will 9106 * only fail if the VMX-preemtion timer fires at the right time (or 9107 * the wrong time, as it were). 9108 */ 9109 static void vmx_preemption_timer_tf_test(void) 9110 { 9111 handler old_db; 9112 u32 reason; 9113 int i; 9114 9115 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9116 report_skip("'Activate VMX-preemption timer' not supported"); 9117 return; 9118 } 9119 9120 old_db = handle_exception(DB_VECTOR, 9121 vmx_preemption_timer_tf_test_db_handler); 9122 9123 test_set_guest(vmx_preemption_timer_tf_test_guest); 9124 9125 enter_guest(); 9126 skip_exit_vmcall(); 9127 9128 vmx_set_test_stage(1); 9129 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9130 vmcs_write(PREEMPT_TIMER_VALUE, 50000); 9131 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9132 9133 /* 9134 * The only exit we should see is "VMX-preemption timer 9135 * expired." If we get a VMCALL exit, that means the #DB 9136 * handler has detected a missing single-step trap. It doesn't 9137 * matter where the guest RIP is when the VMX-preemption timer 9138 * expires (whether it's in the WBINVD loop or in the #DB 9139 * handler)--a single-step trap should never be discarded. 9140 */ 9141 for (i = 0; i < 10000; i++) { 9142 enter_guest(); 9143 reason = (u32)vmcs_read(EXI_REASON); 9144 if (reason == VMX_PREEMPT) 9145 continue; 9146 TEST_ASSERT(reason == VMX_VMCALL); 9147 skip_exit_insn(); 9148 break; 9149 } 9150 9151 report(reason == VMX_PREEMPT, "No single-step traps skipped"); 9152 9153 vmx_set_test_stage(2); 9154 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9155 enter_guest(); 9156 9157 handle_exception(DB_VECTOR, old_db); 9158 } 9159 9160 #define VMX_PREEMPTION_TIMER_EXPIRY_CYCLES 1000000 9161 9162 static u64 vmx_preemption_timer_expiry_start; 9163 static u64 vmx_preemption_timer_expiry_finish; 9164 9165 static void vmx_preemption_timer_expiry_test_guest(void) 9166 { 9167 vmcall(); 9168 vmx_preemption_timer_expiry_start = fenced_rdtsc(); 9169 9170 while (vmx_get_test_stage() == 0) 9171 vmx_preemption_timer_expiry_finish = fenced_rdtsc(); 9172 } 9173 9174 /* 9175 * Test that the VMX-preemption timer is not excessively delayed. 9176 * 9177 * Per the SDM, volume 3, VM-entry starts the VMX-preemption timer 9178 * with the unsigned value in the VMX-preemption timer-value field, 9179 * and the VMX-preemption timer counts down by 1 every time bit X in 9180 * the TSC changes due to a TSC increment (where X is 9181 * IA32_VMX_MISC[4:0]). If the timer counts down to zero in any state 9182 * other than the wait-for-SIPI state, the logical processor 9183 * transitions to the C0 C-state and causes a VM-exit. 9184 * 9185 * The guest code above reads the starting TSC after VM-entry. At this 9186 * point, the VMX-preemption timer has already been activated. Next, 9187 * the guest code reads the current TSC in a loop, storing the value 9188 * read to memory. 9189 * 9190 * If the RDTSC in the loop reads a value past the VMX-preemption 9191 * timer deadline, then the VMX-preemption timer VM-exit must be 9192 * delivered before the next instruction retires. Even if a higher 9193 * priority SMI is delivered first, the VMX-preemption timer VM-exit 9194 * must be delivered before the next instruction retires. Hence, a TSC 9195 * value past the VMX-preemption timer deadline might be read, but it 9196 * cannot be stored. If a TSC value past the deadline *is* stored, 9197 * then the architectural specification has been violated. 9198 */ 9199 static void vmx_preemption_timer_expiry_test(void) 9200 { 9201 u32 preemption_timer_value; 9202 union vmx_misc misc; 9203 u64 tsc_deadline; 9204 u32 reason; 9205 9206 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 9207 report_skip("'Activate VMX-preemption timer' not supported"); 9208 return; 9209 } 9210 9211 test_set_guest(vmx_preemption_timer_expiry_test_guest); 9212 9213 enter_guest(); 9214 skip_exit_vmcall(); 9215 9216 misc.val = rdmsr(MSR_IA32_VMX_MISC); 9217 preemption_timer_value = 9218 VMX_PREEMPTION_TIMER_EXPIRY_CYCLES >> misc.pt_bit; 9219 9220 vmcs_set_bits(PIN_CONTROLS, PIN_PREEMPT); 9221 vmcs_write(PREEMPT_TIMER_VALUE, preemption_timer_value); 9222 vmx_set_test_stage(0); 9223 9224 enter_guest(); 9225 reason = (u32)vmcs_read(EXI_REASON); 9226 TEST_ASSERT(reason == VMX_PREEMPT); 9227 9228 vmcs_clear_bits(PIN_CONTROLS, PIN_PREEMPT); 9229 vmx_set_test_stage(1); 9230 enter_guest(); 9231 9232 tsc_deadline = ((vmx_preemption_timer_expiry_start >> misc.pt_bit) << 9233 misc.pt_bit) + (preemption_timer_value << misc.pt_bit); 9234 9235 report(vmx_preemption_timer_expiry_finish < tsc_deadline, 9236 "Last stored guest TSC (%lu) < TSC deadline (%lu)", 9237 vmx_preemption_timer_expiry_finish, tsc_deadline); 9238 } 9239 9240 static void vmx_db_test_guest(void) 9241 { 9242 /* 9243 * For a hardware generated single-step #DB. 9244 */ 9245 asm volatile("vmcall;" 9246 "nop;" 9247 ".Lpost_nop:"); 9248 /* 9249 * ...in a MOVSS shadow, with pending debug exceptions. 9250 */ 9251 asm volatile("vmcall;" 9252 "nop;" 9253 ".Lpost_movss_nop:"); 9254 /* 9255 * For an L0 synthesized single-step #DB. (L0 intercepts WBINVD and 9256 * emulates it in software.) 9257 */ 9258 asm volatile("vmcall;" 9259 "wbinvd;" 9260 ".Lpost_wbinvd:"); 9261 /* 9262 * ...in a MOVSS shadow, with pending debug exceptions. 9263 */ 9264 asm volatile("vmcall;" 9265 "wbinvd;" 9266 ".Lpost_movss_wbinvd:"); 9267 /* 9268 * For a hardware generated single-step #DB in a transactional region. 9269 */ 9270 asm volatile("vmcall;" 9271 ".Lxbegin: xbegin .Lskip_rtm;" 9272 "xend;" 9273 ".Lskip_rtm:"); 9274 } 9275 9276 /* 9277 * Clear the pending debug exceptions and RFLAGS.TF and re-enter 9278 * L2. No #DB is delivered and L2 continues to the next point of 9279 * interest. 9280 */ 9281 static void dismiss_db(void) 9282 { 9283 vmcs_write(GUEST_PENDING_DEBUG, 0); 9284 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED); 9285 enter_guest(); 9286 } 9287 9288 /* 9289 * Check a variety of VMCS fields relevant to an intercepted #DB exception. 9290 * Then throw away the #DB exception and resume L2. 9291 */ 9292 static void check_db_exit(bool xfail_qual, bool xfail_dr6, bool xfail_pdbg, 9293 void *expected_rip, u64 expected_exit_qual, 9294 u64 expected_dr6) 9295 { 9296 u32 reason = vmcs_read(EXI_REASON); 9297 u32 intr_info = vmcs_read(EXI_INTR_INFO); 9298 u64 exit_qual = vmcs_read(EXI_QUALIFICATION); 9299 u64 guest_rip = vmcs_read(GUEST_RIP); 9300 u64 guest_pending_dbg = vmcs_read(GUEST_PENDING_DEBUG); 9301 u64 dr6 = read_dr6(); 9302 const u32 expected_intr_info = INTR_INFO_VALID_MASK | 9303 INTR_TYPE_HARD_EXCEPTION | DB_VECTOR; 9304 9305 report(reason == VMX_EXC_NMI && intr_info == expected_intr_info, 9306 "Expected #DB VM-exit"); 9307 report((u64)expected_rip == guest_rip, "Expected RIP %p (actual %lx)", 9308 expected_rip, guest_rip); 9309 report_xfail(xfail_pdbg, 0 == guest_pending_dbg, 9310 "Expected pending debug exceptions 0 (actual %lx)", 9311 guest_pending_dbg); 9312 report_xfail(xfail_qual, expected_exit_qual == exit_qual, 9313 "Expected exit qualification %lx (actual %lx)", 9314 expected_exit_qual, exit_qual); 9315 report_xfail(xfail_dr6, expected_dr6 == dr6, 9316 "Expected DR6 %lx (actual %lx)", expected_dr6, dr6); 9317 dismiss_db(); 9318 } 9319 9320 /* 9321 * Assuming the guest has just exited on a VMCALL instruction, skip 9322 * over the vmcall, and set the guest's RFLAGS.TF in the VMCS. If 9323 * pending debug exceptions are non-zero, set the VMCS up as if the 9324 * previous instruction was a MOVSS that generated the indicated 9325 * pending debug exceptions. Then enter L2. 9326 */ 9327 static void single_step_guest(const char *test_name, u64 starting_dr6, 9328 u64 pending_debug_exceptions) 9329 { 9330 printf("\n%s\n", test_name); 9331 skip_exit_vmcall(); 9332 write_dr6(starting_dr6); 9333 vmcs_write(GUEST_RFLAGS, X86_EFLAGS_FIXED | X86_EFLAGS_TF); 9334 if (pending_debug_exceptions) { 9335 vmcs_write(GUEST_PENDING_DEBUG, pending_debug_exceptions); 9336 vmcs_write(GUEST_INTR_STATE, GUEST_INTR_STATE_MOVSS); 9337 } 9338 enter_guest(); 9339 } 9340 9341 /* 9342 * When L1 intercepts #DB, verify that a single-step trap clears 9343 * pending debug exceptions, populates the exit qualification field 9344 * properly, and that DR6 is not prematurely clobbered. In a 9345 * (simulated) MOVSS shadow, make sure that the pending debug 9346 * exception bits are properly accumulated into the exit qualification 9347 * field. 9348 */ 9349 static void vmx_db_test(void) 9350 { 9351 /* 9352 * We are going to set a few arbitrary bits in DR6 to verify that 9353 * (a) DR6 is not modified by an intercepted #DB, and 9354 * (b) stale bits in DR6 (DR6.BD, in particular) don't leak into 9355 * the exit qualification field for a subsequent #DB exception. 9356 */ 9357 const u64 starting_dr6 = DR6_RESERVED | BIT(13) | DR_TRAP3 | DR_TRAP1; 9358 extern char post_nop asm(".Lpost_nop"); 9359 extern char post_movss_nop asm(".Lpost_movss_nop"); 9360 extern char post_wbinvd asm(".Lpost_wbinvd"); 9361 extern char post_movss_wbinvd asm(".Lpost_movss_wbinvd"); 9362 extern char xbegin asm(".Lxbegin"); 9363 extern char skip_rtm asm(".Lskip_rtm"); 9364 9365 /* 9366 * L1 wants to intercept #DB exceptions encountered in L2. 9367 */ 9368 vmcs_write(EXC_BITMAP, BIT(DB_VECTOR)); 9369 9370 /* 9371 * Start L2 and run it up to the first point of interest. 9372 */ 9373 test_set_guest(vmx_db_test_guest); 9374 enter_guest(); 9375 9376 /* 9377 * Hardware-delivered #DB trap for single-step sets the 9378 * standard that L0 has to follow for emulated instructions. 9379 */ 9380 single_step_guest("Hardware delivered single-step", starting_dr6, 0); 9381 check_db_exit(false, false, false, &post_nop, DR_STEP, starting_dr6); 9382 9383 /* 9384 * Hardware-delivered #DB trap for single-step in MOVSS shadow 9385 * also sets the standard that L0 has to follow for emulated 9386 * instructions. Here, we establish the VMCS pending debug 9387 * exceptions to indicate that the simulated MOVSS triggered a 9388 * data breakpoint as well as the single-step trap. 9389 */ 9390 single_step_guest("Hardware delivered single-step in MOVSS shadow", 9391 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0 ); 9392 check_db_exit(false, false, false, &post_movss_nop, DR_STEP | DR_TRAP0, 9393 starting_dr6); 9394 9395 /* 9396 * L0 synthesized #DB trap for single-step is buggy, because 9397 * kvm (a) clobbers DR6 too early, and (b) tries its best to 9398 * reconstitute the exit qualification from the prematurely 9399 * modified DR6, but fails miserably. 9400 */ 9401 single_step_guest("Software synthesized single-step", starting_dr6, 0); 9402 check_db_exit(false, false, false, &post_wbinvd, DR_STEP, starting_dr6); 9403 9404 /* 9405 * L0 synthesized #DB trap for single-step in MOVSS shadow is 9406 * even worse, because L0 also leaves the pending debug 9407 * exceptions in the VMCS instead of accumulating them into 9408 * the exit qualification field for the #DB exception. 9409 */ 9410 single_step_guest("Software synthesized single-step in MOVSS shadow", 9411 starting_dr6, BIT(12) | DR_STEP | DR_TRAP0); 9412 check_db_exit(true, false, true, &post_movss_wbinvd, DR_STEP | DR_TRAP0, 9413 starting_dr6); 9414 9415 /* 9416 * Optional RTM test for hardware that supports RTM, to 9417 * demonstrate that the current volume 3 of the SDM 9418 * (325384-067US), table 27-1 is incorrect. Bit 16 of the exit 9419 * qualification for debug exceptions is not reserved. It is 9420 * set to 1 if a debug exception (#DB) or a breakpoint 9421 * exception (#BP) occurs inside an RTM region while advanced 9422 * debugging of RTM transactional regions is enabled. 9423 */ 9424 if (this_cpu_has(X86_FEATURE_RTM)) { 9425 vmcs_write(ENT_CONTROLS, 9426 vmcs_read(ENT_CONTROLS) | ENT_LOAD_DBGCTLS); 9427 /* 9428 * Set DR7.RTM[bit 11] and IA32_DEBUGCTL.RTM[bit 15] 9429 * in the guest to enable advanced debugging of RTM 9430 * transactional regions. 9431 */ 9432 vmcs_write(GUEST_DR7, BIT(11)); 9433 vmcs_write(GUEST_DEBUGCTL, BIT(15)); 9434 single_step_guest("Hardware delivered single-step in " 9435 "transactional region", starting_dr6, 0); 9436 check_db_exit(false, false, false, &xbegin, BIT(16), 9437 starting_dr6); 9438 } else { 9439 vmcs_write(GUEST_RIP, (u64)&skip_rtm); 9440 enter_guest(); 9441 } 9442 } 9443 9444 static void enable_vid(void) 9445 { 9446 void *virtual_apic_page; 9447 9448 assert(cpu_has_apicv()); 9449 9450 disable_intercept_for_x2apic_msrs(); 9451 9452 virtual_apic_page = alloc_page(); 9453 vmcs_write(APIC_VIRT_ADDR, (u64)virtual_apic_page); 9454 9455 vmcs_set_bits(PIN_CONTROLS, PIN_EXTINT); 9456 9457 vmcs_write(EOI_EXIT_BITMAP0, 0x0); 9458 vmcs_write(EOI_EXIT_BITMAP1, 0x0); 9459 vmcs_write(EOI_EXIT_BITMAP2, 0x0); 9460 vmcs_write(EOI_EXIT_BITMAP3, 0x0); 9461 9462 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY | CPU_TPR_SHADOW); 9463 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_VINTD | CPU_VIRT_X2APIC); 9464 } 9465 9466 static void trigger_ioapic_scan_thread(void *data) 9467 { 9468 /* Wait until other CPU entered L2 */ 9469 while (vmx_get_test_stage() != 1) 9470 ; 9471 9472 /* Trigger ioapic scan */ 9473 ioapic_set_redir(0xf, 0x79, TRIGGER_LEVEL); 9474 vmx_set_test_stage(2); 9475 } 9476 9477 static void irq_79_handler_guest(isr_regs_t *regs) 9478 { 9479 eoi(); 9480 9481 /* L1 expects vmexit on VMX_VMCALL and not VMX_EOI_INDUCED */ 9482 vmcall(); 9483 } 9484 9485 /* 9486 * Constant for num of busy-loop iterations after which 9487 * a timer interrupt should have happened in host 9488 */ 9489 #define TIMER_INTERRUPT_DELAY 100000000 9490 9491 static void vmx_eoi_bitmap_ioapic_scan_test_guest(void) 9492 { 9493 handle_irq(0x79, irq_79_handler_guest); 9494 irq_enable(); 9495 9496 /* Signal to L1 CPU to trigger ioapic scan */ 9497 vmx_set_test_stage(1); 9498 /* Wait until L1 CPU to trigger ioapic scan */ 9499 while (vmx_get_test_stage() != 2) 9500 ; 9501 9502 /* 9503 * Wait for L0 timer interrupt to be raised while we run in L2 9504 * such that L0 will process the IOAPIC scan request before 9505 * resuming L2 9506 */ 9507 delay(TIMER_INTERRUPT_DELAY); 9508 9509 asm volatile ("int $0x79"); 9510 } 9511 9512 static void vmx_eoi_bitmap_ioapic_scan_test(void) 9513 { 9514 if (!cpu_has_apicv() || (cpu_count() < 2)) { 9515 report_skip(__func__); 9516 return; 9517 } 9518 9519 enable_vid(); 9520 9521 on_cpu_async(1, trigger_ioapic_scan_thread, NULL); 9522 test_set_guest(vmx_eoi_bitmap_ioapic_scan_test_guest); 9523 9524 /* 9525 * Launch L2. 9526 * We expect the exit reason to be VMX_VMCALL (and not EOI INDUCED). 9527 * In case the reason isn't VMX_VMCALL, the asserion inside 9528 * skip_exit_vmcall() will fail. 9529 */ 9530 enter_guest(); 9531 skip_exit_vmcall(); 9532 9533 /* Let L2 finish */ 9534 enter_guest(); 9535 report_pass(__func__); 9536 } 9537 9538 #define HLT_WITH_RVI_VECTOR (0xf1) 9539 9540 bool vmx_hlt_with_rvi_guest_isr_fired; 9541 static void vmx_hlt_with_rvi_guest_isr(isr_regs_t *regs) 9542 { 9543 vmx_hlt_with_rvi_guest_isr_fired = true; 9544 eoi(); 9545 } 9546 9547 static void vmx_hlt_with_rvi_guest(void) 9548 { 9549 handle_irq(HLT_WITH_RVI_VECTOR, vmx_hlt_with_rvi_guest_isr); 9550 9551 irq_enable(); 9552 asm volatile ("nop"); 9553 9554 vmcall(); 9555 } 9556 9557 static void vmx_hlt_with_rvi_test(void) 9558 { 9559 if (!cpu_has_apicv()) { 9560 report_skip(__func__); 9561 return; 9562 } 9563 9564 enable_vid(); 9565 9566 vmx_hlt_with_rvi_guest_isr_fired = false; 9567 test_set_guest(vmx_hlt_with_rvi_guest); 9568 9569 enter_guest(); 9570 skip_exit_vmcall(); 9571 9572 vmcs_write(GUEST_ACTV_STATE, ACTV_HLT); 9573 vmcs_write(GUEST_INT_STATUS, HLT_WITH_RVI_VECTOR); 9574 enter_guest(); 9575 9576 report(vmx_hlt_with_rvi_guest_isr_fired, "Interrupt raised in guest"); 9577 } 9578 9579 static void set_irq_line_thread(void *data) 9580 { 9581 /* Wait until other CPU entered L2 */ 9582 while (vmx_get_test_stage() != 1) 9583 ; 9584 9585 /* Set irq-line 0xf to raise vector 0x78 for vCPU 0 */ 9586 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9587 vmx_set_test_stage(2); 9588 } 9589 9590 static bool irq_78_handler_vmcall_before_eoi; 9591 static void irq_78_handler_guest(isr_regs_t *regs) 9592 { 9593 set_irq_line(0xf, 0); 9594 if (irq_78_handler_vmcall_before_eoi) 9595 vmcall(); 9596 eoi(); 9597 vmcall(); 9598 } 9599 9600 static void vmx_apic_passthrough_guest(void) 9601 { 9602 handle_irq(0x78, irq_78_handler_guest); 9603 irq_enable(); 9604 9605 /* If requested, wait for other CPU to trigger ioapic scan */ 9606 if (vmx_get_test_stage() < 1) { 9607 vmx_set_test_stage(1); 9608 while (vmx_get_test_stage() != 2) 9609 ; 9610 } 9611 9612 set_irq_line(0xf, 1); 9613 } 9614 9615 static void vmx_apic_passthrough(bool set_irq_line_from_thread) 9616 { 9617 if (set_irq_line_from_thread && (cpu_count() < 2)) { 9618 report_skip(__func__); 9619 return; 9620 } 9621 9622 /* Test device is required for generating IRQs */ 9623 if (!test_device_enabled()) { 9624 report_skip(__func__); 9625 return; 9626 } 9627 u64 cpu_ctrl_0 = CPU_SECONDARY; 9628 u64 cpu_ctrl_1 = 0; 9629 9630 disable_intercept_for_x2apic_msrs(); 9631 9632 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9633 9634 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9635 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9636 9637 if (set_irq_line_from_thread) { 9638 irq_78_handler_vmcall_before_eoi = false; 9639 on_cpu_async(1, set_irq_line_thread, NULL); 9640 } else { 9641 irq_78_handler_vmcall_before_eoi = true; 9642 ioapic_set_redir(0xf, 0x78, TRIGGER_LEVEL); 9643 vmx_set_test_stage(2); 9644 } 9645 test_set_guest(vmx_apic_passthrough_guest); 9646 9647 if (irq_78_handler_vmcall_before_eoi) { 9648 /* Before EOI remote_irr should still be set */ 9649 enter_guest(); 9650 skip_exit_vmcall(); 9651 TEST_ASSERT_EQ_MSG(1, (int)ioapic_read_redir(0xf).remote_irr, 9652 "IOAPIC pass-through: remote_irr=1 before EOI"); 9653 } 9654 9655 /* After EOI remote_irr should be cleared */ 9656 enter_guest(); 9657 skip_exit_vmcall(); 9658 TEST_ASSERT_EQ_MSG(0, (int)ioapic_read_redir(0xf).remote_irr, 9659 "IOAPIC pass-through: remote_irr=0 after EOI"); 9660 9661 /* Let L2 finish */ 9662 enter_guest(); 9663 report_pass(__func__); 9664 } 9665 9666 static void vmx_apic_passthrough_test(void) 9667 { 9668 vmx_apic_passthrough(false); 9669 } 9670 9671 static void vmx_apic_passthrough_thread_test(void) 9672 { 9673 vmx_apic_passthrough(true); 9674 } 9675 9676 static void vmx_apic_passthrough_tpr_threshold_guest(void) 9677 { 9678 cli(); 9679 apic_set_tpr(0); 9680 } 9681 9682 static bool vmx_apic_passthrough_tpr_threshold_ipi_isr_fired; 9683 static void vmx_apic_passthrough_tpr_threshold_ipi_isr(isr_regs_t *regs) 9684 { 9685 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = true; 9686 eoi(); 9687 } 9688 9689 static void vmx_apic_passthrough_tpr_threshold_test(void) 9690 { 9691 int ipi_vector = 0xe1; 9692 9693 disable_intercept_for_x2apic_msrs(); 9694 vmcs_clear_bits(PIN_CONTROLS, PIN_EXTINT); 9695 9696 /* Raise L0 TPR-threshold by queueing vector in LAPIC IRR */ 9697 cli(); 9698 apic_set_tpr((ipi_vector >> 4) + 1); 9699 apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | 9700 APIC_DM_FIXED | ipi_vector, 9701 0); 9702 9703 test_set_guest(vmx_apic_passthrough_tpr_threshold_guest); 9704 enter_guest(); 9705 9706 report(apic_get_tpr() == 0, "TPR was zero by guest"); 9707 9708 /* Clean pending self-IPI */ 9709 vmx_apic_passthrough_tpr_threshold_ipi_isr_fired = false; 9710 handle_irq(ipi_vector, vmx_apic_passthrough_tpr_threshold_ipi_isr); 9711 sti(); 9712 asm volatile ("nop"); 9713 report(vmx_apic_passthrough_tpr_threshold_ipi_isr_fired, "self-IPI fired"); 9714 9715 report_pass(__func__); 9716 } 9717 9718 static u64 init_signal_test_exit_reason; 9719 static bool init_signal_test_thread_continued; 9720 9721 static void init_signal_test_thread(void *data) 9722 { 9723 struct vmcs *test_vmcs = data; 9724 9725 /* Enter VMX operation (i.e. exec VMXON) */ 9726 u64 *ap_vmxon_region = alloc_page(); 9727 enable_vmx(); 9728 init_vmx(ap_vmxon_region); 9729 _vmx_on(ap_vmxon_region); 9730 9731 /* Signal CPU have entered VMX operation */ 9732 vmx_set_test_stage(1); 9733 9734 /* Wait for BSP CPU to send INIT signal */ 9735 while (vmx_get_test_stage() != 2) 9736 ; 9737 9738 /* 9739 * Signal that we continue as usual as INIT signal 9740 * should be blocked while CPU is in VMX operation 9741 */ 9742 vmx_set_test_stage(3); 9743 9744 /* Wait for signal to enter VMX non-root mode */ 9745 while (vmx_get_test_stage() != 4) 9746 ; 9747 9748 /* Enter VMX non-root mode */ 9749 test_set_guest(v2_null_test_guest); 9750 make_vmcs_current(test_vmcs); 9751 enter_guest(); 9752 /* Save exit reason for BSP CPU to compare to expected result */ 9753 init_signal_test_exit_reason = vmcs_read(EXI_REASON); 9754 /* VMCLEAR test-vmcs so it could be loaded by BSP CPU */ 9755 vmcs_clear(test_vmcs); 9756 launched = false; 9757 /* Signal that CPU exited to VMX root mode */ 9758 vmx_set_test_stage(5); 9759 9760 /* Wait for BSP CPU to signal to exit VMX operation */ 9761 while (vmx_get_test_stage() != 6) 9762 ; 9763 9764 /* Exit VMX operation (i.e. exec VMXOFF) */ 9765 vmx_off(); 9766 9767 /* 9768 * Signal to BSP CPU that we continue as usual as INIT signal 9769 * should have been consumed by VMX_INIT exit from guest 9770 */ 9771 vmx_set_test_stage(7); 9772 9773 /* Wait for BSP CPU to signal to enter VMX operation */ 9774 while (vmx_get_test_stage() != 8) 9775 ; 9776 /* Enter VMX operation (i.e. exec VMXON) */ 9777 _vmx_on(ap_vmxon_region); 9778 /* Signal to BSP we are in VMX operation */ 9779 vmx_set_test_stage(9); 9780 9781 /* Wait for BSP CPU to send INIT signal */ 9782 while (vmx_get_test_stage() != 10) 9783 ; 9784 9785 /* Exit VMX operation (i.e. exec VMXOFF) */ 9786 vmx_off(); 9787 9788 /* 9789 * Exiting VMX operation should result in latched 9790 * INIT signal being processed. Therefore, we should 9791 * never reach the below code. Thus, signal to BSP 9792 * CPU if we have reached here so it is able to 9793 * report an issue if it happens. 9794 */ 9795 init_signal_test_thread_continued = true; 9796 } 9797 9798 #define INIT_SIGNAL_TEST_DELAY 100000000ULL 9799 9800 static void vmx_init_signal_test(void) 9801 { 9802 struct vmcs *test_vmcs; 9803 9804 if (cpu_count() < 2) { 9805 report_skip(__func__); 9806 return; 9807 } 9808 9809 /* VMCLEAR test-vmcs so it could be loaded by other CPU */ 9810 vmcs_save(&test_vmcs); 9811 vmcs_clear(test_vmcs); 9812 9813 vmx_set_test_stage(0); 9814 on_cpu_async(1, init_signal_test_thread, test_vmcs); 9815 9816 /* Wait for other CPU to enter VMX operation */ 9817 while (vmx_get_test_stage() != 1) 9818 ; 9819 9820 /* Send INIT signal to other CPU */ 9821 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9822 id_map[1]); 9823 /* Signal other CPU we have sent INIT signal */ 9824 vmx_set_test_stage(2); 9825 9826 /* 9827 * Wait reasonable amount of time for INIT signal to 9828 * be received on other CPU and verify that other CPU 9829 * have proceed as usual to next test stage as INIT 9830 * signal should be blocked while other CPU in 9831 * VMX operation 9832 */ 9833 delay(INIT_SIGNAL_TEST_DELAY); 9834 report(vmx_get_test_stage() == 3, 9835 "INIT signal blocked when CPU in VMX operation"); 9836 /* No point to continue if we failed at this point */ 9837 if (vmx_get_test_stage() != 3) 9838 return; 9839 9840 /* Signal other CPU to enter VMX non-root mode */ 9841 init_signal_test_exit_reason = -1ull; 9842 vmx_set_test_stage(4); 9843 /* 9844 * Wait reasonable amont of time for other CPU 9845 * to exit to VMX root mode 9846 */ 9847 delay(INIT_SIGNAL_TEST_DELAY); 9848 if (vmx_get_test_stage() != 5) { 9849 report_fail("Pending INIT signal didn't result in VMX exit"); 9850 return; 9851 } 9852 report(init_signal_test_exit_reason == VMX_INIT, 9853 "INIT signal during VMX non-root mode result in exit-reason %s (%lu)", 9854 exit_reason_description(init_signal_test_exit_reason), 9855 init_signal_test_exit_reason); 9856 9857 /* Run guest to completion */ 9858 make_vmcs_current(test_vmcs); 9859 enter_guest(); 9860 9861 /* Signal other CPU to exit VMX operation */ 9862 init_signal_test_thread_continued = false; 9863 vmx_set_test_stage(6); 9864 9865 /* Wait reasonable amount of time for other CPU to exit VMX operation */ 9866 delay(INIT_SIGNAL_TEST_DELAY); 9867 report(vmx_get_test_stage() == 7, 9868 "INIT signal consumed on VMX_INIT exit"); 9869 /* No point to continue if we failed at this point */ 9870 if (vmx_get_test_stage() != 7) 9871 return; 9872 9873 /* Signal other CPU to enter VMX operation */ 9874 vmx_set_test_stage(8); 9875 /* Wait for other CPU to enter VMX operation */ 9876 while (vmx_get_test_stage() != 9) 9877 ; 9878 9879 /* Send INIT signal to other CPU */ 9880 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_INIT | APIC_INT_ASSERT, 9881 id_map[1]); 9882 /* Signal other CPU we have sent INIT signal */ 9883 vmx_set_test_stage(10); 9884 9885 /* 9886 * Wait reasonable amount of time for other CPU 9887 * to exit VMX operation and process INIT signal 9888 */ 9889 delay(INIT_SIGNAL_TEST_DELAY); 9890 report(!init_signal_test_thread_continued, 9891 "INIT signal processed after exit VMX operation"); 9892 9893 /* 9894 * TODO: Send SIPI to other CPU to sipi_entry (See x86/cstart64.S) 9895 * to re-init it to kvm-unit-tests standard environment. 9896 * Somehow (?) verify that SIPI was indeed received. 9897 */ 9898 } 9899 9900 #define SIPI_SIGNAL_TEST_DELAY 100000000ULL 9901 9902 static void vmx_sipi_test_guest(void) 9903 { 9904 if (apic_id() == 0) { 9905 /* wait AP enter guest with activity=WAIT_SIPI */ 9906 while (vmx_get_test_stage() != 1) 9907 ; 9908 delay(SIPI_SIGNAL_TEST_DELAY); 9909 9910 /* First SIPI signal */ 9911 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9912 report_pass("BSP(L2): Send first SIPI to cpu[%d]", id_map[1]); 9913 9914 /* wait AP enter guest */ 9915 while (vmx_get_test_stage() != 2) 9916 ; 9917 delay(SIPI_SIGNAL_TEST_DELAY); 9918 9919 /* Second SIPI signal should be ignored since AP is not in WAIT_SIPI state */ 9920 apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_STARTUP | APIC_INT_ASSERT, id_map[1]); 9921 report_pass("BSP(L2): Send second SIPI to cpu[%d]", id_map[1]); 9922 9923 /* Delay a while to check whether second SIPI would cause VMExit */ 9924 delay(SIPI_SIGNAL_TEST_DELAY); 9925 9926 /* Test is done, notify AP to exit test */ 9927 vmx_set_test_stage(3); 9928 9929 /* wait AP exit non-root mode */ 9930 while (vmx_get_test_stage() != 5) 9931 ; 9932 } else { 9933 /* wait BSP notify test is done */ 9934 while (vmx_get_test_stage() != 3) 9935 ; 9936 9937 /* AP exit guest */ 9938 vmx_set_test_stage(4); 9939 } 9940 } 9941 9942 static void sipi_test_ap_thread(void *data) 9943 { 9944 struct vmcs *ap_vmcs; 9945 u64 *ap_vmxon_region; 9946 void *ap_stack, *ap_syscall_stack; 9947 u64 cpu_ctrl_0 = CPU_SECONDARY; 9948 u64 cpu_ctrl_1 = 0; 9949 9950 /* Enter VMX operation (i.e. exec VMXON) */ 9951 ap_vmxon_region = alloc_page(); 9952 enable_vmx(); 9953 init_vmx(ap_vmxon_region); 9954 _vmx_on(ap_vmxon_region); 9955 init_vmcs(&ap_vmcs); 9956 make_vmcs_current(ap_vmcs); 9957 9958 /* Set stack for AP */ 9959 ap_stack = alloc_page(); 9960 ap_syscall_stack = alloc_page(); 9961 vmcs_write(GUEST_RSP, (u64)(ap_stack + PAGE_SIZE - 1)); 9962 vmcs_write(GUEST_SYSENTER_ESP, (u64)(ap_syscall_stack + PAGE_SIZE - 1)); 9963 9964 /* passthrough lapic to L2 */ 9965 disable_intercept_for_x2apic_msrs(); 9966 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 9967 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 9968 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 9969 9970 /* Set guest activity state to wait-for-SIPI state */ 9971 vmcs_write(GUEST_ACTV_STATE, ACTV_WAIT_SIPI); 9972 9973 vmx_set_test_stage(1); 9974 9975 /* AP enter guest */ 9976 enter_guest(); 9977 9978 if (vmcs_read(EXI_REASON) == VMX_SIPI) { 9979 report_pass("AP: Handle SIPI VMExit"); 9980 vmcs_write(GUEST_ACTV_STATE, ACTV_ACTIVE); 9981 vmx_set_test_stage(2); 9982 } else { 9983 report_fail("AP: Unexpected VMExit, reason=%ld", vmcs_read(EXI_REASON)); 9984 vmx_off(); 9985 return; 9986 } 9987 9988 /* AP enter guest */ 9989 enter_guest(); 9990 9991 report(vmcs_read(EXI_REASON) != VMX_SIPI, 9992 "AP: should no SIPI VMExit since activity is not in WAIT_SIPI state"); 9993 9994 /* notify BSP that AP is already exit from non-root mode */ 9995 vmx_set_test_stage(5); 9996 9997 /* Leave VMX operation */ 9998 vmx_off(); 9999 } 10000 10001 static void vmx_sipi_signal_test(void) 10002 { 10003 if (!(rdmsr(MSR_IA32_VMX_MISC) & MSR_IA32_VMX_MISC_ACTIVITY_WAIT_SIPI)) { 10004 printf("\tACTIVITY_WAIT_SIPI state is not supported.\n"); 10005 return; 10006 } 10007 10008 if (cpu_count() < 2) { 10009 report_skip(__func__); 10010 return; 10011 } 10012 10013 u64 cpu_ctrl_0 = CPU_SECONDARY; 10014 u64 cpu_ctrl_1 = 0; 10015 10016 /* passthrough lapic to L2 */ 10017 disable_intercept_for_x2apic_msrs(); 10018 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) & ~PIN_EXTINT); 10019 vmcs_write(CPU_EXEC_CTRL0, vmcs_read(CPU_EXEC_CTRL0) | cpu_ctrl_0); 10020 vmcs_write(CPU_EXEC_CTRL1, vmcs_read(CPU_EXEC_CTRL1) | cpu_ctrl_1); 10021 10022 test_set_guest(vmx_sipi_test_guest); 10023 10024 /* update CR3 on AP */ 10025 on_cpu(1, update_cr3, (void *)read_cr3()); 10026 10027 /* start AP */ 10028 on_cpu_async(1, sipi_test_ap_thread, NULL); 10029 10030 vmx_set_test_stage(0); 10031 10032 /* BSP enter guest */ 10033 enter_guest(); 10034 } 10035 10036 10037 enum vmcs_access { 10038 ACCESS_VMREAD, 10039 ACCESS_VMWRITE, 10040 ACCESS_NONE, 10041 }; 10042 10043 struct vmcs_shadow_test_common { 10044 enum vmcs_access op; 10045 enum Reason reason; 10046 u64 field; 10047 u64 value; 10048 u64 flags; 10049 u64 time; 10050 } l1_l2_common; 10051 10052 static inline u64 vmread_flags(u64 field, u64 *val) 10053 { 10054 u64 flags; 10055 10056 asm volatile ("vmread %2, %1; pushf; pop %0" 10057 : "=r" (flags), "=rm" (*val) : "r" (field) : "cc"); 10058 return flags & X86_EFLAGS_ALU; 10059 } 10060 10061 static inline u64 vmwrite_flags(u64 field, u64 val) 10062 { 10063 u64 flags; 10064 10065 asm volatile ("vmwrite %1, %2; pushf; pop %0" 10066 : "=r"(flags) : "rm" (val), "r" (field) : "cc"); 10067 return flags & X86_EFLAGS_ALU; 10068 } 10069 10070 static void vmx_vmcs_shadow_test_guest(void) 10071 { 10072 struct vmcs_shadow_test_common *c = &l1_l2_common; 10073 u64 start; 10074 10075 while (c->op != ACCESS_NONE) { 10076 start = rdtsc(); 10077 switch (c->op) { 10078 default: 10079 c->flags = -1ull; 10080 break; 10081 case ACCESS_VMREAD: 10082 c->flags = vmread_flags(c->field, &c->value); 10083 break; 10084 case ACCESS_VMWRITE: 10085 c->flags = vmwrite_flags(c->field, 0); 10086 break; 10087 } 10088 c->time = rdtsc() - start; 10089 vmcall(); 10090 } 10091 } 10092 10093 static u64 vmread_from_shadow(u64 field) 10094 { 10095 struct vmcs *primary; 10096 struct vmcs *shadow; 10097 u64 value; 10098 10099 TEST_ASSERT(!vmcs_save(&primary)); 10100 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10101 TEST_ASSERT(!make_vmcs_current(shadow)); 10102 value = vmcs_read(field); 10103 TEST_ASSERT(!make_vmcs_current(primary)); 10104 return value; 10105 } 10106 10107 static u64 vmwrite_to_shadow(u64 field, u64 value) 10108 { 10109 struct vmcs *primary; 10110 struct vmcs *shadow; 10111 10112 TEST_ASSERT(!vmcs_save(&primary)); 10113 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10114 TEST_ASSERT(!make_vmcs_current(shadow)); 10115 vmcs_write(field, value); 10116 value = vmcs_read(field); 10117 TEST_ASSERT(!make_vmcs_current(primary)); 10118 return value; 10119 } 10120 10121 static void vmcs_shadow_test_access(u8 *bitmap[2], enum vmcs_access access) 10122 { 10123 struct vmcs_shadow_test_common *c = &l1_l2_common; 10124 10125 c->op = access; 10126 vmcs_write(VMX_INST_ERROR, 0); 10127 enter_guest(); 10128 c->reason = vmcs_read(EXI_REASON) & 0xffff; 10129 if (c->reason != VMX_VMCALL) { 10130 skip_exit_insn(); 10131 enter_guest(); 10132 } 10133 skip_exit_vmcall(); 10134 } 10135 10136 static void vmcs_shadow_test_field(u8 *bitmap[2], u64 field) 10137 { 10138 struct vmcs_shadow_test_common *c = &l1_l2_common; 10139 struct vmcs *shadow; 10140 u64 value; 10141 uintptr_t flags[2]; 10142 bool good_shadow; 10143 u32 vmx_inst_error; 10144 10145 report_prefix_pushf("field %lx", field); 10146 c->field = field; 10147 10148 shadow = (struct vmcs *)vmcs_read(VMCS_LINK_PTR); 10149 if (shadow != (struct vmcs *)-1ull) { 10150 flags[ACCESS_VMREAD] = vmread_flags(field, &value); 10151 flags[ACCESS_VMWRITE] = vmwrite_flags(field, value); 10152 good_shadow = !flags[ACCESS_VMREAD] && !flags[ACCESS_VMWRITE]; 10153 } else { 10154 /* 10155 * When VMCS link pointer is -1ull, VMWRITE/VMREAD on 10156 * shadowed-fields should fail with setting RFLAGS.CF. 10157 */ 10158 flags[ACCESS_VMREAD] = X86_EFLAGS_CF; 10159 flags[ACCESS_VMWRITE] = X86_EFLAGS_CF; 10160 good_shadow = false; 10161 } 10162 10163 /* Intercept both VMREAD and VMWRITE. */ 10164 report_prefix_push("no VMREAD/VMWRITE permission"); 10165 /* VMWRITE/VMREAD done on reserved-bit should always intercept */ 10166 if (!(field >> VMCS_FIELD_RESERVED_SHIFT)) { 10167 set_bit(field, bitmap[ACCESS_VMREAD]); 10168 set_bit(field, bitmap[ACCESS_VMWRITE]); 10169 } 10170 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10171 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10172 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10173 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10174 report_prefix_pop(); 10175 10176 if (field >> VMCS_FIELD_RESERVED_SHIFT) 10177 goto out; 10178 10179 /* Permit shadowed VMREAD. */ 10180 report_prefix_push("VMREAD permission only"); 10181 clear_bit(field, bitmap[ACCESS_VMREAD]); 10182 set_bit(field, bitmap[ACCESS_VMWRITE]); 10183 if (good_shadow) 10184 value = vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10185 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10186 report(c->reason == VMX_VMWRITE, "not shadowed for VMWRITE"); 10187 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10188 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10189 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10190 c->time); 10191 report(c->flags == flags[ACCESS_VMREAD], 10192 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10193 c->flags, flags[ACCESS_VMREAD]); 10194 if (good_shadow) 10195 report(c->value == value, 10196 "value read from shadow (%lx) is as expected (%lx)", 10197 c->value, value); 10198 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10199 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10200 "VMX_INST_ERROR (%d) is as expected (%d)", 10201 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10202 report_prefix_pop(); 10203 10204 /* Permit shadowed VMWRITE. */ 10205 report_prefix_push("VMWRITE permission only"); 10206 set_bit(field, bitmap[ACCESS_VMREAD]); 10207 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10208 if (good_shadow) 10209 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10210 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10211 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10212 report(c->reason == VMX_VMCALL, 10213 "shadowed for VMWRITE (in %ld cycles)", 10214 c->time); 10215 report(c->flags == flags[ACCESS_VMREAD], 10216 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10217 c->flags, flags[ACCESS_VMREAD]); 10218 if (good_shadow) { 10219 value = vmread_from_shadow(field); 10220 report(value == 0, 10221 "shadow VMCS value (%lx) is as expected (%lx)", value, 10222 0ul); 10223 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10224 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10225 "VMX_INST_ERROR (%d) is as expected (%d)", 10226 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10227 } 10228 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10229 report(c->reason == VMX_VMREAD, "not shadowed for VMREAD"); 10230 report_prefix_pop(); 10231 10232 /* Permit shadowed VMREAD and VMWRITE. */ 10233 report_prefix_push("VMREAD and VMWRITE permission"); 10234 clear_bit(field, bitmap[ACCESS_VMREAD]); 10235 clear_bit(field, bitmap[ACCESS_VMWRITE]); 10236 if (good_shadow) 10237 vmwrite_to_shadow(field, MAGIC_VAL_1 + field); 10238 vmcs_shadow_test_access(bitmap, ACCESS_VMWRITE); 10239 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10240 report(c->reason == VMX_VMCALL, 10241 "shadowed for VMWRITE (in %ld cycles)", 10242 c->time); 10243 report(c->flags == flags[ACCESS_VMREAD], 10244 "ALU flags after VMWRITE (%lx) are as expected (%lx)", 10245 c->flags, flags[ACCESS_VMREAD]); 10246 if (good_shadow) { 10247 value = vmread_from_shadow(field); 10248 report(value == 0, 10249 "shadow VMCS value (%lx) is as expected (%lx)", value, 10250 0ul); 10251 } else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMWRITE]) { 10252 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10253 "VMX_INST_ERROR (%d) is as expected (%d)", 10254 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10255 } 10256 vmcs_shadow_test_access(bitmap, ACCESS_VMREAD); 10257 vmx_inst_error = vmcs_read(VMX_INST_ERROR); 10258 report(c->reason == VMX_VMCALL, "shadowed for VMREAD (in %ld cycles)", 10259 c->time); 10260 report(c->flags == flags[ACCESS_VMREAD], 10261 "ALU flags after VMREAD (%lx) are as expected (%lx)", 10262 c->flags, flags[ACCESS_VMREAD]); 10263 if (good_shadow) 10264 report(c->value == 0, 10265 "value read from shadow (%lx) is as expected (%lx)", 10266 c->value, 0ul); 10267 else if (shadow != (struct vmcs *)-1ull && flags[ACCESS_VMREAD]) 10268 report(vmx_inst_error == VMXERR_UNSUPPORTED_VMCS_COMPONENT, 10269 "VMX_INST_ERROR (%d) is as expected (%d)", 10270 vmx_inst_error, VMXERR_UNSUPPORTED_VMCS_COMPONENT); 10271 report_prefix_pop(); 10272 10273 out: 10274 report_prefix_pop(); 10275 } 10276 10277 static void vmx_vmcs_shadow_test_body(u8 *bitmap[2]) 10278 { 10279 unsigned base; 10280 unsigned index; 10281 unsigned bit; 10282 unsigned highest_index = rdmsr(MSR_IA32_VMX_VMCS_ENUM); 10283 10284 /* Run test on all possible valid VMCS fields */ 10285 for (base = 0; 10286 base < (1 << VMCS_FIELD_RESERVED_SHIFT); 10287 base += (1 << VMCS_FIELD_TYPE_SHIFT)) 10288 for (index = 0; index <= highest_index; index++) 10289 vmcs_shadow_test_field(bitmap, base + index); 10290 10291 /* 10292 * Run tests on some invalid VMCS fields 10293 * (Have reserved bit set). 10294 */ 10295 for (bit = VMCS_FIELD_RESERVED_SHIFT; bit < VMCS_FIELD_BIT_SIZE; bit++) 10296 vmcs_shadow_test_field(bitmap, (1ull << bit)); 10297 } 10298 10299 static void vmx_vmcs_shadow_test(void) 10300 { 10301 u8 *bitmap[2]; 10302 struct vmcs *shadow; 10303 10304 if (!(ctrl_cpu_rev[0].clr & CPU_SECONDARY)) { 10305 printf("\t'Activate secondary controls' not supported.\n"); 10306 return; 10307 } 10308 10309 if (!(ctrl_cpu_rev[1].clr & CPU_SHADOW_VMCS)) { 10310 printf("\t'VMCS shadowing' not supported.\n"); 10311 return; 10312 } 10313 10314 if (!(rdmsr(MSR_IA32_VMX_MISC) & 10315 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS)) { 10316 printf("\tVMWRITE can't modify VM-exit information fields.\n"); 10317 return; 10318 } 10319 10320 test_set_guest(vmx_vmcs_shadow_test_guest); 10321 10322 bitmap[ACCESS_VMREAD] = alloc_page(); 10323 bitmap[ACCESS_VMWRITE] = alloc_page(); 10324 10325 vmcs_write(VMREAD_BITMAP, virt_to_phys(bitmap[ACCESS_VMREAD])); 10326 vmcs_write(VMWRITE_BITMAP, virt_to_phys(bitmap[ACCESS_VMWRITE])); 10327 10328 shadow = alloc_page(); 10329 shadow->hdr.revision_id = basic.revision; 10330 shadow->hdr.shadow_vmcs = 1; 10331 TEST_ASSERT(!vmcs_clear(shadow)); 10332 10333 vmcs_clear_bits(CPU_EXEC_CTRL0, CPU_RDTSC); 10334 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_SECONDARY); 10335 vmcs_set_bits(CPU_EXEC_CTRL1, CPU_SHADOW_VMCS); 10336 10337 vmcs_write(VMCS_LINK_PTR, virt_to_phys(shadow)); 10338 report_prefix_push("valid link pointer"); 10339 vmx_vmcs_shadow_test_body(bitmap); 10340 report_prefix_pop(); 10341 10342 vmcs_write(VMCS_LINK_PTR, -1ull); 10343 report_prefix_push("invalid link pointer"); 10344 vmx_vmcs_shadow_test_body(bitmap); 10345 report_prefix_pop(); 10346 10347 l1_l2_common.op = ACCESS_NONE; 10348 enter_guest(); 10349 } 10350 10351 /* 10352 * This test monitors the difference between a guest RDTSC instruction 10353 * and the IA32_TIME_STAMP_COUNTER MSR value stored in the VMCS12 10354 * VM-exit MSR-store list when taking a VM-exit on the instruction 10355 * following RDTSC. 10356 */ 10357 #define RDTSC_DIFF_ITERS 100000 10358 #define RDTSC_DIFF_FAILS 100 10359 #define HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD 750 10360 10361 /* 10362 * Set 'use TSC offsetting' and set the guest offset to the 10363 * inverse of the host's current TSC value, so that the guest starts running 10364 * with an effective TSC value of 0. 10365 */ 10366 static void reset_guest_tsc_to_zero(void) 10367 { 10368 vmcs_set_bits(CPU_EXEC_CTRL0, CPU_USE_TSC_OFFSET); 10369 vmcs_write(TSC_OFFSET, -rdtsc()); 10370 } 10371 10372 static void rdtsc_vmexit_diff_test_guest(void) 10373 { 10374 int i; 10375 10376 for (i = 0; i < RDTSC_DIFF_ITERS; i++) 10377 /* Ensure rdtsc is the last instruction before the vmcall. */ 10378 asm volatile("rdtsc; vmcall" : : : "eax", "edx"); 10379 } 10380 10381 /* 10382 * This function only considers the "use TSC offsetting" VM-execution 10383 * control. It does not handle "use TSC scaling" (because the latter 10384 * isn't available to the host today.) 10385 */ 10386 static unsigned long long host_time_to_guest_time(unsigned long long t) 10387 { 10388 TEST_ASSERT(!(ctrl_cpu_rev[0].clr & CPU_SECONDARY) || 10389 !(vmcs_read(CPU_EXEC_CTRL1) & CPU_USE_TSC_SCALING)); 10390 10391 if (vmcs_read(CPU_EXEC_CTRL0) & CPU_USE_TSC_OFFSET) 10392 t += vmcs_read(TSC_OFFSET); 10393 10394 return t; 10395 } 10396 10397 static unsigned long long rdtsc_vmexit_diff_test_iteration(void) 10398 { 10399 unsigned long long guest_tsc, host_to_guest_tsc; 10400 10401 enter_guest(); 10402 skip_exit_vmcall(); 10403 guest_tsc = (u32) regs.rax + (regs.rdx << 32); 10404 host_to_guest_tsc = host_time_to_guest_time(exit_msr_store[0].value); 10405 10406 return host_to_guest_tsc - guest_tsc; 10407 } 10408 10409 static void rdtsc_vmexit_diff_test(void) 10410 { 10411 unsigned long long delta; 10412 int fail = 0; 10413 int i; 10414 10415 if (!(ctrl_cpu_rev[0].clr & CPU_USE_TSC_OFFSET)) 10416 test_skip("CPU doesn't support the 'use TSC offsetting' processor-based VM-execution control.\n"); 10417 10418 test_set_guest(rdtsc_vmexit_diff_test_guest); 10419 10420 reset_guest_tsc_to_zero(); 10421 10422 /* 10423 * Set up the VMCS12 VM-exit MSR-store list to store just one 10424 * MSR: IA32_TIME_STAMP_COUNTER. Note that the value stored is 10425 * in the host time domain (i.e., it is not adjusted according 10426 * to the TSC multiplier and TSC offset fields in the VMCS12, 10427 * as a guest RDTSC would be.) 10428 */ 10429 exit_msr_store = alloc_page(); 10430 exit_msr_store[0].index = MSR_IA32_TSC; 10431 vmcs_write(EXI_MSR_ST_CNT, 1); 10432 vmcs_write(EXIT_MSR_ST_ADDR, virt_to_phys(exit_msr_store)); 10433 10434 for (i = 0; i < RDTSC_DIFF_ITERS && fail < RDTSC_DIFF_FAILS; i++) { 10435 delta = rdtsc_vmexit_diff_test_iteration(); 10436 if (delta >= HOST_CAPTURED_GUEST_TSC_DIFF_THRESHOLD) 10437 fail++; 10438 } 10439 10440 enter_guest(); 10441 10442 report(fail < RDTSC_DIFF_FAILS, 10443 "RDTSC to VM-exit delta too high in %d of %d iterations, last = %llu", 10444 fail, i, delta); 10445 } 10446 10447 static int invalid_msr_init(struct vmcs *vmcs) 10448 { 10449 if (!(ctrl_pin_rev.clr & PIN_PREEMPT)) { 10450 printf("\tPreemption timer is not supported\n"); 10451 return VMX_TEST_EXIT; 10452 } 10453 vmcs_write(PIN_CONTROLS, vmcs_read(PIN_CONTROLS) | PIN_PREEMPT); 10454 preempt_val = 10000000; 10455 vmcs_write(PREEMPT_TIMER_VALUE, preempt_val); 10456 preempt_scale = rdmsr(MSR_IA32_VMX_MISC) & 0x1F; 10457 10458 if (!(ctrl_exit_rev.clr & EXI_SAVE_PREEMPT)) 10459 printf("\tSave preemption value is not supported\n"); 10460 10461 vmcs_write(ENT_MSR_LD_CNT, 1); 10462 vmcs_write(ENTER_MSR_LD_ADDR, (u64)0x13370000); 10463 10464 return VMX_TEST_START; 10465 } 10466 10467 10468 static void invalid_msr_main(void) 10469 { 10470 report_fail("Invalid MSR load"); 10471 } 10472 10473 static int invalid_msr_exit_handler(union exit_reason exit_reason) 10474 { 10475 report_fail("Invalid MSR load"); 10476 print_vmexit_info(exit_reason); 10477 return VMX_TEST_EXIT; 10478 } 10479 10480 static int invalid_msr_entry_failure(struct vmentry_result *result) 10481 { 10482 report(result->exit_reason.failed_vmentry && 10483 result->exit_reason.basic == VMX_FAIL_MSR, "Invalid MSR load"); 10484 return VMX_TEST_VMEXIT; 10485 } 10486 10487 /* 10488 * The max number of MSRs in an atomic switch MSR list is: 10489 * (111B + 1) * 512 = 4096 10490 * 10491 * Each list entry consumes: 10492 * 4-byte MSR index + 4 bytes reserved + 8-byte data = 16 bytes 10493 * 10494 * Allocate 128 kB to cover max_msr_list_size (i.e., 64 kB) and then some. 10495 */ 10496 static const u32 msr_list_page_order = 5; 10497 10498 static void atomic_switch_msr_limit_test_guest(void) 10499 { 10500 vmcall(); 10501 } 10502 10503 static void populate_msr_list(struct vmx_msr_entry *msr_list, 10504 size_t byte_capacity, int count) 10505 { 10506 int i; 10507 10508 for (i = 0; i < count; i++) { 10509 msr_list[i].index = MSR_IA32_TSC; 10510 msr_list[i].reserved = 0; 10511 msr_list[i].value = 0x1234567890abcdef; 10512 } 10513 10514 memset(msr_list + count, 0xff, 10515 byte_capacity - count * sizeof(*msr_list)); 10516 } 10517 10518 static int max_msr_list_size(void) 10519 { 10520 u32 vmx_misc = rdmsr(MSR_IA32_VMX_MISC); 10521 u32 factor = ((vmx_misc & GENMASK(27, 25)) >> 25) + 1; 10522 10523 return factor * 512; 10524 } 10525 10526 static void atomic_switch_msrs_test(int count) 10527 { 10528 struct vmx_msr_entry *vm_enter_load; 10529 struct vmx_msr_entry *vm_exit_load; 10530 struct vmx_msr_entry *vm_exit_store; 10531 int max_allowed = max_msr_list_size(); 10532 int byte_capacity = 1ul << (msr_list_page_order + PAGE_SHIFT); 10533 /* Exceeding the max MSR list size at exit trigers KVM to abort. */ 10534 int exit_count = count > max_allowed ? max_allowed : count; 10535 int cleanup_count = count > max_allowed ? 2 : 1; 10536 int i; 10537 10538 /* 10539 * Check for the IA32_TSC MSR, 10540 * available with the "TSC flag" and used to populate the MSR lists. 10541 */ 10542 if (!(cpuid(1).d & (1 << 4))) { 10543 report_skip(__func__); 10544 return; 10545 } 10546 10547 /* Set L2 guest. */ 10548 test_set_guest(atomic_switch_msr_limit_test_guest); 10549 10550 /* Setup atomic MSR switch lists. */ 10551 vm_enter_load = alloc_pages(msr_list_page_order); 10552 vm_exit_load = alloc_pages(msr_list_page_order); 10553 vm_exit_store = alloc_pages(msr_list_page_order); 10554 10555 vmcs_write(ENTER_MSR_LD_ADDR, (u64)vm_enter_load); 10556 vmcs_write(EXIT_MSR_LD_ADDR, (u64)vm_exit_load); 10557 vmcs_write(EXIT_MSR_ST_ADDR, (u64)vm_exit_store); 10558 10559 /* 10560 * VM-Enter should succeed up to the max number of MSRs per list, and 10561 * should not consume junk beyond the last entry. 10562 */ 10563 populate_msr_list(vm_enter_load, byte_capacity, count); 10564 populate_msr_list(vm_exit_load, byte_capacity, exit_count); 10565 populate_msr_list(vm_exit_store, byte_capacity, exit_count); 10566 10567 vmcs_write(ENT_MSR_LD_CNT, count); 10568 vmcs_write(EXI_MSR_LD_CNT, exit_count); 10569 vmcs_write(EXI_MSR_ST_CNT, exit_count); 10570 10571 if (count <= max_allowed) { 10572 enter_guest(); 10573 assert_exit_reason(VMX_VMCALL); 10574 skip_exit_vmcall(); 10575 } else { 10576 u32 exit_qual; 10577 10578 test_guest_state("Invalid MSR Load Count", true, count, 10579 "ENT_MSR_LD_CNT"); 10580 10581 exit_qual = vmcs_read(EXI_QUALIFICATION); 10582 report(exit_qual == max_allowed + 1, "exit_qual, %u, is %u.", 10583 exit_qual, max_allowed + 1); 10584 } 10585 10586 /* Cleanup. */ 10587 vmcs_write(ENT_MSR_LD_CNT, 0); 10588 vmcs_write(EXI_MSR_LD_CNT, 0); 10589 vmcs_write(EXI_MSR_ST_CNT, 0); 10590 for (i = 0; i < cleanup_count; i++) { 10591 enter_guest(); 10592 skip_exit_vmcall(); 10593 } 10594 free_pages_by_order(vm_enter_load, msr_list_page_order); 10595 free_pages_by_order(vm_exit_load, msr_list_page_order); 10596 free_pages_by_order(vm_exit_store, msr_list_page_order); 10597 } 10598 10599 static void atomic_switch_max_msrs_test(void) 10600 { 10601 atomic_switch_msrs_test(max_msr_list_size()); 10602 } 10603 10604 static void atomic_switch_overflow_msrs_test(void) 10605 { 10606 if (test_device_enabled()) 10607 atomic_switch_msrs_test(max_msr_list_size() + 1); 10608 else 10609 test_skip("Test is only supported on KVM"); 10610 } 10611 10612 static void vmx_pf_exception_test_guest(void) 10613 { 10614 ac_test_run(PT_LEVEL_PML4); 10615 } 10616 10617 static void vmx_pf_exception_test(void) 10618 { 10619 u64 efer; 10620 struct cpuid cpuid; 10621 10622 test_set_guest(vmx_pf_exception_test_guest); 10623 10624 enter_guest(); 10625 10626 while (vmcs_read(EXI_REASON) != VMX_VMCALL) { 10627 switch (vmcs_read(EXI_REASON)) { 10628 case VMX_RDMSR: 10629 assert(regs.rcx == MSR_EFER); 10630 efer = vmcs_read(GUEST_EFER); 10631 regs.rdx = efer >> 32; 10632 regs.rax = efer & 0xffffffff; 10633 break; 10634 case VMX_WRMSR: 10635 assert(regs.rcx == MSR_EFER); 10636 efer = regs.rdx << 32 | (regs.rax & 0xffffffff); 10637 vmcs_write(GUEST_EFER, efer); 10638 break; 10639 case VMX_CPUID: 10640 cpuid = (struct cpuid) {0, 0, 0, 0}; 10641 cpuid = raw_cpuid(regs.rax, regs.rcx); 10642 regs.rax = cpuid.a; 10643 regs.rbx = cpuid.b; 10644 regs.rcx = cpuid.c; 10645 regs.rdx = cpuid.d; 10646 break; 10647 default: 10648 assert_msg(false, 10649 "Unexpected exit to L1, exit_reason: %s (0x%lx)", 10650 exit_reason_description(vmcs_read(EXI_REASON)), 10651 vmcs_read(EXI_REASON)); 10652 } 10653 skip_exit_insn(); 10654 enter_guest(); 10655 } 10656 10657 assert_exit_reason(VMX_VMCALL); 10658 } 10659 #define TEST(name) { #name, .v2 = name } 10660 10661 /* name/init/guest_main/exit_handler/syscall_handler/guest_regs */ 10662 struct vmx_test vmx_tests[] = { 10663 { "null", NULL, basic_guest_main, basic_exit_handler, NULL, {0} }, 10664 { "vmenter", NULL, vmenter_main, vmenter_exit_handler, NULL, {0} }, 10665 { "preemption timer", preemption_timer_init, preemption_timer_main, 10666 preemption_timer_exit_handler, NULL, {0} }, 10667 { "control field PAT", test_ctrl_pat_init, test_ctrl_pat_main, 10668 test_ctrl_pat_exit_handler, NULL, {0} }, 10669 { "control field EFER", test_ctrl_efer_init, test_ctrl_efer_main, 10670 test_ctrl_efer_exit_handler, NULL, {0} }, 10671 { "CR shadowing", NULL, cr_shadowing_main, 10672 cr_shadowing_exit_handler, NULL, {0} }, 10673 { "I/O bitmap", iobmp_init, iobmp_main, iobmp_exit_handler, 10674 NULL, {0} }, 10675 { "instruction intercept", insn_intercept_init, insn_intercept_main, 10676 insn_intercept_exit_handler, NULL, {0} }, 10677 { "EPT A/D disabled", ept_init, ept_main, ept_exit_handler, NULL, {0} }, 10678 { "EPT A/D enabled", eptad_init, eptad_main, eptad_exit_handler, NULL, {0} }, 10679 { "PML", pml_init, pml_main, pml_exit_handler, NULL, {0} }, 10680 { "interrupt", interrupt_init, interrupt_main, 10681 interrupt_exit_handler, NULL, {0} }, 10682 { "nmi_hlt", nmi_hlt_init, nmi_hlt_main, 10683 nmi_hlt_exit_handler, NULL, {0} }, 10684 { "debug controls", dbgctls_init, dbgctls_main, dbgctls_exit_handler, 10685 NULL, {0} }, 10686 { "MSR switch", msr_switch_init, msr_switch_main, 10687 msr_switch_exit_handler, NULL, {0}, msr_switch_entry_failure }, 10688 { "vmmcall", vmmcall_init, vmmcall_main, vmmcall_exit_handler, NULL, {0} }, 10689 { "disable RDTSCP", disable_rdtscp_init, disable_rdtscp_main, 10690 disable_rdtscp_exit_handler, NULL, {0} }, 10691 { "int3", int3_init, int3_guest_main, int3_exit_handler, NULL, {0} }, 10692 { "into", into_init, into_guest_main, into_exit_handler, NULL, {0} }, 10693 { "exit_monitor_from_l2_test", NULL, exit_monitor_from_l2_main, 10694 exit_monitor_from_l2_handler, NULL, {0} }, 10695 { "invalid_msr", invalid_msr_init, invalid_msr_main, 10696 invalid_msr_exit_handler, NULL, {0}, invalid_msr_entry_failure}, 10697 /* Basic V2 tests. */ 10698 TEST(v2_null_test), 10699 TEST(v2_multiple_entries_test), 10700 TEST(fixture_test_case1), 10701 TEST(fixture_test_case2), 10702 /* Opcode tests. */ 10703 TEST(invvpid_test), 10704 /* VM-entry tests */ 10705 TEST(vmx_controls_test), 10706 TEST(vmx_host_state_area_test), 10707 TEST(vmx_guest_state_area_test), 10708 TEST(vmentry_movss_shadow_test), 10709 TEST(vmentry_unrestricted_guest_test), 10710 /* APICv tests */ 10711 TEST(vmx_eoi_bitmap_ioapic_scan_test), 10712 TEST(vmx_hlt_with_rvi_test), 10713 TEST(apic_reg_virt_test), 10714 TEST(virt_x2apic_mode_test), 10715 /* APIC pass-through tests */ 10716 TEST(vmx_apic_passthrough_test), 10717 TEST(vmx_apic_passthrough_thread_test), 10718 TEST(vmx_apic_passthrough_tpr_threshold_test), 10719 TEST(vmx_init_signal_test), 10720 TEST(vmx_sipi_signal_test), 10721 /* VMCS Shadowing tests */ 10722 TEST(vmx_vmcs_shadow_test), 10723 /* Regression tests */ 10724 TEST(vmx_ldtr_test), 10725 TEST(vmx_cr_load_test), 10726 TEST(vmx_cr4_osxsave_test), 10727 TEST(vmx_nm_test), 10728 TEST(vmx_db_test), 10729 TEST(vmx_nmi_window_test), 10730 TEST(vmx_intr_window_test), 10731 TEST(vmx_pending_event_test), 10732 TEST(vmx_pending_event_hlt_test), 10733 TEST(vmx_store_tsc_test), 10734 TEST(vmx_preemption_timer_zero_test), 10735 TEST(vmx_preemption_timer_tf_test), 10736 TEST(vmx_preemption_timer_expiry_test), 10737 /* EPT access tests. */ 10738 TEST(ept_access_test_not_present), 10739 TEST(ept_access_test_read_only), 10740 TEST(ept_access_test_write_only), 10741 TEST(ept_access_test_read_write), 10742 TEST(ept_access_test_execute_only), 10743 TEST(ept_access_test_read_execute), 10744 TEST(ept_access_test_write_execute), 10745 TEST(ept_access_test_read_write_execute), 10746 TEST(ept_access_test_reserved_bits), 10747 TEST(ept_access_test_ignored_bits), 10748 TEST(ept_access_test_paddr_not_present_ad_disabled), 10749 TEST(ept_access_test_paddr_not_present_ad_enabled), 10750 TEST(ept_access_test_paddr_read_only_ad_disabled), 10751 TEST(ept_access_test_paddr_read_only_ad_enabled), 10752 TEST(ept_access_test_paddr_read_write), 10753 TEST(ept_access_test_paddr_read_write_execute), 10754 TEST(ept_access_test_paddr_read_execute_ad_disabled), 10755 TEST(ept_access_test_paddr_read_execute_ad_enabled), 10756 TEST(ept_access_test_paddr_not_present_page_fault), 10757 TEST(ept_access_test_force_2m_page), 10758 /* Atomic MSR switch tests. */ 10759 TEST(atomic_switch_max_msrs_test), 10760 TEST(atomic_switch_overflow_msrs_test), 10761 TEST(rdtsc_vmexit_diff_test), 10762 TEST(vmx_mtf_test), 10763 TEST(vmx_mtf_pdpte_test), 10764 TEST(vmx_pf_exception_test), 10765 { NULL, NULL, NULL, NULL, NULL, {0} }, 10766 }; 10767